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1. 发明授权

US06645797B1 Method for forming fins in a FinFET device using sacrificial carbon layer 有权
标题翻译：在使用牺牲碳层的FinFET器件中形成翅片的方法
公开(公告)号：US06645797B1
公开(公告)日：2003-11-11
申请号：US10310926
申请日：2002-12-06
申请人： Matthew S. Buynoski , Srikanteswara Dakshina-Murthy , Cyrus E. Tabery , Haihong Wang , Chih-Yuh Yang , Bin Yu
发明人： Matthew S. Buynoski , Srikanteswara Dakshina-Murthy , Cyrus E. Tabery , Haihong Wang , Chih-Yuh Yang , Bin Yu
IPC分类号： H01L2184
CPC分类号： H01L29/785 , H01L29/66795
摘要： A method for forming a fin in a semiconductor device that includes a substrate, an insulating layer formed on the substrate, and a conductive layer formed on the insulating layer, includes forming a carbon layer over the conductive layer and forming a mask over the carbon layer. The method further includes etching the mask and carbon layer to form at least one structure, where the structure has a first width, reducing the width of the carbon layer in the at least one structure to a second width, depositing an oxide layer to surround the at least one structure, removing a portion of the oxide layer and the mask, removing the carbon layer to form an opening in a remaining portion of the oxide layer for each of the at least one structure, filling the at least one opening with conductive material, and removing the remaining portion of the oxide layer and a portion of the conductive layer to form the fin.
摘要翻译：一种在半导体器件中形成翅片的方法，包括：衬底，形成在衬底上的绝缘层和形成在绝缘层上的导电层，包括在导电层上形成碳层，并在碳层上形成掩模。该方法还包括蚀刻掩模和碳层以形成至少一种结构，其中结构具有第一宽度，将至少一个结构中的碳层的宽度减小到第二宽度，沉积氧化物层以围绕至少一个结构，去除所述氧化物层和所述掩模的一部分，除去所述碳层以在所述至少一个结构中的每一个结构的氧化物层的剩余部分中形成开口，用导电材料填充所述至少一个开口并且去除氧化物层的剩余部分和导电层的一部分以形成翅片。

2. 发明授权

US07029958B2 Self aligned damascene gate 有权
标题翻译：自对准镶嵌门
公开(公告)号：US07029958B2
公开(公告)日：2006-04-18
申请号：US10699887
申请日：2003-11-04
申请人： Cyrus E. Tabery , Shibly S. Ahmed , Matthew S. Buynoski , Srikanteswara Dakshina-Murthy , Zoran Krivokapic , Haihong Wang , Chih-Yuh Yang , Bin Yu
发明人： Cyrus E. Tabery , Shibly S. Ahmed , Matthew S. Buynoski , Srikanteswara Dakshina-Murthy , Zoran Krivokapic , Haihong Wang , Chih-Yuh Yang , Bin Yu
IPC分类号： H01L21/00
CPC分类号： H01L29/785 , H01L29/66818 , H01L29/7842
摘要： A method for forming a metal-oxide semiconductor field-effect transistor (MOSFET) includes patterning a fin area, a source region, and a drain region on a substrate, forming a fin in the fin area, and forming a mask in the fin area. The method further includes etching the mask to expose a channel area of the MOSFET, etching the fin to thin a width of the fin in the channel area, forming a gate over the fin, and forming contacts to the gate, the source region, and the drain region.
摘要翻译：一种形成金属氧化物半导体场效应晶体管（MOSFET）的方法包括在衬底上构图翅片区域，源极区域和漏极区域，在翅片区域中形成鳍片，并在鳍片区域中形成掩模。该方法还包括蚀刻掩模以暴露MOSFET的沟道区域，蚀刻鳍以在沟道区域中减薄翅片的宽度，在鳍上方形成栅极，以及形成与栅极，源区和漏极区域。

3. 发明授权

US07679134B1 FinFET device with multiple fin structures 有权
标题翻译： FinFET器件具有多个鳍结构
公开(公告)号：US07679134B1
公开(公告)日：2010-03-16
申请号：US10754515
申请日：2004-01-12
申请人： Matthew S. Buynoski , Judy Xilin An , Haihong Wang , Bin Yu
发明人： Matthew S. Buynoski , Judy Xilin An , Haihong Wang , Bin Yu
IPC分类号： H01L29/94
CPC分类号： H01L29/785 , H01L21/3086 , H01L21/3088 , H01L21/32139 , H01L29/66795
摘要： A semiconductor device includes a group of fin structures. The group of fin structures includes a conductive material and is formed by growing the conductive material in an opening of an oxide layer. The semiconductor device further includes a source region formed at one end of the group of fin structures, a drain region formed at an opposite end of the group of fin structures, and at least one gate.
摘要翻译：半导体器件包括一组翅片结构。翅片结构的组包括导电材料，并且通过在氧化物层的开口中生长导电材料而形成。半导体器件还包括形成在鳍片结构组的一端处的源极区域，形成在鳍片结构组的相对端处的漏极区域和至少一个栅极。

4. 发明授权

US06709982B1 Double spacer FinFET formation 有权
标题翻译：双间隔FinFET形成
公开(公告)号：US06709982B1
公开(公告)日：2004-03-23
申请号：US10303702
申请日：2002-11-26
申请人： Matthew S. Buynoski , Judy Xilin An , Haihong Wang , Bin Yu
发明人： Matthew S. Buynoski , Judy Xilin An , Haihong Wang , Bin Yu
IPC分类号： H01L21311
CPC分类号： H01L29/785 , H01L21/3086 , H01L21/3088 , H01L21/32139 , H01L29/66795
摘要： A method for forming a group of structures in a semiconductor device includes forming a conductive layer on a substrate, where the conductive layer includes a conductive material, and forming an oxide layer over the conductive layer. The method further includes etching at least one opening in the oxide layer, filling the at least one opening with the conductive material, etching the conductive material to form spacers along sidewalls of the at least one opening, and removing the oxide layer and a portion of the conductive layer to form the group of structures.
摘要翻译：一种在半导体器件中形成一组结构的方法包括在基底上形成导电层，其中导电层包括导电材料，并在导电层上形成氧化物层。该方法还包括蚀刻氧化物层中的至少一个开口，用导电材料填充至少一个开口，蚀刻导电材料以在至少一个开口的侧壁上形成间隔物，并且去除氧化物层和一部分导电层形成一组结构。

5. 发明授权

US07432557B1 FinFET device with multiple channels 有权
标题翻译： FinFET器件具有多个通道
公开(公告)号：US07432557B1
公开(公告)日：2008-10-07
申请号：US10755344
申请日：2004-01-13
申请人： Matthew S. Buynoski , Judy Xilin An , Bin Yu
发明人： Matthew S. Buynoski , Judy Xilin An , Bin Yu
IPC分类号： H01L23/62
CPC分类号： H01L29/785 , H01L29/42384 , H01L29/66795 , H01L29/78603 , H01L2924/0002 , H01L2924/00
摘要： A method for forming one or more FinFET devices includes forming a source region and a drain region in an oxide layer, where the oxide layer is disposed on a substrate, and etching the oxide layer between the source region and the drain region to form a group of oxide walls and channels for a first device. The method further includes depositing a connector material over the oxide walls and channels for the first device, forming a gate mask for the first device, removing the connector material from the channels, depositing channel material in the channels for the first device, forming a gate dielectric for first device over the channels, depositing a gate material over the gate dielectric for the first device, and patterning and etching the gate material to form at least one gate electrode for the first device.
摘要翻译：半导体器件包括源极区域，漏极区域和形成在源极区域和漏极区域之间的沟道组。通道组中的至少一个通道通过氧化物结构与通道组中的另一个通道分离。半导体器件还包括至少一个形成在该组沟道的至少一部分上的栅极。

6. 发明授权

US06716686B1 Method for forming channels in a finfet device 失效
标题翻译：在finfet装置中形成通道的方法
公开(公告)号：US06716686B1
公开(公告)日：2004-04-06
申请号：US10613997
申请日：2003-07-08
申请人： Matthew S. Buynoski , Judy Xilin An , Bin Yu
发明人： Matthew S. Buynoski , Judy Xilin An , Bin Yu
IPC分类号： H01L2100
CPC分类号： H01L29/785 , H01L29/42384 , H01L29/66795 , H01L29/78603 , H01L2924/0002 , H01L2924/00
摘要： A method for forming one or more FinFET devices includes forming a source region and a drain region in an oxide layer, where the oxide layer is disposed on a substrate, and etching the oxide layer between the source region and the drain region to form a group of oxide walls and channels for a first device. The method further includes depositing a connector material over the oxide walls and channels for the first device, forming a gate mask for the first device, removing the connector material from the channels, depositing channel material in the channels for the first device, forming a gate dielectric for first device over the channels, depositing a gate material over the gate dielectric for the first device, and patterning and etching the gate material to form at least one gate electrode for the first device.
摘要翻译：用于形成一个或多个FinFET器件的方法包括在氧化物层中形成源极区域和漏极区域，其中氧化物层设置在衬底上，并且蚀刻源极区域和漏极区域之间的氧化物层以形成基团的第一装置的氧化物壁和通道。该方法还包括在第一器件的氧化物壁和通道上沉积连接器材料，形成用于第一器件的栅极掩模，从通道移除连接器材料，将沟道材料沉积在第一器件的通道中，形成栅极在沟道上的第一器件的电介质，在第一器件的栅极电介质上沉积栅极材料，以及图案化和蚀刻栅极材料以形成用于第一器件的至少一个栅电极。

7. 发明授权

US07105421B1 Silicon on insulator field effect transistor with heterojunction gate 有权
公开(公告)号：US07105421B1
公开(公告)日：2006-09-12
申请号：US10835438
申请日：2004-04-29
申请人： Qi Xiang , Matthew S. Buynoski
发明人： Qi Xiang , Matthew S. Buynoski
IPC分类号： H01L21/00
CPC分类号： H01L29/78696 , H01L29/432 , H01L29/66772 , H01L29/78645
摘要： A field effect transistor (FET) is formed on a silicon on insulator (SOI) substrate in the thin silicon layer above the insulating buried oxide layer. The channel region is lightly doped with a first impurity to increase free carrier conductivity of a first type. The source region and the drain region are heavily dopes with the first impurity. A gate and a back gate are positioned along the side of the channel region and extending from the source region and is implanted with a second semiconductor with an energy gap greater than silicon and is implanted with an impurity to increase free carrier flow of a second type.

8. 发明授权

US06815340B1 Method of forming an electroless nucleation layer on a via bottom 有权
标题翻译：在通孔底部形成无电解成核层的方法
公开(公告)号：US06815340B1
公开(公告)日：2004-11-09
申请号：US10145928
申请日：2002-05-15
申请人： Sergey D. Lopatin , Paul R. Besser , Matthew S. Buynoski , Pin-Chin Connie Wang
发明人： Sergey D. Lopatin , Paul R. Besser , Matthew S. Buynoski , Pin-Chin Connie Wang
IPC分类号： H01L214763
CPC分类号： H01L21/76843 , H01L21/288 , H01L21/76846 , H01L21/76849 , H01L21/76874
摘要： A method of fabricating an integrated circuit can include performing a reactive ion etch (RIE) to form a via aperture in a dielectric layer where the via aperture exposes a portion of a conductive layer located under the dielectric layer, removing polymer residue from the RIE, and forming a nucleation layer over the exposed portion of the conductive layer using an alloy. The nucleation layer can be formed in an electroless process and can improve electromigration reliability, reduce via resistance, eliminate via corrosion, and eliminate copper resputtering on dielectric sidewalls.
摘要翻译：制造集成电路的方法可以包括执行反应离子蚀刻（RIE）以在电介质层中形成通孔，其中通孔孔暴露位于电介质层下面的导电层的一部分，从RIE除去聚合物残余物，以及使用合金在导电层的暴露部分上形成成核层。成核层可以在无电解过程中形成，并且可以提高电迁移可靠性，降低通孔电阻，消除通孔腐蚀，并消除电介质侧壁上的铜再溅射。

9. 发明授权

US06784506B2 Silicide process using high K-dielectrics 失效
标题翻译：使用高K电介质的硅化物工艺
公开(公告)号：US06784506B2
公开(公告)日：2004-08-31
申请号：US09939744
申请日：2001-08-28
申请人： Qi Xiang , Paul R. Besser , Matthew S. Buynoski , John Clayton Foster , Paul L. King , Eric N. Paton
发明人： Qi Xiang , Paul R. Besser , Matthew S. Buynoski , John Clayton Foster , Paul L. King , Eric N. Paton
IPC分类号： H01L2976
CPC分类号： H01L29/4933 , H01L21/28167 , H01L21/28194 , H01L29/517 , H01L29/518 , H01L29/665
摘要： A method for preventing the thermal decomposition of a high-K dielectric layer of a gate electrode during the formation of a metal silicide on the gate electrode by using nickel as the metal component of the silicide.
摘要翻译：通过使用镍作为硅化物的金属成分，在栅电极形成金属硅化物期间防止栅电极的高K电介质层的热分解的方法。

10. 发明授权

US06759308B2 Silicon on insulator field effect transistor with heterojunction gate 有权
标题翻译：具有异质结栅的绝缘体上的场效应晶体管
公开(公告)号：US06759308B2
公开(公告)日：2004-07-06
申请号：US09902429
申请日：2001-07-10
申请人： Qi Xiang , Matthew S. Buynoski
发明人： Qi Xiang , Matthew S. Buynoski
IPC分类号： H01L2130
CPC分类号： H01L29/78696 , H01L29/432 , H01L29/66772 , H01L29/78645
摘要： A field effect transistor (FET) is formed on a silicon on insulator (SOI) substrate in the thin silicon layer above the insulating buried oxide layer. The channel region is lightly doped with a first impurity to increase free carrier conductivity of a first type. The source region and the drain region are heavily dopes with the first impurity. A gate and a back gate are positioned along the side of the channel region and extending from the source region and is implanted with a second semiconductor with an energy gap greater than silicon and is implanted with an impurity to increase free carrier flow of a second type.
摘要翻译：在隔离掩埋氧化物层上方的薄硅层中的绝缘体上硅（SOI）衬底上形成场效应晶体管（FET）。沟道区域被轻掺杂第一杂质以增加第一类型的自由载流子导电性。源极区和漏极区是具有第一杂质的重掺杂物。栅极和背栅极沿着沟道区域的侧面定位并且从源极区域延伸并且注入具有大于硅的能隙的第二半导体，并且注入杂质以增加第二类型的自由载流子。

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