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91. 发明授权

US06656645B2 Method of manufacturing a photomask 有权
公开(公告)号：US06656645B2
公开(公告)日：2003-12-02
申请号：US09924769
申请日：2001-08-09
申请人： Toshihiko Tanaka , Norio Hasegawa , Tsuneo Terasawa
发明人： Toshihiko Tanaka , Norio Hasegawa , Tsuneo Terasawa
IPC分类号： G03F900
CPC分类号： G03F1/72 , G03F1/68
摘要： After a shade pattern constituted by a resist film formed on a photomask is stripped, a new shade pattern constituted by a resist film is formed on the photomask to reclaim a photomask.

92. 发明授权

US06656644B2 Manufacturing method of photomask and photomask 有权
公开(公告)号：US06656644B2
公开(公告)日：2003-12-02
申请号：US09881701
申请日：2001-06-18
申请人： Norio Hasegawa , Toshihiko Tanaka , Joji Okada , Kazutaka Mori , Ko Miyazaki
发明人： Norio Hasegawa , Toshihiko Tanaka , Joji Okada , Kazutaka Mori , Ko Miyazaki
IPC分类号： G03F900
CPC分类号： G03F1/56 , G03F7/0035
摘要： In order to shorten the time required to change or correct a mask pattern over a mask, light-shielding patterns formed of a resist film for integrated circuit pattern transfer are partly provided over a mask substrate constituting a photomask in addition to light-shielding patterns formed of a metal for the integrated circuit pattern transfer.

93. 发明授权

US06653052B2 Electron device manufacturing method, a pattern forming method, and a photomask used for those methods 有权
标题翻译：电子器件制造方法，图案形成方法和用于这些方法的光掩模
公开(公告)号：US06653052B2
公开(公告)日：2003-11-25
申请号：US09810194
申请日：2001-03-19
申请人： Toshihiko Tanaka , Norio Hasegawa , Hiroshi Shiraishi , Hidetoshi Satoh
发明人： Toshihiko Tanaka , Norio Hasegawa , Hiroshi Shiraishi , Hidetoshi Satoh
IPC分类号： G03F750
CPC分类号： G03F1/30
摘要： A method of manufacturing an electron device provided with minute structure such as a semiconductor integrated circuit using projection exposure technique and phase shift mask technique, maintaining a high yield is disclosed. In an electron device manufacturing method according to the invention, a desired electron device is manufactured by printing a light shielding film pattern on a photosensitive film provided on the surface of a workpiece by a projection tool using a mask where a phase shifter having predetermined thickness is partially formed on the flat surface of a transparent plate and a light shielding film having a predetermined pattern and made of non-metal is partially provided with the film covering the end of the shifter and developing the photosensitive film. Further, concretely, the above pattern is printed using a mask where the light shielding film made of non-metal is partially extended on the surface of the shifter and the transparent plate including the end of the shifter by the projection tool. According to the electron device manufacturing method according to the invention, an electron device provided with minute structure can be precisely manufactured maintaining a high yield.
摘要翻译：公开了一种制造具有微小结构的电子器件的方法，例如使用投影曝光技术和相移掩模技术的半导体集成电路，保持高产率。在根据本发明的电子器件制造方法中，通过使用具有预定厚度的移相器的掩模通过投影工具在设置在工件表面上的感光膜上印刷遮光膜图案来制造所需的电子器件部分地形成在透明板的平坦表面上和具有预定图案并由非金属制成的遮光膜部分地设置有覆盖移位器的端部并显影感光膜的膜。此外，具体地，使用由非金属制成的遮光膜在移位器的表面上部分地延伸的掩模和通过投影工具包括移位器的端部的透明板来打印上述图案。根据本发明的电子器件制造方法，可以精确地制造具有微小结构的电子器件，保持高产率。

94. 发明授权

US06649956B2 Semiconductor integrated circuit device and manufacturing method thereof 有权
公开(公告)号：US06649956B2
公开(公告)日：2003-11-18
申请号：US10227799
申请日：2002-08-27
申请人： Makoto Yoshida , Takahiro Kumauchi , Yoshitaka Tadaki , Isamu Asano , Norio Hasegawa , Keizo Kawakita
发明人： Makoto Yoshida , Takahiro Kumauchi , Yoshitaka Tadaki , Isamu Asano , Norio Hasegawa , Keizo Kawakita
IPC分类号： H01L2972
CPC分类号： H01L27/10852 , H01L27/10817
摘要： An active region (L) with a metal insulator semiconductor field effect transistor (MISFET) (Qs) formed therein for selection of a DRAM memory cell, which makes up a memory cell of the DRAM, is arranged to have an island-like pattern that linearly extends in an X direction on one principal surface of a semiconductor substrate (1). The memory-cell selection MISFET (Qs) has an insulated gate electrode (7) (word line WL) that extends along a Y direction on the principal surface of the semiconductor substrate (1) with the same width kept along the length thereof, which gate electrode is arranged to oppose another gate electrode (7) (word line WL) adjacent thereto at a prespecified distance or pitch that is narrower than said width. In addition, a bit line (BL) is provided overlying the memory-cell select MISFET (Qs) in a manner such that the bit line extends in the X direction on the principal surface of the semiconductor substrate (1) with the same width and opposes its neighboring bit line (BL) at a distance or pitch that is wider than said width.

95. 发明授权

US06596656B2 Manufacturing use of photomasks with an opaque pattern comprising an organic layer photoabsorptive to exposure light with wavelengths exceeding 200 NM 失效
标题翻译：制造使用具有不透明图案的光掩模，所述不透明图案包括对波长超过200nm的曝光光吸收的有机层
公开(公告)号：US06596656B2
公开(公告)日：2003-07-22
申请号：US09931938
申请日：2001-08-20
申请人： Toshihiko Tanaka , Norio Hasegawa , Kazutaka Mori , Ko Miyazaki , Tsuneo Terasawa
发明人： Toshihiko Tanaka , Norio Hasegawa , Kazutaka Mori , Ko Miyazaki , Tsuneo Terasawa
IPC分类号： H01L2131
CPC分类号： G03F1/56 , G03F1/00 , G03F1/58 , G03F7/0035 , Y10S438/945
摘要： A method is provided for well printing a specified pattern even when the exposure treatment using a resist mask uses exposure light with a wavelength over 200 nm. When exposure treatment is applied to a semiconductor wafer by using exposure light with a wavelength over 200 nm, a photomask is used. The photomask is provided with an opaque pattern of a resist layer on an organic layer which is photoabsorptive in reaction to exposure light.
摘要翻译：即使当使用抗蚀剂掩模的曝光处理使用具有超过200nm的波长的曝光光时，也提供了用于良好地打印指定图案的方法。当通过使用波长超过200nm的曝光光对半导体晶片进行曝光处理时，使用光掩模。光掩模在有机层上设置有抗光蚀刻层的不透明图案，其与曝光光反应是光吸收性的。

96. 发明授权

US06538855B1 Magneto-resistive thin film magnetic head preventing entry of unnecessary magnetic flux and having good reproduction characteristics 失效
标题翻译：磁阻薄膜磁头防止不必要的磁通进入并具有良好的再生特性
公开(公告)号：US06538855B1
公开(公告)日：2003-03-25
申请号：US09717668
申请日：2000-11-21
申请人： Akira Nakamura , Morio Kondo , Norio Hasegawa , Yasuhiko Shinjo , Kenji Machida , Naoto Hayashi , Kazutoshi Mutou , Toshihiro Uehara , Junji Numazawa
发明人： Akira Nakamura , Morio Kondo , Norio Hasegawa , Yasuhiko Shinjo , Kenji Machida , Naoto Hayashi , Kazutoshi Mutou , Toshihiro Uehara , Junji Numazawa
IPC分类号： G11B539
CPC分类号： G11B5/3925 , G11B5/11 , G11B5/3146
摘要： A magneto-resistive thin film magnetic head is provided, which magnetic head includes: a base; a first yoke provided on the base and separated by a gap into first and second portions, the first portion including a side which opposes a magnetic recording medium; a magneto-resistive element which is magnetically coupled to the first and second portions of the first yoke and detects a magnetic recording signal; a second yoke formed on the first yoke so as to form a reproducing head gap between the first portion of the first yoke and the second yoke; and a third yoke provided between the first portion of the first yoke and the base so as to be magnetically coupled to the first portion of the first yoke. The reproducing head gap, the first portion of the first yoke, the magneto-resistive element, the second portion of the first yoke, ad the second yoke form a cut magnetic circuit.
摘要翻译：提供一种磁阻薄膜磁头，该磁头包括：基座; 设置在基座上并由间隙分隔成第一和第二部分的第一磁轭，第一部分包括与磁记录介质相对的一侧; 磁阻元件，其磁耦合到第一磁轭的第一和第二部分，并检测磁记录信号; 形成在第一磁轭上的第二磁轭，以在第一磁轭的第一部分和第二磁轭之间形成再现磁头间隙; 以及设置在第一磁轭的第一部分和基座之间的第三磁轭，以便磁耦合到第一磁轭的第一部分。再现磁头间隙，第一磁轭的第一部分，磁阻元件，第一磁轭的第二部分，第二磁轭形成切割磁路。

97. 发明授权

US06483136B1 Semiconductor integrated circuit and method of fabricating the same 有权
标题翻译：半导体集成电路及其制造方法
公开(公告)号：US06483136B1
公开(公告)日：2002-11-19
申请号：US09446302
申请日：2000-04-14
申请人： Makoto Yoshida , Takahiro Kumauchi , Yoshitaka Tadaki , Isamu Asano , Norio Hasegawa , Keizo Kawakita
发明人： Makoto Yoshida , Takahiro Kumauchi , Yoshitaka Tadaki , Isamu Asano , Norio Hasegawa , Keizo Kawakita
IPC分类号： H01L2972
CPC分类号： H01L27/10852 , H01L27/10817
摘要： An active region (L) with a metal insulator semiconductor field effect transistor (MISFET) (Qs) formed therein for selection of a DRAM memory cell, which makes up a memory cell of the DRAM, is arranged to have an island-like pattern that linearly extends in an X direction on one principal surface of a semiconductor substrate (1). The memory-cell selection MISFET (Qs) has an insulated gate electrode (7) (word line WL) that extends along a Y direction on the principal surface of the semiconductor substrate (1) with the same width kept along the length thereof, which gate electrode is arranged to oppose another gate electrode (7) (word line WL) adjacent thereto at a prespecified distance or pitch that is narrower than said width. In addition, a bit line (BL) is provided overlying the memory-cell select MISFET (Qs) in a manner such that the bit line extends in the X direction on the principal surface of the semiconductor substrate (1) with the same width and opposes its neighboring bit line (BL) at a distance or pitch that is wider than said width.
摘要翻译：在其中形成有用于选择构成DRAM的存储单元的DRAM存储单元的金属绝缘体半导体场效应晶体管（MISFET）（Qs）的有源区域（L）被布置成具有岛状图案，在半导体衬底（1）的一个主表面上沿X方向线性地延伸。存储单元选择MISFET（Qs）具有在半导体衬底（1）的主表面上沿着Y方向延伸的绝缘栅电极（字线WL），沿着其长度保持相同的宽度，栅电极被布置成以比所述宽度窄的预定距离或间距与与其相邻的另一个栅电极（7）（字线WL）相对。此外，位线（BL）以这样的方式设置在存储单元选择MISFET（Qs）上，使得位线在半导体衬底（1）的主表面上沿X方向以相同的宽度延伸，并且以比所述宽度更宽的距离或间距来对置其相邻位线（BL）。

98. 发明授权

US06291847B1 Semiconductor integrated circuit device and process for manufacturing the same 有权
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US06291847B1
公开(公告)日：2001-09-18
申请号：US09159754
申请日：1998-09-24
申请人： Kiyonori Ohyu , Makoto Ohkura , Aritoshi Sugimoto , Yoshitaka Tadaki , Makoto Ogasawara , Masashi Horiguchi , Norio Hasegawa , Shinichi Fukada
发明人： Kiyonori Ohyu , Makoto Ohkura , Aritoshi Sugimoto , Yoshitaka Tadaki , Makoto Ogasawara , Masashi Horiguchi , Norio Hasegawa , Shinichi Fukada
IPC分类号： H01L27108
CPC分类号： H01L27/10897 , H01L27/10814 , H01L27/10894
摘要： A field oxide film 3 in a region where relief cells are formed is made wider than the field oxide film 3 in a region where normal memory cells are formed thereby to make a field relaxation layer 8r of the relief cells deeper than the field relaxation layer 8 of the normal cells, and the depletion layer of the sources and drains (n-type semiconductor regions) of the relief cells is widened to weaken the junction field.
摘要翻译：在形成正常存储单元的区域中，形成有浮雕单元的区域中的场氧化膜3比场氧化膜3宽，使得浮雕单元的场弛豫层8r比场弛豫层8更深的正电池，并且补充电池的源极和漏极（n型半导体区域）的耗尽层变宽以削弱结场。

99. 发明授权

US06278148B1 Semiconductor device having a shielding conductor 失效
标题翻译：具有屏蔽导体的半导体器件
公开(公告)号：US06278148B1
公开(公告)日：2001-08-21
申请号：US09040457
申请日：1998-03-18
申请人： Takao Watanabe , Takuya Fukuda , Norio Hasegawa
发明人： Takao Watanabe , Takuya Fukuda , Norio Hasegawa
IPC分类号： H01L27108
CPC分类号： H01L27/10897 , G11C5/063 , G11C7/02 , G11C11/4097 , H01L23/5225 , H01L23/552 , H01L27/10805 , H01L27/10882 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to a semiconductor device that includes a dynamic memory and logic circuits that are integrated on a single chip and that can avoid noise problems and signal delay. The portion above the memory is shielded with a shielding conductor that is biased to an equipotential. Wirings between logical blocks and bonding pads or between logical blocks are passed over the conductive layer. Wiring for logic circuits can be done in the same metal wiring layer in which the shielding conductor is provided. The shielding conductor can have a mesh-like structure to improve its integrity and wirings can be passed over conductive portions of the shielding layer to be protected from noise. In addition to the dynamic memory, other memories and analog circuits can be used instead of or in combination with the dynamic memory.
摘要翻译：本发明涉及一种半导体器件，其包括集成在单个芯片上并且可以避免噪声问题和信号延迟的动态存储器和逻辑电路。存储器上方的部分用被偏置到等电位的屏蔽导体屏蔽。逻辑块和焊盘之间或逻辑块之间的布线通过导电层。逻辑电路的布线可以在设置有屏蔽导体的同一金属布线层中完成。屏蔽导体可以具有网状结构以改善其完整性，并且布线可以穿过屏蔽层的导电部分以防止噪声。除了动态存储器之外，可以使用其他存储器和模拟电路来代替动态存储器或与动态存储器组合使用。

100. 发明授权

US5885735A Mask having a phase shifter and method of manufacturing same 失效
标题翻译：具有移相器的掩模及其制造方法
公开(公告)号：US5885735A
公开(公告)日：1999-03-23
申请号：US834542
申请日：1997-03-31
申请人： Akira Imai , Norio Hasegawa , Hiroshi Fukuda , Toshihiko Tanaka
发明人： Akira Imai , Norio Hasegawa , Hiroshi Fukuda , Toshihiko Tanaka
IPC分类号： G03F1/00 , G03F1/26 , G03F1/29 , G03F1/72 , G03F9/00
CPC分类号： G03F1/72 , G03F1/26 , G03F1/29 , G03F1/38
摘要： There is disclosed a mask which includes a first phase shifter layer and a second phase shifter layer formed on the first phase shifter layer and has a structure capable of easily effecting highly precise control of the phase of exposure light and correction for a defect in the phase shifter layers. There are also disclosed a method of manufacturing the mask and a method of forming by use of the mask a pattern which has a smaller local error in pattern dimension and is free of a defect.
摘要翻译：公开了一种掩模，其包括形成在第一移相器层上的第一移相器层和第二移相器层，并且具有能够容易地实现对曝光光的相位的高度精确控制和对相的缺陷进行校正的结构移位层。还公开了一种制造掩模的方法以及通过使用掩模形成图案的图案尺寸较小的局部误差并且没有缺陷的图案的方法。

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