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1. 发明授权

US06649956B2 Semiconductor integrated circuit device and manufacturing method thereof 有权
公开(公告)号：US06649956B2
公开(公告)日：2003-11-18
申请号：US10227799
申请日：2002-08-27
申请人： Makoto Yoshida , Takahiro Kumauchi , Yoshitaka Tadaki , Isamu Asano , Norio Hasegawa , Keizo Kawakita
发明人： Makoto Yoshida , Takahiro Kumauchi , Yoshitaka Tadaki , Isamu Asano , Norio Hasegawa , Keizo Kawakita
IPC分类号： H01L2972
CPC分类号： H01L27/10852 , H01L27/10817
摘要： An active region (L) with a metal insulator semiconductor field effect transistor (MISFET) (Qs) formed therein for selection of a DRAM memory cell, which makes up a memory cell of the DRAM, is arranged to have an island-like pattern that linearly extends in an X direction on one principal surface of a semiconductor substrate (1). The memory-cell selection MISFET (Qs) has an insulated gate electrode (7) (word line WL) that extends along a Y direction on the principal surface of the semiconductor substrate (1) with the same width kept along the length thereof, which gate electrode is arranged to oppose another gate electrode (7) (word line WL) adjacent thereto at a prespecified distance or pitch that is narrower than said width. In addition, a bit line (BL) is provided overlying the memory-cell select MISFET (Qs) in a manner such that the bit line extends in the X direction on the principal surface of the semiconductor substrate (1) with the same width and opposes its neighboring bit line (BL) at a distance or pitch that is wider than said width.

2. 发明授权

US06483136B1 Semiconductor integrated circuit and method of fabricating the same 有权
标题翻译：半导体集成电路及其制造方法
公开(公告)号：US06483136B1
公开(公告)日：2002-11-19
申请号：US09446302
申请日：2000-04-14
申请人： Makoto Yoshida , Takahiro Kumauchi , Yoshitaka Tadaki , Isamu Asano , Norio Hasegawa , Keizo Kawakita
发明人： Makoto Yoshida , Takahiro Kumauchi , Yoshitaka Tadaki , Isamu Asano , Norio Hasegawa , Keizo Kawakita
IPC分类号： H01L2972
CPC分类号： H01L27/10852 , H01L27/10817
摘要： An active region (L) with a metal insulator semiconductor field effect transistor (MISFET) (Qs) formed therein for selection of a DRAM memory cell, which makes up a memory cell of the DRAM, is arranged to have an island-like pattern that linearly extends in an X direction on one principal surface of a semiconductor substrate (1). The memory-cell selection MISFET (Qs) has an insulated gate electrode (7) (word line WL) that extends along a Y direction on the principal surface of the semiconductor substrate (1) with the same width kept along the length thereof, which gate electrode is arranged to oppose another gate electrode (7) (word line WL) adjacent thereto at a prespecified distance or pitch that is narrower than said width. In addition, a bit line (BL) is provided overlying the memory-cell select MISFET (Qs) in a manner such that the bit line extends in the X direction on the principal surface of the semiconductor substrate (1) with the same width and opposes its neighboring bit line (BL) at a distance or pitch that is wider than said width.
摘要翻译：在其中形成有用于选择构成DRAM的存储单元的DRAM存储单元的金属绝缘体半导体场效应晶体管（MISFET）（Qs）的有源区域（L）被布置成具有岛状图案，在半导体衬底（1）的一个主表面上沿X方向线性地延伸。存储单元选择MISFET（Qs）具有在半导体衬底（1）的主表面上沿着Y方向延伸的绝缘栅电极（字线WL），沿着其长度保持相同的宽度，栅电极被布置成以比所述宽度窄的预定距离或间距与与其相邻的另一个栅电极（7）（字线WL）相对。此外，位线（BL）以这样的方式设置在存储单元选择MISFET（Qs）上，使得位线在半导体衬底（1）的主表面上沿X方向以相同的宽度延伸，并且以比所述宽度更宽的距离或间距来对置其相邻位线（BL）。

3. 发明授权

US07042038B2 Semiconductor integrated circuit device and manufacturing method thereof 有权
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US07042038B2
公开(公告)日：2006-05-09
申请号：US10653889
申请日：2003-09-04
申请人： Makoto Yoshida , Takahiro Kumauchi , Yoshitaka Tadaki , Isamu Asano , Norio Hasegawa , Keizo Kawakita
发明人： Makoto Yoshida , Takahiro Kumauchi , Yoshitaka Tadaki , Isamu Asano , Norio Hasegawa , Keizo Kawakita
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/10852 , H01L27/10817
摘要： An active region (L) with a metal insulator semiconductor field effect transistor (MISFET) (Qs) formed therein for selection of a DRAM memory cell, which makes up a memory cell of the DRAM, is arranged to have an island-like pattern that linearly extends in an X direction on one principal surface of a semiconductor substrate (1). The memory-cell selection MISFET (Qs) has an insulated gate electrode (7) (word line WL) that extends along a Y direction on the principal surface of the semiconductor substrate (1) with the same width kept along the length thereof, which gate electrode is arranged to oppose another gate electrode (7) (word line WL) adjacent thereto at a prespecified distance or pitch that is narrower than said width. In addition, a bit line (BL) is provided overlying the memory-cell select MISFET (Qs) in a manner such that the bit line extends in the X direction on the principal surface of the semiconductor substrate (1) with the same width and opposes its neighboring bit line (BL) at a distance or pitch that is wider than said width.
摘要翻译：在其中形成有用于选择构成DRAM的存储单元的DRAM存储单元的金属绝缘体半导体场效应晶体管（MISFET）（Qs）的有源区域（L）被布置成具有岛状图案，在半导体衬底（1）的一个主表面上沿X方向线性地延伸。存储单元选择MISFET（Qs）具有在半导体衬底（1）的主表面上沿着Y方向延伸的绝缘栅电极（字线WL），沿着其长度保持相同的宽度，栅电极被布置成以比所述宽度窄的预定距离或间距与与其相邻的另一个栅电极（7）（字线WL）相对。此外，位线（BL）以这样的方式设置在存储单元选择MISFET（Qs）上，使得位线在半导体衬底（1）的主表面上沿X方向以相同的宽度延伸，并且以比所述宽度更宽的距离或间距来对置其相邻位线（BL）。

4. 发明授权

US06573546B2 Semiconductor integrated circuit device and process for manufacturing the same 有权
公开(公告)号：US06573546B2
公开(公告)日：2003-06-03
申请号：US09922673
申请日：2001-08-07
申请人： Kiyonori Ohyu , Makoto Ohkura , Aritoshi Sugimoto , Yoshitaka Tadaki , Makoto Ogasawara , Masashi Horiguchi , Norio Hasegawa , Shinichi Fukada
发明人： Kiyonori Ohyu , Makoto Ohkura , Aritoshi Sugimoto , Yoshitaka Tadaki , Makoto Ogasawara , Masashi Horiguchi , Norio Hasegawa , Shinichi Fukada
IPC分类号： H01L27108
CPC分类号： H01L27/10897 , H01L27/10814 , H01L27/10894
摘要： A field oxide film 3 in a region where relief cells are formed is made wider than the field oxide film 3 in a region where normal memory cells are formed thereby to make a field relaxation layer 8r of the relief cells deeper than the field relaxation layer 8 of the normal cells, and the depletion layer of the sources and drains (n-type semiconductor regions) of the relief cells is widened to weaken the junction field.

5. 发明授权

US06291847B1 Semiconductor integrated circuit device and process for manufacturing the same 有权
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US06291847B1
公开(公告)日：2001-09-18
申请号：US09159754
申请日：1998-09-24
申请人： Kiyonori Ohyu , Makoto Ohkura , Aritoshi Sugimoto , Yoshitaka Tadaki , Makoto Ogasawara , Masashi Horiguchi , Norio Hasegawa , Shinichi Fukada
发明人： Kiyonori Ohyu , Makoto Ohkura , Aritoshi Sugimoto , Yoshitaka Tadaki , Makoto Ogasawara , Masashi Horiguchi , Norio Hasegawa , Shinichi Fukada
IPC分类号： H01L27108
CPC分类号： H01L27/10897 , H01L27/10814 , H01L27/10894
摘要： A field oxide film 3 in a region where relief cells are formed is made wider than the field oxide film 3 in a region where normal memory cells are formed thereby to make a field relaxation layer 8r of the relief cells deeper than the field relaxation layer 8 of the normal cells, and the depletion layer of the sources and drains (n-type semiconductor regions) of the relief cells is widened to weaken the junction field.
摘要翻译：在形成正常存储单元的区域中，形成有浮雕单元的区域中的场氧化膜3比场氧化膜3宽，使得浮雕单元的场弛豫层8r比场弛豫层8更深的正电池，并且补充电池的源极和漏极（n型半导体区域）的耗尽层变宽以削弱结场。

6. 发明授权

US09297649B2 Pattern dimension measurement method and charged particle beam apparatus 有权
标题翻译：图案尺寸测量方法和带电粒子束装置
公开(公告)号：US09297649B2
公开(公告)日：2016-03-29
申请号：US14001433
申请日：2011-12-12
申请人： Hiroki Kawada , Norio Hasegawa , Toru Ikegami
发明人： Hiroki Kawada , Norio Hasegawa , Toru Ikegami
IPC分类号： G01B15/06 , G01N23/225 , H01J37/28 , H01J37/22 , G01N23/00 , H01J37/244
CPC分类号： G01B15/06 , G01N23/00 , H01J37/222 , H01J37/244 , H01J37/28 , H01J2237/24578 , H01J2237/2816 , H01J2237/2817
摘要： The present invention aims to provide a pattern dimension measurement method for accurately measuring an amount of shrinkage of a pattern that shrinks and an original dimension value before the shrinkage and a charged particle beam apparatus.In order to attain the above-mentioned object, there are proposed a pattern dimension measurement method and a charged particle beam apparatus that are characterized by: forming a thin film on a sample including the pattern after carrying out beam scanning onto a first portion of the pattern; acquiring a first measurement value by scanning a beam onto a region corresponding to the first portion on which the thin film is formed; acquiring a second measurement value by scanning a beam onto a second portion that has identical dimensions as those of the first portion on design data; and finding the amount of shrinkage of the pattern based on subtraction processing of subtracting the first measurement value from the second measurement value.
摘要翻译：本发明的目的在于提供一种图形尺寸测量方法，用于精确测量收缩的图案的收缩量和收缩前的原始尺寸值以及带电粒子束装置。为了实现上述目的，提出了一种图案尺寸测量方法和带电粒子束装置，其特征在于：在对包含图案的样品进行束扫描之后，在包含该图案的样品上形成薄膜至第一部分模式; 通过将光束扫描到与其上形成有薄膜的第一部分对应的区域来获取第一测量值; 通过将光束扫描到与设计数据上的第一部分具有相同尺寸的第二部分上来获取第二测量值; 并且基于从第二测量值减去第一测量值的减法处理来找出图案的收缩量。

7. 发明授权

US08671366B2 Estimating shape based on comparison between actual waveform and library in lithography process 有权
标题翻译：基于光刻过程中实际波形与库之间的比较估算形状
公开(公告)号：US08671366B2
公开(公告)日：2014-03-11
申请号：US13390354
申请日：2010-07-15
申请人： Maki Tanaka , Norio Hasegawa , Chie Shishido , Mayuka Osaki
发明人： Maki Tanaka , Norio Hasegawa , Chie Shishido , Mayuka Osaki
IPC分类号： G06F17/50
CPC分类号： G01B15/04 , H01L22/12 , H01L2924/0002 , H01L2924/00
摘要： The present invention aims at proposing a library creation method and a pattern shape estimation method in which it is possible, when estimating a shape based on comparison between an actual waveform and a library, to appropriately estimate the shape.As an illustrative embodiment to achieve the object, there are proposed a method of selecting a pattern by referring to a library, a method of creating a library by use of pattern cross-sectional shapes calculated through an exposure process simulation in advance, and a method for selecting a pattern shape stored in the library.
摘要翻译：本发明旨在提出一种库创建方法和图案形状估计方法，其中当基于实际波形和库之间的比较来估计形状时，可以适当地估计形状。作为实现该目的的说明性实施例，提出了通过参照库来选择图案的方法，通过使用预先通过曝光处理模拟计算的图案横截面形状来创建库的方法，以及方法用于选择存储在库中的图案形状。

8. 发明申请

US20140048706A1 PATTERN DIMENSION MEASUREMENT METHOD AND CHARGED PARTICLE BEAM APPARATUS 有权
标题翻译：图案尺寸测量方法和充电颗粒光束装置
公开(公告)号：US20140048706A1
公开(公告)日：2014-02-20
申请号：US14001433
申请日：2011-12-12
申请人： Hiroki Kawada , Norio Hasegawa , Toru Ikegami
发明人： Hiroki Kawada , Norio Hasegawa , Toru Ikegami
IPC分类号： G01N23/00
CPC分类号： G01B15/06 , G01N23/00 , H01J37/222 , H01J37/244 , H01J37/28 , H01J2237/24578 , H01J2237/2816 , H01J2237/2817
摘要： The present invention aims to provide a pattern dimension measurement method for accurately measuring an amount of shrinkage of a pattern that shrinks and an original dimension value before the shrinkage and a charged particle beam apparatus.In order to attain the above-mentioned object, there are proposed a pattern dimension measurement method and a charged particle beam apparatus that are characterized by: forming a thin film on a sample including the pattern after carrying out beam scanning onto a first portion of the pattern; acquiring a first measurement value by scanning a beam onto a region corresponding to the first portion on which the thin film is formed; acquiring a second measurement value by scanning a beam onto a second portion that has identical dimensions as those of the first portion on design data; and finding the amount of shrinkage of the pattern based on subtraction processing of subtracting the first measurement value from the second measurement value.
摘要翻译：本发明的目的在于提供一种图形尺寸测量方法，用于精确测量收缩的图案的收缩量和收缩前的原始尺寸值以及带电粒子束装置。为了实现上述目的，提出了一种图案尺寸测量方法和带电粒子束装置，其特征在于：在对包含图案的样品进行束扫描之后，在包含该图案的样品上形成薄膜至第一部分模式; 通过将光束扫描到与其上形成有薄膜的第一部分对应的区域来获取第一测量值; 通过将光束扫描到与设计数据上的第一部分具有相同尺寸的第二部分上来获取第二测量值; 并且基于从第二测量值减去第一测量值的减法处理来找出图案的收缩量。

9. 发明申请

US20130279793A1 IMAGE PROCESSING APPARATUS AND COMPUTER PROGRAM 有权
标题翻译：图像处理设备和计算机程序
公开(公告)号：US20130279793A1
公开(公告)日：2013-10-24
申请号：US13882141
申请日：2011-10-26
申请人： Yasutaka Toyoda , Norio Hasegawa , Ryoichi Matsuoka , Atsuko Yamaguchi
发明人： Yasutaka Toyoda , Norio Hasegawa , Ryoichi Matsuoka , Atsuko Yamaguchi
IPC分类号： G06T7/00
CPC分类号： G06T7/0004 , G06T7/001 , G06T2207/30141 , G06T2207/30152 , H01J37/222 , H01J37/28 , H01J2237/24578 , H01J2237/24592 , H01J2237/2817 , H01L22/12 , H01L2924/0002 , H01L2924/00
摘要： An object of the present invention is to provide an image processing apparatus and a computer program which detects a defect such as a scum at high speed and with high precision. In order to accomplish the above-described object, the present invention proposes an image processing apparatus and a computer program which acquires image data, and detects edge branch points from this image data. Here, at each of the edge branch points, an edge associated therewith branches off in at least three or more directions. According to this configuration, it becomes possible to detect a defect such as a scum without utilizing the reference-pattern image. As a consequence, it becomes possible to detect the scum at high speed and with high precision.
摘要翻译：本发明的目的是提供一种图像处理装置和计算机程序，其以高速和高精度检测浮渣等缺陷。为了实现上述目的，本发明提出一种图像处理装置和计算机程序，其获取图像数据，并从该图像数据检测边缘分支点。这里，在每个边缘分支点处，与其相关联的边缘在至少三个或更多个方向上分支。根据该结构，能够在不利用基准图案图像的情况下检测浮渣等缺陷。因此，可以高速，高精度地检测浮渣。

10. 发明授权

US08085870B2 Transmitter 有权
标题翻译：发射机
公开(公告)号：US08085870B2
公开(公告)日：2011-12-27
申请号：US12309140
申请日：2007-03-20
申请人： Takashi Okada , Jun Watanabe , Takahiro Todate , Norio Hasegawa
发明人： Takashi Okada , Jun Watanabe , Takahiro Todate , Norio Hasegawa
IPC分类号： H04L25/49
CPC分类号： H04B1/707 , H04B2201/70706
摘要： A transmitter suppresses peak power occurring in a transmission signal. The transmitter generates peak suppression signals for suppressing the peak power in the transmission signal respectively, synthesizes the peak suppression signals generated, and subtracts a signal as a synthesis result from the transmission signal.
摘要翻译：发射机抑制发射信号中发生的峰值功率。发射机分别产生用于抑制发送信号中的峰值功率的峰值抑制信号，合成产生的峰值抑制信号，并从发送信号中减去作为合成结果的信号。

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