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91. 发明授权

US5999464A Semiconductor memory device and method of checking same for defect 失效
公开(公告)号：US5999464A
公开(公告)日：1999-12-07
申请号：US58885
申请日：1998-04-13
申请人： Hideto Hidaka , Mikio Asakura , Kiyohiro Furutani , Tetsuo Kato
发明人： Hideto Hidaka , Mikio Asakura , Kiyohiro Furutani , Tetsuo Kato
IPC分类号： G11C11/413 , G11C11/401 , G11C29/00 , G11C29/04 , G11C29/14 , G11C29/24
CPC分类号： G11C29/24
摘要： A semiconductor memory device includes a first test row decoder (9a) for selecting memory cells in normal rows in a test mode, a second test row decoder (9b) for selecting spare memory cell rows, a first test column decoder (10a) for selecting memory cells in normal columns, and a second test column decoder (10b) for selecting spare memory cell columns. A control circuit (11) may perform switching between four combinations of the row and column decoders by using a control signal (SRT) and a control signal (SCT). All spare memory cells are tested prior to reparation of a defective memory cell for yield enhancement.

92. 发明授权

US5970507A Semiconductor memory device having a refresh-cycle program circuit 失效
标题翻译：具有刷新循环程序电路的半导体存储器件
公开(公告)号：US5970507A
公开(公告)日：1999-10-19
申请号：US676963
申请日：1996-07-08
申请人： Tetsuo Kato , Kiyohiro Furutani , Hideto Hidaka , Mikio Asakura
发明人： Tetsuo Kato , Kiyohiro Furutani , Hideto Hidaka , Mikio Asakura
IPC分类号： G11C11/403 , G11C11/406 , G11C11/409 , G06F12/00
CPC分类号： G11C11/406
摘要： In a semiconductor memory device, a self refresh cycle program circuit is provided and a refresh operation is conducted in accordance with one of the refresh cycles programmed in the refresh-cycle program circuit. The refresh cycle of the self-refresh mode is selected from a plurality of refresh-cycle types. A plurality of refresh modes allows a refresh cycle to be selected from a plurality of refresh-cycle types in accordance with a selected refresh mode.
摘要翻译：在半导体存储器件中，提供自刷新周期程序电路，并且根据在刷新周期程序电路中编程的刷新周期之一进行刷新操作。从多个刷新周期类型中选择自刷新模式的刷新周期。多个刷新模式允许根据所选择的刷新模式从多个刷新周期类型中选择刷新周期。

93. 再颁专利

USRE36169E Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：USRE36169E
公开(公告)日：1999-03-30
申请号：US609097
申请日：1996-02-29
申请人： Kiyohiro Furutani
发明人： Kiyohiro Furutani
IPC分类号： G11C11/409 , G11C5/02 , G11C7/10 , G11C11/401 , G11C11/4096 , H01L21/8242 , H01L27/108
CPC分类号： G11C11/4096 , G11C7/1006
摘要： A semiconductor memory device is provided having a read out gate for detecting and providing to a main I/O line pair the potential difference of a sub-data input/output line pair, and a write gate for transferring data of the main I/O line pair to the sub-data input/output line pair in an energy region surrounded by a sense amplifier region and a word line coupling region. By providing the read out gate and the write gate in the empty region which was not conventionally used, the access operation can be carried out at high speed without increasing the chip area of the semiconductor memory device.
摘要翻译：提供一种半导体存储器件，其具有用于检测并向主I / O线对提供子数据输入/输出线对的电位差的读出门和用于传送主I / O的数据的写入门在由读出放大器区域和字线耦合区域围绕的能量区域中的子数据输入/输出线对的线对。通过在未被常规使用的空区域中提供读出门和写入门，可以高速执行访问操作，而不增加半导体存储器件的芯片面积。

94. 发明授权

US5867439A Semiconductor memory device having internal address converting function, whose test and layout are conducted easily 失效
标题翻译：具有内部地址转换功能的半导体存储器件，其测试和布局容易进行
公开(公告)号：US5867439A
公开(公告)日：1999-02-02
申请号：US22490
申请日：1998-02-12
申请人： Mikio Asakura , Hideto Hidaka , Kiyohiro Furutani , Kenichi Yasuda
发明人： Mikio Asakura , Hideto Hidaka , Kiyohiro Furutani , Kenichi Yasuda
IPC分类号： G11C8/12 , G11C11/401 , G11C11/406 , G11C29/00 , G11C29/14 , G11C29/28 , G11C29/56 , G11C7/00
CPC分类号： G11C11/406 , G11C29/28 , G11C8/12
摘要： In a semiconductor memory device selectively implementing one of a 4K refresh cycle and a 8K refresh cycle, the positions of externally applied address signal bits are switched internally by address switching circuits such that memory cells at the same positions are selected regardless of whether the 4K refresh cycle or the 8K refresh cycle is specified according to a refresh cycle mode specify signal. As a result, by testing the device in one refresh cycle mode, the device can be checked in both refresh cycle operations, reducing the test time and making the test easier.
摘要翻译：在选择性地实现4K刷新周期和8K刷新周期之一的半导体存储器件中，外部施加的地址信号位的位置由地址切换电路在内部切换，使得在相同位置的存储单元被选择，而不管4K刷新循环或8K刷新周期根据刷新周期模式指定信号指定。因此，通过在一个刷新周期模式下测试器件，可以在两个刷新周期操作中检查器件，减少测试时间并使测试更容易。

95. 发明授权

US5793686A Semiconductor memory device having data input/output circuit of small occupied area capable of high-speed data input/output 失效
公开(公告)号：US5793686A
公开(公告)日：1998-08-11
申请号：US755930
申请日：1996-11-25
申请人： Kiyohiro Furutani , Tsukasa Ooishi , Mikio Asakura , Hideto Hidaka , Kei Hamade , Yoshito Nakaoka
发明人： Kiyohiro Furutani , Tsukasa Ooishi , Mikio Asakura , Hideto Hidaka , Kei Hamade , Yoshito Nakaoka
IPC分类号： G11C11/41 , G11C7/10 , G11C11/401 , G11C29/00 , G11C29/14 , G11C29/34 , G11C29/38 , G11C7/00
CPC分类号： G11C29/38 , G11C29/34 , G11C7/1051 , G11C7/1078
摘要： Read drivers which are provided in correspondence to simultaneously selected plural bits of memory cells are wired-OR connected to internal read data buses which in turn are provided in correspondence to a plurality of memory cell arrays respectively. A test mode circuit is provided for the internal read data buses for detecting coincidence/incoincidence of logics of signal potentials on these internal read data bus lines. In a test operation, all read drivers are activated to read selected memory cell data on the corresponding internal read data bus lines.

96. 发明授权

US5710737A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5710737A
公开(公告)日：1998-01-20
申请号：US652035
申请日：1996-05-23
申请人： Yuichiro Komiya , Kiyohiro Furutani , Tsukasa Ooishi , Kei Hamade
发明人： Yuichiro Komiya , Kiyohiro Furutani , Tsukasa Ooishi , Kei Hamade
IPC分类号： G01R31/26 , G01R31/28 , G01R31/3185 , G11C8/00 , G11C11/401 , G11C11/404 , G11C29/00 , G11C29/06 , G11C29/18 , G11C7/00
CPC分类号： G11C29/18 , G11C8/00
摘要： A sense amplifier (2) is connected to an input/output circuit (7), transmitting input/output data therebetween. The input/output circuit (7) is connected to an address scramble circuit (8). Furthermore, the input/output circuit (7) is connected to a data input/output terminal (DIO), externally transmitting data. The address scramble circuit (8) receives input data (INTDQ) from the data input/output terminal (DIO) and converts the input data (INTDQ) into write data (WD) in accordance with the layout of memory cells in a memory array (1) in response to a burn-in mode signal (BIT) outputted from an address key circuit (9) and a row address first signal RAF outputted from a row address buffer (6). Having the above configuration, a semiconductor memory device can be provided, which permits a prescribed stress to be imposed on its internal circuit only by inputting simple data even in a burn-in test. Moreover, a semiconductor memory device can be provided, which allows an external verification as to whether the device itself enters a burn-in mode or not.
摘要翻译：读出放大器（2）连接到输入/输出电路（7），在它们之间传输输入/输出数据。输入/输出电路（7）连接到地址加扰电路（8）。此外，输入/输出电路（7）连接到数据输入/输出端（DIO），外部发送数据。地址扰频电路（8）从数据输入/输出端（DIO）接收输入数据（INTDQ），并根据存储器阵列中存储单元的布局将输入数据（INTDQ）转换为写入数据（WD） 1）响应于从地址键电路（9）输出的老化模式信号（BIT）和从行地址缓冲器（6）输出的行地址第一信号RAF。具有上述结构，可以提供一种半导体存储器件，即使在老化测试中也能通过输入简单的数据来对其内部电路施加规定的应力。此外，可以提供半导体存储器件，其允许对器件本身是否进入老化模式进行外部验证。

97. 发明授权

US5600607A Semiconductor memory device that can read out data at high speed 失效
标题翻译：可高速读出数据的半导体存储器件
公开(公告)号：US5600607A
公开(公告)日：1997-02-04
申请号：US435691
申请日：1995-05-05
申请人： Kiyohiro Furutani , Hiroshi Miyamoto
发明人： Kiyohiro Furutani , Hiroshi Miyamoto
IPC分类号： G11C11/401 , G11C7/22 , G11C11/4076 , G11C11/409 , G11C11/4093 , G11C11/4096 , G11C8/00
CPC分类号： G11C11/4093 , G11C11/4076 , G11C11/4096 , G11C7/22
摘要： A .phi..sub.C generation circuit provides a column address buffer control signal to a column address buffer so that the column address buffer maintains a latch operation during the operation period of a differential amplifier. The column address buffer responds to a column address buffer control signal to latch an input address signal for providing a column address signal to a .phi..sub.D and PAE generation circuit. The .phi..sub.D and PAE generation circuit provides a differential amplifier activation signal to the differential amplifier according to a column address signal and a column access activation signal. The differential amplifier responds to a differential amplifier activation signal for amplifying data applied from a data input and output line to provide the same to a selector via a readout data line.
摘要翻译： phi C生成电路向列地址缓冲器提供列地址缓冲器控制信号，使得列地址缓冲器在差分放大器的操作周期期间保持锁存操作。列地址缓冲器响应列地址缓冲器控制信号以锁存输入地址信号，以向列D和PAE生成电路提供列地址信号。 phi D和PAE生成电路根据列地址信号和列访问激活信号向差分放大器提供差分放大器激活信号。差分放大器响应于差分放大器激活信号，用于放大从数据输入和输出线施加的数据，以通过读出数据线将其提供给选择器。

98. 发明授权

US5587607A Semiconductor integrated circuit device having improvement arrangement of pads 失效
标题翻译：具有焊盘改进布置的半导体集成电路器件
公开(公告)号：US5587607A
公开(公告)日：1996-12-24
申请号：US292301
申请日：1994-08-18
申请人： Kenichi Yasuda , Kiyohiro Furutani , Hiroshi Miyamoto
发明人： Kenichi Yasuda , Kiyohiro Furutani , Hiroshi Miyamoto
IPC分类号： H01L27/04 , G11C5/14 , G11C7/10 , G11C11/401 , H01L21/60 , H01L21/822 , H01L23/495 , H01L23/50 , H01L27/10 , H01L23/48 , H01L23/52
CPC分类号： G11C5/14 , B82Y10/00 , G11C7/1006 , G11C7/1045 , H01L23/4951 , H01L24/05 , H01L24/06 , H01L24/49 , G11C2029/1804 , H01L2223/6611 , H01L2224/04042 , H01L2224/05554 , H01L2224/05556 , H01L2224/05599 , H01L2224/06136 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/48465 , H01L2224/49113 , H01L24/48 , H01L2924/00014 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/10253 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041
摘要： A DRAM includes a package, a semiconductor chip housed in the package, and a plurality of leads each disposed from the outside of the package over the periphery of the semiconductor chip. The power supply potential is applied to some of the leads. Corresponding to one power supply lead, one power supply pad and one selection pad are formed. Corresponding to another power supply lead, another power supply pad and another selection pad are formed. Each of these two selection pads is connected or not connected to the corresponding power supply lead by bonding. As a result, one of four word configurations is selected. Since these two selection pads are disposed in the vicinity of the corresponding power supply leads, respectively, the number of times of bonding to one power supply lead is reduced.
摘要翻译： DRAM包括封装，容纳在封装中的半导体芯片，以及从半导体芯片周边的封装外部设置的多个引线。电源电位适用于某些引线。对应于一个电源引线，形成一个电源焊盘和一个选择焊盘。对应于另一个电源引线，形成另一个电源焊盘和另一个选择焊盘。这两个选择焊盘中的每一个通过结合连接或不连接到相应的电源引线。结果，选择了四个字配置之一。由于这两个选择焊盘分别设置在相应的电源引线附近，所以与一个电源引线的接合次数减少。

99. 发明授权

US5586076A Semiconductor memory device permitting high speed data transfer and high density integration 失效
标题翻译：半导体存储器件允许高速数据传输和高密度集成
公开(公告)号：US5586076A
公开(公告)日：1996-12-17
申请号：US304899
申请日：1994-09-13
申请人： Hiroshi Miyamoto , Yoshikazu Morooka , Kiyohiro Furutani , Shigeru Kikuda
发明人： Hiroshi Miyamoto , Yoshikazu Morooka , Kiyohiro Furutani , Shigeru Kikuda
IPC分类号： G11C11/401 , G11C7/10 , G11C11/409 , G11C11/4096 , G11C7/00 , G11C11/24
CPC分类号： G11C11/4096 , G11C7/10
摘要： In a memory cell array, data lines are formed into a hierarchical arrangement of sub data lines provided for every block and a main data line common to each block, and a sub data line selected by a column address among sub data lines belonging a block which are simultaneously selected by a row address is connected to a bit line. Accordingly, the sub data line length is reduced, which reduces floating capacitance, reading and writing operations can be conducted at a high speed, and sub data lines can be selectively operated. In addition, power required for charging the sub data lines can be reduced, and entire power consumption by the semiconductor memory device can be reduced as well.
摘要翻译：在存储单元阵列中，数据线被形成为每个块提供的子数据线和每个块共同的主数据线的分层布置，以及由属于块的子数据线之间的列地址选择的子数据线通过行地址同时选择连接到位线。因此，减少了子数据线的长度，这降低了浮动电容，可以高速地执行读和写操作，并且可以选择性地操作子数据线。此外，可以减少对子数据线进行充电所需的功率，并且可以减小半导体存储器件的整体功耗。

100. 发明授权

US5519243A Semiconductor device and manufacturing method thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US5519243A
公开(公告)日：1996-05-21
申请号：US305524
申请日：1994-09-13
申请人： Shigeru Kikuda , Kiyohiro Furutani , Makoto Suwa
发明人： Shigeru Kikuda , Kiyohiro Furutani , Makoto Suwa
IPC分类号： H01L21/8238 , H01L27/092 , H01L27/10 , H01L27/105 , H01L29/76 , H01L21/265
CPC分类号： H01L27/105 , Y10S438/901
摘要： A semiconductor device according to the present invention includes on the main surface of a p substrate a storing circuit region and peripheral circuit regions. An n well surrounds a p well including the storing circuit region and a p well including the peripheral circuit regions. As a result, a capacitance element is formed in the semiconductor substrate. It is possible to miniaturize the semiconductor device, and to improve reliability of connection between elements.
摘要翻译：根据本发明的半导体器件在p基板的主表面上包括存储电路区域和外围电路区域。 n阱围绕包括存储电路区域的p阱和包括外围电路区域的p阱。结果，在半导体衬底中形成电容元件。可以使半导体器件小型化，并提高元件之间的连接的可靠性。

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