专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5600607A Semiconductor memory device that can read out data at high speed 失效
标题翻译：可高速读出数据的半导体存储器件
公开(公告)号：US5600607A
公开(公告)日：1997-02-04
申请号：US435691
申请日：1995-05-05
申请人： Kiyohiro Furutani , Hiroshi Miyamoto
发明人： Kiyohiro Furutani , Hiroshi Miyamoto
IPC分类号： G11C11/401 , G11C7/22 , G11C11/4076 , G11C11/409 , G11C11/4093 , G11C11/4096 , G11C8/00
CPC分类号： G11C11/4093 , G11C11/4076 , G11C11/4096 , G11C7/22
摘要： A .phi..sub.C generation circuit provides a column address buffer control signal to a column address buffer so that the column address buffer maintains a latch operation during the operation period of a differential amplifier. The column address buffer responds to a column address buffer control signal to latch an input address signal for providing a column address signal to a .phi..sub.D and PAE generation circuit. The .phi..sub.D and PAE generation circuit provides a differential amplifier activation signal to the differential amplifier according to a column address signal and a column access activation signal. The differential amplifier responds to a differential amplifier activation signal for amplifying data applied from a data input and output line to provide the same to a selector via a readout data line.
摘要翻译： phi C生成电路向列地址缓冲器提供列地址缓冲器控制信号，使得列地址缓冲器在差分放大器的操作周期期间保持锁存操作。列地址缓冲器响应列地址缓冲器控制信号以锁存输入地址信号，以向列D和PAE生成电路提供列地址信号。 phi D和PAE生成电路根据列地址信号和列访问激活信号向差分放大器提供差分放大器激活信号。差分放大器响应于差分放大器激活信号，用于放大从数据输入和输出线施加的数据，以通过读出数据线将其提供给选择器。

2. 发明授权

US5587607A Semiconductor integrated circuit device having improvement arrangement of pads 失效
标题翻译：具有焊盘改进布置的半导体集成电路器件
公开(公告)号：US5587607A
公开(公告)日：1996-12-24
申请号：US292301
申请日：1994-08-18
申请人： Kenichi Yasuda , Kiyohiro Furutani , Hiroshi Miyamoto
发明人： Kenichi Yasuda , Kiyohiro Furutani , Hiroshi Miyamoto
IPC分类号： H01L27/04 , G11C5/14 , G11C7/10 , G11C11/401 , H01L21/60 , H01L21/822 , H01L23/495 , H01L23/50 , H01L27/10 , H01L23/48 , H01L23/52
CPC分类号： G11C5/14 , B82Y10/00 , G11C7/1006 , G11C7/1045 , H01L23/4951 , H01L24/05 , H01L24/06 , H01L24/49 , G11C2029/1804 , H01L2223/6611 , H01L2224/04042 , H01L2224/05554 , H01L2224/05556 , H01L2224/05599 , H01L2224/06136 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/48465 , H01L2224/49113 , H01L24/48 , H01L2924/00014 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/10253 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041
摘要： A DRAM includes a package, a semiconductor chip housed in the package, and a plurality of leads each disposed from the outside of the package over the periphery of the semiconductor chip. The power supply potential is applied to some of the leads. Corresponding to one power supply lead, one power supply pad and one selection pad are formed. Corresponding to another power supply lead, another power supply pad and another selection pad are formed. Each of these two selection pads is connected or not connected to the corresponding power supply lead by bonding. As a result, one of four word configurations is selected. Since these two selection pads are disposed in the vicinity of the corresponding power supply leads, respectively, the number of times of bonding to one power supply lead is reduced.
摘要翻译： DRAM包括封装，容纳在封装中的半导体芯片，以及从半导体芯片周边的封装外部设置的多个引线。电源电位适用于某些引线。对应于一个电源引线，形成一个电源焊盘和一个选择焊盘。对应于另一个电源引线，形成另一个电源焊盘和另一个选择焊盘。这两个选择焊盘中的每一个通过结合连接或不连接到相应的电源引线。结果，选择了四个字配置之一。由于这两个选择焊盘分别设置在相应的电源引线附近，所以与一个电源引线的接合次数减少。

3. 发明授权

US5586076A Semiconductor memory device permitting high speed data transfer and high density integration 失效
标题翻译：半导体存储器件允许高速数据传输和高密度集成
公开(公告)号：US5586076A
公开(公告)日：1996-12-17
申请号：US304899
申请日：1994-09-13
申请人： Hiroshi Miyamoto , Yoshikazu Morooka , Kiyohiro Furutani , Shigeru Kikuda
发明人： Hiroshi Miyamoto , Yoshikazu Morooka , Kiyohiro Furutani , Shigeru Kikuda
IPC分类号： G11C11/401 , G11C7/10 , G11C11/409 , G11C11/4096 , G11C7/00 , G11C11/24
CPC分类号： G11C11/4096 , G11C7/10
摘要： In a memory cell array, data lines are formed into a hierarchical arrangement of sub data lines provided for every block and a main data line common to each block, and a sub data line selected by a column address among sub data lines belonging a block which are simultaneously selected by a row address is connected to a bit line. Accordingly, the sub data line length is reduced, which reduces floating capacitance, reading and writing operations can be conducted at a high speed, and sub data lines can be selectively operated. In addition, power required for charging the sub data lines can be reduced, and entire power consumption by the semiconductor memory device can be reduced as well.
摘要翻译：在存储单元阵列中，数据线被形成为每个块提供的子数据线和每个块共同的主数据线的分层布置，以及由属于块的子数据线之间的列地址选择的子数据线通过行地址同时选择连接到位线。因此，减少了子数据线的长度，这降低了浮动电容，可以高速地执行读和写操作，并且可以选择性地操作子数据线。此外，可以减少对子数据线进行充电所需的功率，并且可以减小半导体存储器件的整体功耗。

4. 发明授权

US5907509A Semiconductor memory device that can read out data at high speed 失效
标题翻译：可高速读出数据的半导体存储器件
公开(公告)号：US5907509A
公开(公告)日：1999-05-25
申请号：US978421
申请日：1997-11-25
申请人： Kiyohiro Furutani , Hiroshi Miyamoto
发明人： Kiyohiro Furutani , Hiroshi Miyamoto
IPC分类号： G11C11/401 , G11C7/22 , G11C11/4076 , G11C11/409 , G11C11/4093 , G11C11/4096 , G11C7/00
CPC分类号： G11C11/4093 , G11C11/4076 , G11C11/4096 , G11C7/22
摘要： A .phi..sub.C generation circuit provides a column address buffer control signal to a column address buffer so that the column address buffer maintains a latch operation during the operation period of a differential amplifier. The column address buffer responds to a column address buffer control signal to latch an input address signal for providing a column address signal to a .phi..sub.D and PAE generation circuit. The .phi..sub.D and PAE generation circuit provides a differential amplifier activation signal to the differential amplifier according to a column address signal and a column access activation signal. The differential amplifier responds to a differential amplifier activation signal for amplifying data applied from a data input and output line to provide the same to a selector via a readout data line.
摘要翻译： phi C生成电路向列地址缓冲器提供列地址缓冲器控制信号，使得列地址缓冲器在差分放大器的操作周期期间保持锁存操作。列地址缓冲器响应列地址缓冲器控制信号以锁存输入地址信号，以向列D和PAE生成电路提供列地址信号。 phi D和PAE生成电路根据列地址信号和列访问激活信号向差分放大器提供差分放大器激活信号。差分放大器响应于差分放大器激活信号，用于放大从数据输入和输出线施加的数据，以通过读出数据线将其提供给选择器。

5. 发明授权

US5729502A Semiconductor memory device that can read out data at high speed 失效
公开(公告)号：US5729502A
公开(公告)日：1998-03-17
申请号：US775762
申请日：1996-12-31
申请人： Kiyohiro Furutani , Hiroshi Miyamoto
发明人： Kiyohiro Furutani , Hiroshi Miyamoto
IPC分类号： G11C11/401 , G11C7/22 , G11C11/4076 , G11C11/409 , G11C11/4093 , G11C11/4096 , G11C8/00
CPC分类号： G11C11/4093 , G11C11/4076 , G11C11/4096 , G11C7/22
摘要： A .phi..sub.C generation circuit provides a column address buffer control signal to a column address buffer so that the column address buffer maintains a latch operation during the operation period of a differential amplifier. The column address buffer responds to a column address buffer control signal to latch an input address signal for providing a column address signal to a .phi..sub.D and PAE generation circuit. The .phi..sub.D and PAE generation circuit provides a differential amplifier activation signal to the differential amplifier according to a column address signal and a column access activation signal. The differential amplifier responds to a differential amplifier activation signal for amplifying data applied from a data input and output line to provide the same to a selector via a readout data line.

6. 发明授权

US5481497A Semiconductor memory device providing external output data signal in accordance with states of true and complementary read buses 失效
标题翻译：半导体存储器件根据真实和补充读取总线的状态提供外部输出数据信号
公开(公告)号：US5481497A
公开(公告)日：1996-01-02
申请号：US304749
申请日：1994-09-12
申请人： Tadaaki Yamauchi , Hiroshi Miyamoto , Yoshikazu Morooka , Kiyohiro Furutani , Makiko Aoki
发明人： Tadaaki Yamauchi , Hiroshi Miyamoto , Yoshikazu Morooka , Kiyohiro Furutani , Makiko Aoki
IPC分类号： G11C11/417 , G11C7/10 , G11C11/407 , G11C11/409 , G11C7/00
CPC分类号： G11C7/1051 , G11C7/1048
摘要： Read data supplied from one of a plurality of differential amplifier circuits is transmitted to a read data bus driver circuit via one of a plurality of CMOS transfer gates and a data latch circuit. The potential of read data bus pair is forcedly set to a low level in response to a control signal until the read data is transmitted to the read data bus driver circuit. Thereafter, the read data bus driver circuit drives the read data bus pair in accordance with the transmitted read data. Thereby, a speed of the address access operation can be increased without outputting invalid data.
摘要翻译：从多个差分放大器电路之一提供的读取数据通过多个CMOS传输门和数据锁存电路中的一个发送到读数据总线驱动电路。读取数据总线对的电位响应于控制信号被强制设置为低电平，直到读取的数据被发送到读取数据总线驱动器电路。此后，读数据总线驱动电路根据发送的读数据驱动读数据总线对。从而，可以增加地址访问操作的速度而不输出无效数据。

7. 发明授权

US08300480B2 Semiconductor device having sense amplifiers supplied with an over-drive voltage in a normal mode and supplied with a step-down voltage in a refresh mode 有权
标题翻译：具有以正常模式提供过驱动电压并在刷新模式下被提供降压电压的读出放大器的半导体器件
公开(公告)号：US08300480B2
公开(公告)日：2012-10-30
申请号：US12897399
申请日：2010-10-04
申请人： Kiyohiro Furutani
发明人： Kiyohiro Furutani
IPC分类号： G11C7/08
CPC分类号： G11C11/4074 , G11C7/02 , G11C11/406 , G11C11/40615 , G11C2211/4068
摘要： A semiconductor device which has a sense amplifier and is supplied with an external power supply voltage includes a drive signal line connected to the sense amplifier, a step up circuit generating a first voltage from the external power supply voltage, the first voltage being higher than the external power supply voltage, and a step down circuit lowering the external power supply voltage into a second voltage. For enabling the sense amplifier to perform sensing operation in a normal mode involving external access, the first voltage is applied to the drive signal line in an initial stage of the sensing operation, and thereafter the second voltage is applied to the drive signal line. In a refresh mode not involving external access, the step up circuit is shut down, and the second voltage is applied to the drive signal line from the initial stage of the sensing operation.
摘要翻译：具有读出放大器并被提供有外部电源电压的半导体器件包括连接到读出放大器的驱动信号线，从外部电源电压产生第一电压的升压电路，第一电压高于外部电源电压和降压电路将外部电源电压降低到第二电压。为了使得读出放大器能够在涉及外部访问的正常模式下执行感测操作，在感测操作的初始阶段将第一电压施加到驱动信号线，此后将第二电压施加到驱动信号线。在不涉及外部访问的刷新模式下，升压电路被关闭，并且第二电压从感测操作的初始阶段施加到驱动信号线。

8. 发明申请

US20100157713A1 Semiconductor device with refresh control circuit 失效
标题翻译：具有刷新控制电路的半导体器件
公开(公告)号：US20100157713A1
公开(公告)日：2010-06-24
申请号：US12654109
申请日：2009-12-10
申请人： Kiyohiro Furutani
发明人： Kiyohiro Furutani
IPC分类号： G11C7/00 , G11C5/14
CPC分类号： G11C11/406 , G11C8/06 , G11C8/08 , G11C8/18 , G11C11/40615 , G11C2211/4067
摘要： In a semiconductor device including a row-based control circuit applied with a current reduction circuit having a standby state and an active state, a refresh control circuit generates a refresh request signal every predetermined time interval on a self-refresh mode and time-sequentially generates an internal active signal at N times in connection with the refresh request signal once. The row-based control circuit time-sequentially refreshes information of memory cells on the based of the internal active signal at the N times. The refresh control circuit inactivates the row-based control circuit by making the current reduction circuit the standby state.
摘要翻译：在包括具有待机状态和活动状态的电流降低电路的基于行的控制电路的半导体器件中，刷新控制电路在自刷新模式下以预定的时间间隔生成刷新请求信号，并且时间顺序地产生与刷新请求信号一次的N次内部有效信号。基于行的控制电路基于N次内部有效信号时间顺序刷新存储单元的信息。刷新控制电路通过使电流还原电路处于待机状态来使基于行的控制电路失活。

9. 发明授权

US07542363B2 Semiconductor memory device enhancing reliability in data reading 有权
标题翻译：半导体存储器件提高了数据读取的可靠性
公开(公告)号：US07542363B2
公开(公告)日：2009-06-02
申请号：US11082926
申请日：2005-03-18
申请人： Takashi Kubo , Takashi Itoh , Yasuhiro Kashiwazaki , Taku Ogura , Kiyohiro Furutani
发明人： Takashi Kubo , Takashi Itoh , Yasuhiro Kashiwazaki , Taku Ogura , Kiyohiro Furutani
IPC分类号： G11C7/02
CPC分类号： G11C11/5642 , G11C5/145 , G11C7/06 , G11C7/12 , G11C16/24 , G11C16/26 , G11C16/30 , G11C2207/065 , G11C2207/2227 , G11C2211/5634 , G11C2211/5645
摘要： An internal voltage generating circuit generates and supplies a boosted voltage higher than an internal power supply voltage, as an operating power supply voltage, to a sense amplifier in a read circuit for reading data of a memory cell. A bit line precharge current supplied via an internal data line is produced from the internal power supply voltage. It is possible to provide a nonvolatile semiconductor memory device, which can perform a precise sense operation and an accurate reading of data even under a low power supply voltage condition.
摘要翻译：内部电压产生电路产生并提供高于作为工作电源电压的内部电源电压的升压电压到用于读取存储器单元的数据的读取电路中的读出放大器。从内部电源电压产生经由内部数据线提供的位线预充电电流。可以提供一种非易失性半导体存储器件，即使在低电源电压条件下也能进行精确的读出操作和数据的精确读取。

10. 发明申请

US20070285146A1 Semiconductor device with pump circuit 有权
公开(公告)号：US20070285146A1
公开(公告)日：2007-12-13
申请号：US11822184
申请日：2007-07-03
申请人： Minoru Senda , Kiyohiro Furutani , Taku Ogura , Shigehiro Kuge , Satoshi Kawasaki , Tadaaki Yamauchi
发明人： Minoru Senda , Kiyohiro Furutani , Taku Ogura , Shigehiro Kuge , Satoshi Kawasaki , Tadaaki Yamauchi
IPC分类号： H03K3/00
CPC分类号： G11C16/30 , G11C5/145 , G11C16/04 , H02M3/073 , H02M2003/071 , H02M2003/075 , H02M2003/077 , H03K3/356113
摘要： In the present semiconductor device a positive, driving pump circuit is driven by an external power supply potential EXVDD (for example of 1.8V) to generate a positive voltage VPC (for example of 2.4V). A negative pump circuit for internal operation is driven by the positive voltage VPC to generate a negative voltage VNA (for example of −9.2V) required in an erasure or similar internal operation for a word line. The negative pump circuit for internal operation can have a smaller number of stages of pump and hence consume a smaller area than when the circuit is driven by the external power supply voltage EXVDD (for example of 1.8V) as conventional.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式