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1. 发明授权

US06301163B1 Semiconductor memory device and method of checking same for defect 有权
标题翻译：半导体存储器件及其检查方法为缺陷
公开(公告)号：US06301163B1
公开(公告)日：2001-10-09
申请号：US09385582
申请日：1999-08-27
申请人： Hideto Hidaka , Mikio Asakura , Kiyohiro Furutani , Tetsuo Kato
发明人： Hideto Hidaka , Mikio Asakura , Kiyohiro Furutani , Tetsuo Kato
IPC分类号： G11C2900
CPC分类号： G11C29/24
摘要： A semiconductor memory device includes a first test row decoder (9a) for selecting memory cells in normal rows in a test mode, a second test row decoder (9b) for selecting spare memory cell rows, a first test column decoder (10a) for selecting memory cells in normal columns, and a second test column decoder (10b) for selecting spare memory cell columns. A control circuit (11) may perform switching between four combinations of the row and column decoders by using a control signal (SRT) and a control signal (SCT). All spare memory cells are tested prior to reparation of a defective memory cell for yield enhancement.
摘要翻译：一种半导体存储器件，包括用于在测试模式下选择正常行中的存储单元的第一测试行解码器（9a），用于选择备用存储单元行的第二测试行解码器（9b），用于选择的第一测试列解码器正常列中的存储单元，以及用于选择备用存储单元列的第二测试列解码器（10b）。控制电路（11）可以通过使用控制信号（SRT）和控制信号（SCT）来执行行和列解码器的四个组合之间的切换。所有备用存储器单元在修补缺陷存储器单元以进行产量增强之前被测试。

2. 发明授权

US5764576A Semiconductor memory device and method of checking same for defect 失效
公开(公告)号：US5764576A
公开(公告)日：1998-06-09
申请号：US752419
申请日：1996-11-19
申请人： Hideto Hidaka , Mikio Asakura , Kiyohiro Furutani , Tetsuo Kato
发明人： Hideto Hidaka , Mikio Asakura , Kiyohiro Furutani , Tetsuo Kato
IPC分类号： G11C11/413 , G11C11/401 , G11C29/00 , G11C29/04 , G11C29/14 , G11C29/24
CPC分类号： G11C29/24
摘要： A semiconductor memory device includes a first test row decoder (9a) for selecting memory cells in normal rows in a test mode, a second test row decoder (9b) for selecting spare memory cell rows, a first test column decoder (10a) for selecting memory cells in normal columns, and a second test column decoder (10b) for selecting spare memory cell columns. A control circuit (11) may perform switching between four combinations of the row and column decoders by using a control signal (SRT) and a control signal (SCT). All spare memory cells are tested prior to reparation of a defective memory cell for yield enhancement.

3. 发明授权

US5999464A Semiconductor memory device and method of checking same for defect 失效
公开(公告)号：US5999464A
公开(公告)日：1999-12-07
申请号：US58885
申请日：1998-04-13
申请人： Hideto Hidaka , Mikio Asakura , Kiyohiro Furutani , Tetsuo Kato
发明人： Hideto Hidaka , Mikio Asakura , Kiyohiro Furutani , Tetsuo Kato
IPC分类号： G11C11/413 , G11C11/401 , G11C29/00 , G11C29/04 , G11C29/14 , G11C29/24
CPC分类号： G11C29/24
摘要： A semiconductor memory device includes a first test row decoder (9a) for selecting memory cells in normal rows in a test mode, a second test row decoder (9b) for selecting spare memory cell rows, a first test column decoder (10a) for selecting memory cells in normal columns, and a second test column decoder (10b) for selecting spare memory cell columns. A control circuit (11) may perform switching between four combinations of the row and column decoders by using a control signal (SRT) and a control signal (SCT). All spare memory cells are tested prior to reparation of a defective memory cell for yield enhancement.

4. 发明授权

US5970507A Semiconductor memory device having a refresh-cycle program circuit 失效
标题翻译：具有刷新循环程序电路的半导体存储器件
公开(公告)号：US5970507A
公开(公告)日：1999-10-19
申请号：US676963
申请日：1996-07-08
申请人： Tetsuo Kato , Kiyohiro Furutani , Hideto Hidaka , Mikio Asakura
发明人： Tetsuo Kato , Kiyohiro Furutani , Hideto Hidaka , Mikio Asakura
IPC分类号： G11C11/403 , G11C11/406 , G11C11/409 , G06F12/00
CPC分类号： G11C11/406
摘要： In a semiconductor memory device, a self refresh cycle program circuit is provided and a refresh operation is conducted in accordance with one of the refresh cycles programmed in the refresh-cycle program circuit. The refresh cycle of the self-refresh mode is selected from a plurality of refresh-cycle types. A plurality of refresh modes allows a refresh cycle to be selected from a plurality of refresh-cycle types in accordance with a selected refresh mode.
摘要翻译：在半导体存储器件中，提供自刷新周期程序电路，并且根据在刷新周期程序电路中编程的刷新周期之一进行刷新操作。从多个刷新周期类型中选择自刷新模式的刷新周期。多个刷新模式允许根据所选择的刷新模式从多个刷新周期类型中选择刷新周期。

5. 发明授权

US06400621B2 Semiconductor memory device and method of checking same for defect 失效
标题翻译：半导体存储器件及其检查方法为缺陷
公开(公告)号：US06400621B2
公开(公告)日：2002-06-04
申请号：US09912518
申请日：2001-07-26
申请人： Hideto Hidaka , Mikio Asakura , Kiyohiro Furutani , Tetsuo Kato
发明人： Hideto Hidaka , Mikio Asakura , Kiyohiro Furutani , Tetsuo Kato
IPC分类号： G11C700
CPC分类号： G11C29/24
摘要： A semiconductor memory device includes a first test row decoder (9a) for selecting memory cells in normal rows in a test mode, a second test row decoder (9b) for selecting spare memory cell rows, a first test column decoder (10a) for selecting memory cells in normal columns, and a second test column decoder (10b) for selecting spare memory cell columns. A control circuit (11) may perform switching between four combinations of the row and column decoders by using a control signal (SRT) and a control signal (SCT). All spare memory cells are tested prior to reparation of a defective memory cell for yield enhancement.
摘要翻译：一种半导体存储器件，包括用于在测试模式下选择正常行中的存储单元的第一测试行解码器（9a），用于选择备用存储单元行的第二测试行解码器（9b），用于选择的第一测试列解码器正常列中的存储单元，以及用于选择备用存储单元列的第二测试列解码器（10b）。控制电路（11）可以通过使用控制信号（SRT）和控制信号（SCT）来执行行和列解码器的四个组合之间的切换。所有备用存储器单元在修补缺陷存储器单元以进行产量增强之前被测试。

6. 发明授权

US5898316A Mode setting circuit of semiconductor device 失效
标题翻译：半导体器件的模式设置电路
公开(公告)号：US5898316A
公开(公告)日：1999-04-27
申请号：US673244
申请日：1996-06-27
申请人： Tetsuo Kato , Tsukasa Ooishi , Hideto Hidaka , Mikio Asakura
发明人： Tetsuo Kato , Tsukasa Ooishi , Hideto Hidaka , Mikio Asakura
IPC分类号： G11C11/406 , G11C11/401 , G11C11/407 , H03K19/173
CPC分类号： G11C7/1045 , G11C11/40611 , G11C2211/4061
摘要： Two NAND gates are provided corresponding to each of a plurality of pads. By connecting a mode switching pad to power supply potential or ground potential, one of the two NAND gates provided corresponding to each pad is activated, and the other NAND gate is non-activated. As a result, different mode select signals are provided from the output of each NAND gate.
摘要翻译：对应于多个焊盘中的每一个提供两个NAND门。通过将模式切换焊盘连接到电源电位或接地电位，与每个焊盘对应的两个NAND门中的一个被激活，而另一个NAND门不被激活。结果，从每个NAND门的输出提供不同的模式选择信号。

7. 发明授权

US06288956B1 Semiconductor device having test function 失效
标题翻译：具有测试功能的半导体器件
公开(公告)号：US06288956B1
公开(公告)日：2001-09-11
申请号：US09477717
申请日：2000-01-05
申请人： Tetsushi Tanizaki , Tetsuo Kato , Mikio Asakura , Yasuhiro Konishi , Takayuki Miyamoto
发明人： Tetsushi Tanizaki , Tetsuo Kato , Mikio Asakura , Yasuhiro Konishi , Takayuki Miyamoto
IPC分类号： G11C1140
CPC分类号： G11C29/46
摘要： A semiconductor device according to the present invention includes a plurality of test mode circuits. Each test mode circuit includes a plurality of decode circuits decoding an input signal and a plurality of latch circuits. Each decode circuit generates a test mode signal. The test mode signals are held in the latch circuits. Each test mode circuit further includes decode circuits outputting a group reset signal for resetting a corresponding latch circuit. Thus, a plurality of test mode signals can be combined arbitrarily and serially.
摘要翻译：根据本发明的半导体器件包括多个测试模式电路。每个测试模式电路包括解码输入信号和多个锁存电路的多个解码电路。每个解码电路产生测试模式信号。测试模式信号保持在锁存电路中。每个测试模式电路还包括输出用于复位相应的锁存电路的组复位信号的解码电路。因此，多个测试模式信号可以任意和连续地组合。

8. 发明授权

US06327198B1 Semiconductor memory device having a test mode setting circuit 失效
标题翻译：具有测试模式设置电路的半导体存储器件
公开(公告)号：US06327198B1
公开(公告)日：2001-12-04
申请号：US09500087
申请日：2000-02-08
申请人： Tetsuo Kato , Takayuki Miyamoto , Tetsushi Tanizaki , Mikio Asakura
发明人： Tetsuo Kato , Takayuki Miyamoto , Tetsushi Tanizaki , Mikio Asakura
IPC分类号： G11C2900
CPC分类号： G11C29/12
摘要： A semiconductor memory device according to the present invention includes: a test mode setting circuit capable of serially setting a plurality of test modes in accordance with an external signal; a voltage generating circuit; a column related control circuit; a row related control circuit; and a memory cell array. In a corresponding test mode, odd-numbered word lines/even-numbered word lines are brought into a selection/non-selection state. In the corresponding test mode, a voltage of the bit line is set higher (an internal power supply voltage) or lower (a ground voltage) than an equalization voltage in a normal operation mode. Thus, a checker pattern can efficiently be written.
摘要翻译：根据本发明的半导体存储器件包括：测试模式设置电路，能够根据外部信号串行设置多个测试模式; 电压发生电路; 列相关控制电路; 一行相关控制电路; 和存储单元阵列。在对应的测试模式中，奇数字线/偶数字线被带入选择/非选择状态。在相应的测试模式中，在正常操作模式下，位线的电压被设定为高于均衡电压（内部电源电压）或更低（接地电压）。因此，可以有效地写入检查图案。

9. 发明申请

US20090129837A1 DEVELOPING DEVICE USING RECYCLED TONER 审中-公开
标题翻译：使用回收墨粉的开发设备
公开(公告)号：US20090129837A1
公开(公告)日：2009-05-21
申请号：US12255339
申请日：2008-10-21
申请人： Tetsuo Kato , Takashi Ikeda
发明人： Tetsuo Kato , Takashi Ikeda
IPC分类号： G03G21/00
CPC分类号： G03G15/0808 , G03G15/0877 , G03G15/0893 , G03G2215/00025 , G03G2215/0634 , G03G2215/0819
摘要： According to an embodiment of the present invention, a ratio of a recycled toner in a first developer is detected by an auto toner sensor for recycled toner. The carrying speed of a recycled toner mixer is controlled according to a detection result. Consequently, when recycled toner density in a recycled-toner carrying chamber increases, the recycled toner mixer is rotated at high speed to discharge the recycled toner from the recycled-toner carrying chamber at high speed.
摘要翻译：根据本发明的实施例，通过用于再循环调色剂的自动调色剂传感器来检测第一显影剂中再循环调色剂的比例。根据检测结果控制回收调色剂混合器的运送速度。因此，当再循环调色剂携带室中的再循环调色剂浓度增加时，回收的调色剂混合器以高速旋转，从再循环的调色剂承载室高速排出回收的调色剂。

10. 发明申请

US20060240710A1 Waterproof packing, waterproof connector using the same and process for producing waterproof connector 有权
标题翻译：防水包装，使用相同的防水连接器和生产防水连接器的工艺
公开(公告)号：US20060240710A1
公开(公告)日：2006-10-26
申请号：US11399475
申请日：2006-04-07
申请人： Tetsuo Kato , Kazuki Zaitsu
发明人： Tetsuo Kato , Kazuki Zaitsu
IPC分类号： H01R13/40
CPC分类号： H01R13/5205
摘要： A waterproof packing includes: a core member including an electric wire passing part inside and a contacting part for fitting to a mounting side outside; and thermoplastic adhesive adhering to at least the electric wire passing part and the contacting part, wherein the waterproof packing adheres to an electric wire with the thermoplastic adhesive of the electric wire passing part and the waterproof packing adheres to the mounting side with the thermoplastic adhesive of the contacting part by heating. A waterproof connector includes: the waterproof packing; a connector housing for inserting an electric wire having a terminal therein; and a packing receiving part of the connector housing, wherein the waterproof packing is inserted in the packing receiving part as the mounting side.
摘要翻译：防水包装包括：包括电线通过部分的芯部件和用于装配到安装侧的接触部分; 以及至少粘附在电线通过部分和接触部分上的热塑性粘合剂，其中防水填料与电线通过部分的热塑性粘合剂和防水填料粘合到电线上，其中热塑性粘合剂接触部分通过加热。防水接头包括：防水包装; 用于将具有端子的电线插入其中的连接器壳体; 以及连接器壳体的填料接收部分，其中防水密封件作为安装侧插入到填料接收部分中。

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