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1. 发明公开

US20240347088A1 VARIABLE PAGE SIZE ARCHITECTURE 审中-公开
公开(公告)号：US20240347088A1
公开(公告)日：2024-10-17
申请号：US18617019
申请日：2024-03-26
申请人： Micron Technology, Inc.
发明人： Corrado Villa
IPC分类号： G11C8/16 , G11C7/04 , G11C7/10 , G11C8/10 , G11C29/18
CPC分类号： G11C8/16 , G11C7/04 , G11C7/1012 , G11C7/1045 , G11C8/10 , G11C2029/1804 , G11C2207/2245
摘要： Methods, systems, and devices for operating a memory array with variable page sizes are described. The page size may be dynamically changed, and multiple rows of the memory array may be accessed in parallel to create the desired page size. A memory bank of the array may contain multiple memory sections, and each memory section may have its own set of sense components (e.g., sense amplifiers) to read or program the memory cells. Multiple memory sections may thus be accessed in parallel to create a memory page from multiple rows of memory cells. The addressing scheme may be modified based on the page size. The logic row address may identify the memory sections to be accessed in parallel. The memory sections may also be linked and accessing a row in one section may automatically access a row in a second memory section.

2. 发明授权

US10014056B1 Changing storage parameters 有权
公开(公告)号：US10014056B1
公开(公告)日：2018-07-03
申请号：US15598936
申请日：2017-05-18
申请人： SanDisk Technologies LLC
发明人： Aaron Lee , Yi-Chieh Chen , Anne Koh , Gulzar Kathawala , Mrinal Kochar
IPC分类号： G11C7/22 , G11C16/06 , G11C16/26 , G11C11/56 , G11C16/10 , G11C16/04 , G11C29/02
CPC分类号： G11C7/22 , G11C7/222 , G11C13/004 , G11C13/0069 , G11C16/0483 , G11C16/10 , G11C16/26 , G11C29/023 , G11C29/028 , G11C29/18 , G11C29/36 , G11C2029/0409 , G11C2029/1804
摘要： Apparatuses, systems, methods, and computer program products are disclosed for changing storage parameters. An integrated circuit (IC) memory element receives a command to change a value of a parameter associated with the IC memory element. A parameter includes a setting for one or more storage operations of an IC memory element. An IC memory element receives one or more data sets with a command. A data set includes an identifier associated with a parameter to be changed and a new value for the parameter. Each of one or more data sets is received at a same data rate as a command. An IC memory element writes, for each of one or more data sets, a new value for a parameter to a storage location associated with the parameter.

3. 发明申请

US20130283122A1 Error Correction Coding Over Multiple Memory Pages 审中-公开
标题翻译：多个内存页面上的错误校正编码
公开(公告)号：US20130283122A1
公开(公告)日：2013-10-24
申请号：US13921446
申请日：2013-06-19
申请人： Apple Inc.
发明人： Micha Anholt , Or Ordentlich , Naftali Sommer , Ofir Shalvi
IPC分类号： H03M13/29
CPC分类号： H03M13/29 , G06F11/1012 , G11C29/00 , G11C2029/1804
摘要： A method for data storage includes encoding each of multiple data items individually using a first Error Correction Code (ECC) to produce respective encoded data items. The encoded data items are stored in a memory. The multiple data items are encoded jointly using a second ECC, so as to produce a code word of the second ECC, and only a part of the code word is stored in the memory. The stored encoded data items are recalled from the memory and the first ECC is decoded in order to reconstruct the data items. Upon a failure to reconstruct a given data item from a respective given encoded data item by decoding the first ECC, the given data item is reconstructed based on the part of the code word of the second ECC and on the encoded data items other than the given encoded data item.
摘要翻译：一种用于数据存储的方法包括使用第一纠错码（ECC）分别对多个数据项中的每一个进行编码，以产生相应的编码数据项。编码数据项存储在存储器中。多个数据项使用第二ECC共同编码，以便产生第二ECC的代码字，并且仅一部分代码字被存储在存储器中。存储的编码数据项被从存储器调用，并且第一ECC被解码以便重构数据项。在通过解码第一ECC无法从相应的给定编码数据项中重建给定数据项时，基于第二ECC的代码字的部分和除了给定的编码数据项之外的编码数据项重建给定数据项编码数据项。

4. 发明授权

US07937630B2 Semiconductor memory and method for testing the same 有权
标题翻译：半导体存储器及其测试方法
公开(公告)号：US07937630B2
公开(公告)日：2011-05-03
申请号：US11797699
申请日：2007-05-07
申请人： Kaoru Mori
发明人： Kaoru Mori
IPC分类号： G11C29/00
CPC分类号： G11C29/16 , G11C2029/1804
摘要： A semiconductor memory in which arbitrary operation mode information is set in a plurality of CRs at test time and by which a test cost is reduced and a method for testing such a semiconductor memory. The plurality of CRs hold operation mode information. When a CR control circuit detects write commands to write to an address for register access or read commands to read from the address for register access in a predetermined order, the CR control circuit updates the operation mode information for each of the plurality of CRs on a time division basis. A command generation section generates the write commands, the read commands, or a test start command by which write operation or read operation does not occur, in response to a control signal from the outside. In addition, the command generation section regenerates the test start command each time the plurality of CRs are updated. A data pad compression circuit changes the operation mode information to be written to the plurality of CRs by using test data inputted to part of data pads, after inverting the test data or in its original condition according to a code, as data for a rest of the data pads, the code represented by part of an address inputted at the time of the test start command being sent.
摘要翻译：一种半导体存储器，其中在测试时间内在多个CR中设置任意操作模式信息，并且测试成本降低，并且测试这种半导体存储器的方法。多个CR保持操作模式信息。当CR控制电路检测写入命令以写入寄存器访问的地址或读取命令以按预定顺序从地址读取寄存器访问时，CR控制电路更新在多个CR中的每一个的操作模式信息时分基础。响应于来自外部的控制信号，命令生成部分生成写入命令，读取命令或者不发生写入操作或读取操作的测试开始命令。另外，每当更新多个CR时，命令生成部重新生成测试开始命令。数据块压缩电路通过使用输入到数据块的一部分的测试数据，在将测试数据或其原始状态根据代码反转之后，将待写入的操作模式信息改变为用于其余部分的数据数据焊盘，由发送测试开始命令时输入的地址的一部分表示的代码。

5. 发明授权

US07454672B2 Semiconductor memory device testable with a single data rate and/or dual data rate pattern in a merged data input/output pin test mode 有权
标题翻译：半导体存储器件可以在合并的数据输入/输出引脚测试模式中以单个数据速率和/或双数据速率模式进行测试
公开(公告)号：US07454672B2
公开(公告)日：2008-11-18
申请号：US10748906
申请日：2003-12-30
申请人： Jong-Cheol Lee , Su-Chul Kim , Uk-Rae Cho
发明人： Jong-Cheol Lee , Su-Chul Kim , Uk-Rae Cho
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/1201 , G11C29/48 , G11C2029/1804
摘要： Provided is a semiconductor memory device testable with a single data rate (SDR) or a dual data rate (DDR) pattern in a merged data input/output pin (DQ) test mode. The device includes a first path circuit, a second path circuit, and a merged output generator configured to generate a merged data bit having a SDR and/or DDR pattern.
摘要翻译：提供了在合并的数据输入/输出引脚（DQ）测试模式中可以以单个数据速率（SDR）或双数据速率（DDR）模式进行测试的半导体存储器件。该装置包括第一路径电路，第二路径电路和被配置为生成具有SDR和/或DDR模式的合并数据位的合并输出发生器。

6. 发明授权

US07260700B2 Method and apparatus for separating native, functional and test configurations of memory 有权
标题翻译：用于分离存储器的本机，功能和测试配置的方法和装置
公开(公告)号：US07260700B2
公开(公告)日：2007-08-21
申请号：US10954708
申请日：2004-09-30
申请人： Ghasi R. Agrawal , Willie K. Chan
发明人： Ghasi R. Agrawal , Willie K. Chan
IPC分类号： G06F12/00
CPC分类号： G11C29/34 , G11C2029/1804
摘要： A method for allowing native, functional, and test configurations of a memory to be independent of one another includes steps as follows. A memory is first provided. The memory has a native configuration including k words and n data output pins, k and n being positive integers. Each of the k words has a width of n bits. Then the n data output pins are connected to a programmable multiplexer for multiplexing the n data output pins into at least one group of data output pins of the programmable multiplexer. Each of the at least one group of data output pins has no more than n data output pins and is suitable for enabling the memory to have at least one of a test configuration or a functional configuration. At user's discretion, the test configuration may or may not have a width of n bits, the functional configuration may or may not have a width of n bits, and the test configuration and the functional configuration may or may not have the same width.
摘要翻译：允许存储器的本机，功能和测试配置彼此独立的方法包括以下步骤。首先提供内存。存储器具有包括k个字和n个数据输出引脚的原始配置，k和n是正整数。 k个字中的每一个都具有n位的宽度。然后n个数据输出引脚连接到可编程多路复用器，用于将n个数据输出引脚复用到可编程多路复用器的至少一组数据输出引脚中。所述至少一组数据输出引脚中的每一个具有不超过n个数据输出引脚，并且适于使得存储器具有测试配置或功能配置中的至少一个。根据用户的判断，测试配置可以具有或可以不具有n位的宽度，功能配置可以具有或可以不具有n位的宽度，并且测试配置和功能配置可以具有或可以不具有相同的宽度。

7. 发明申请

US20060109724A1 Memory device capable of changing data output mode 失效
公开(公告)号：US20060109724A1
公开(公告)日：2006-05-25
申请号：US11131544
申请日：2005-05-17
申请人： Jun Chung
发明人： Jun Chung
IPC分类号： G11C29/00
CPC分类号： G11C7/1045 , G11C29/1201 , G11C29/48 , G11C29/785 , G11C29/846 , G11C2029/1804 , G11C2207/105
摘要： Disclosed herein is a memory device capable of changing data output modes. According to the present invention, an address that is input to a circuit, which is designed in 8-bit output mode, is internally modified, to operate in 16-bit output mode, and a test operation is performed in 8-bit output mode. As such, two kinds of output mode circuits can be tested in one test equipment. Accordingly, test efficiency can be enhanced and costs can be saved.

8. 发明申请

US20050195666A1 Memory device including parallel test circuit 有权
标题翻译：存储器件包括并联测试电路
公开(公告)号：US20050195666A1
公开(公告)日：2005-09-08
申请号：US10879175
申请日：2004-06-30
申请人： Yun Hong , Shin Chu
发明人： Yun Hong , Shin Chu
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/40 , G11C29/1201 , G11C29/48 , G11C2029/1804
摘要： A memory device including a parallel test circuit can overcome a channel deficiency phenomenon of test equipment by reducing the number of input/output pads. The memory device including a parallel test circuit comprises a burst length regulating block, a parallel test block, an output block and a plurality of input/output pads. The burst length regulating block sets a second burst length at a test mode which is longer than a first burst length at a normal mode. The parallel test block compresses data and tests the compressed data by a repair unit. The output block sequentially outputs data outputted from at least two or more parallel test blocks depending on the second burst length. The plurality of input/output pads externally output data outputted from the output block.
摘要翻译：包括并行测试电路的存储器件可以通过减少输入/输出焊盘的数量来克服测试设备的通道不足现象。包括并行测试电路的存储器件包括突发长度调节块，并行测试块，输出块和多个输入/输出焊盘。突发长度调节块在正常模式下在比第一突发长度长的测试模式下设置第二突发长度。并行测试块通过修复单元压缩数据并测试压缩数据。输出块根据第二突发长度顺序地输出从至少两个或更多个并行测试块输出的数据。多个输入/输出板从外部输出从输出块输出的数据。

9. 发明申请

US20030015792A1 Memory chip and semiconductor device using the memory chip and manufacturing method of those 失效
标题翻译：内存芯片和半导体器件采用的是内存芯片及其制造方法
公开(公告)号：US20030015792A1
公开(公告)日：2003-01-23
申请号：US10190500
申请日：2002-07-09
发明人： Yukihiro Urakawa
IPC分类号： H01L023/34
CPC分类号： H01L25/18 , G11C5/04 , G11C7/1045 , G11C11/005 , G11C29/006 , G11C2029/1804 , H01L22/20 , H01L22/22 , H01L23/544 , H01L24/45 , H01L24/48 , H01L24/73 , H01L25/0652 , H01L25/0655 , H01L27/10897 , H01L2223/54406 , H01L2223/5446 , H01L2223/54473 , H01L2223/5448 , H01L2224/16145 , H01L2224/32225 , H01L2224/451 , H01L2224/48137 , H01L2224/48227 , H01L2224/73265 , H01L2924/01019 , H01L2924/01079 , H01L2924/1305 , H01L2924/13091 , H01L2924/19041 , H01L2924/00012 , H01L2924/00 , H01L2924/00015
摘要： In a wafer, a plurality of basic chips F is arranged therein. The basic chip F has a memory capacity of i-mega bytes. By dicing, a memory chip including four basic chips F is cut out of the wafer. The memory chip has a memory capacity of 4nulli-mega bytes. A Dicing line is interposed between four basic chips F configuring the memory chip. Four basic chips F can change a word organization by a control signal individually.
摘要翻译：在晶片中，配置有多个基本芯片F. 基本芯片F具有i兆字节的存储容量。通过切割，从晶片切出包括四个基本芯片F的存储芯片。存储器芯片的存储容量为4xi兆字节。切割线插入配置存储器芯片的四个基本芯片F之间。四个基本芯片F可以通过单独的控制信号改变单词组织。

10. 发明授权

US11961588B2 Variable page size architecture 有权
公开(公告)号：US11961588B2
公开(公告)日：2024-04-16
申请号：US17590528
申请日：2022-02-01
申请人： Micron Technology, Inc.
发明人： Corrado Villa
IPC分类号： G11C8/16 , G11C7/04 , G11C7/10 , G11C8/10 , G11C29/18
CPC分类号： G11C8/16 , G11C7/04 , G11C7/1012 , G11C7/1045 , G11C8/10 , G11C2029/1804 , G11C2207/2245
摘要： Methods, systems, and devices for operating a memory array with variable page sizes are described. The page size may be dynamically changed, and multiple rows of the memory array may be accessed in parallel to create the desired page size. A memory bank of the array may contain multiple memory sections, and each memory section may have its own set of sense components (e.g., sense amplifiers) to read or program the memory cells. Multiple memory sections may thus be accessed in parallel to create a memory page from multiple rows of memory cells. The addressing scheme may be modified based on the page size. The logic row address may identify the memory sections to be accessed in parallel. The memory sections may also be linked and accessing a row in one section may automatically access a row in a second memory section.

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