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91. 发明授权

US07485486B2 Photodiode for multiple wavelength operation 有权
标题翻译：用于多波长操作的光电二极管
公开(公告)号：US07485486B2
公开(公告)日：2009-02-03
申请号：US11532762
申请日：2006-09-18
申请人： Dong Zheng , Phillip J. Benzel , Joy Jones , Alexander Kalnitsky , Perumal Ratman
发明人： Dong Zheng , Phillip J. Benzel , Joy Jones , Alexander Kalnitsky , Perumal Ratman
IPC分类号： H01L21/00
CPC分类号： H01L27/1462 , H01L27/1463 , H01L31/02165
摘要： A method of a fabricating a multiple wavelength adapted photodiode and resulting photodiode includes the steps of providing a substrate having a first semiconductor type surface region on at least a portion thereof, implanting and forming a second semiconductor type shallow surface layer into the surface region, and forming a multi-layer anti-reflective coating (ARC) on the shallow surface layer. The forming step includes depositing or forming a thin oxide layer on the shallow surface layer and depositing a second dielectric layer different from the thin oxide layer on the thin oxide layer. An etch stop is formed on the second dielectric, wherein the etch stop includes at least one layer resistant to oxide etch. At least one oxide including layer (e.g. ILD) is then deposited on the etch stop. The oxide including layer and etch stop are then removed to expose at least a portion of the ARC to the ambient.
摘要翻译：一种制造多波长适应光电二极管和所得光电二极管的方法包括以下步骤：在其至少一部分上提供具有第一半导体类型表面区域的衬底，将表面区域中的第二半导体型浅表面层注入并形成，以及在浅表面层上形成多层抗反射涂层（ARC）。形成步骤包括在浅表面层上沉积或形成薄氧化物层，并在薄氧化物层上沉积不同于薄氧化物层的第二电介质层。蚀刻停止件形成在第二电介质上，其中蚀刻停止层包括至少一层抵抗氧化物蚀刻的层。然后将至少一种包括层（例如ILD）的氧化物沉积在蚀刻停止件上。然后去除包括氧化物层和蚀刻停止层，以将ARC的至少一部分暴露于环境中。

92. 发明申请

US20080266959A1 MEMORY ARRAY OF FLOATING GATE-BASED NON-VOLATILE MEMORY CELLS 有权
标题翻译：基于盖帽的不挥发性记忆细胞的记忆阵列
公开(公告)号：US20080266959A1
公开(公告)日：2008-10-30
申请号：US11861111
申请日：2007-09-25
申请人： Hosam Haggag , Alexander Kalnitsky , Edgardo Laber , Michael D. Church , Yun Yue
发明人： Hosam Haggag , Alexander Kalnitsky , Edgardo Laber , Michael D. Church , Yun Yue
IPC分类号： G11C16/04
CPC分类号： G11C16/0433
摘要： A memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a high voltage access transistor, a floating gate memory transistor electrically connected to the access transistor, and a coupling capacitor electrically connected to the memory transistor. A first set of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A second set of word lines are each electrically connected to the access transistor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the access transistor in each of the memory cells in a respective column. A second set of bit lines are each electrically connected to the memory transistor in each of the memory cells in a respective column. Various combinations of voltages can be applied to the word lines and bit lines in operations to program, erase, read, or inhibit a logic state stored by the memory transistor in one or more of the memory cells.
摘要翻译：存储器阵列包括以行和列的矩阵组织的多个存储器单元。每个存储单元包括高电压存取晶体管，电连接到存取晶体管的浮动栅极存储晶体管和电连接到存储晶体管的耦合电容器。第一组字线分别电连接到相应行中的每个存储器单元中的电容器。第二组字线各自电连接到相应行中的每个存储单元中的存取晶体管。第一组位线分别电连接到相应列中每个存储单元中的存取晶体管。第二组位线分别电连接到相应列中每个存储器单元中的存储晶体管。在操作中可以对字线和位线施加电压的各种组合，以对存储器晶体管存储在一个或多个存储器单元中的逻辑状态进行编程，擦除，读取或禁止。

93. 发明申请

US20080136336A1 BACKLIGHT CONTROL USING LIGHT SENSORS WITH INFRARED SUPPRESSION 有权
标题翻译：使用具有红外抑制的光传感器的背光控制
公开(公告)号：US20080136336A1
公开(公告)日：2008-06-12
申请号：US11950325
申请日：2007-12-04
申请人： Alexander Kalnitsky , Dong Zheng , Joy Jones , Xijian Lin , Gregory Cestra , Phillip J. Benzel
发明人： Alexander Kalnitsky , Dong Zheng , Joy Jones , Xijian Lin , Gregory Cestra , Phillip J. Benzel
IPC分类号： H05B37/02
CPC分类号： H05B33/0854 , G09G3/3406 , G09G2320/0626 , G09G2360/144
摘要： Described herein are light sensors that primarily respond to visible light while suppressing infrared light. Also described herein are systems the incorporate such light sensors. Such a system can include a display, a light source to backlight the display and a controller to control the brightness of the light source based on feedback received from such light sensors. Described herein are also methods for controlling backlighting.
摘要翻译：这里描述的是主要响应可见光同时抑制红外光的光传感器。这里也描述了并入这种光传感器的系统。这样的系统可以包括显示器，用于背光显示器的光源和控制器，以基于从这种光传感器接收的反馈来控制光源的亮度。这里也描述了控制背光的方法。

94. 发明申请

US20080044973A1 Method and apparatus for shielding tunneling circuit and floating gate for integration of a floating gate voltage reference in a general purpose CMOS technology 失效
标题翻译：用于屏蔽隧道电路和浮栅的方法和装置，用于在通用CMOS技术中集成浮栅参考电压
公开(公告)号：US20080044973A1
公开(公告)日：2008-02-21
申请号：US11639658
申请日：2006-12-14
申请人： Alexander Kalnitsky , John M. Caruso
发明人： Alexander Kalnitsky , John M. Caruso
IPC分类号： H01L21/336
CPC分类号： G11C27/005 , G11C16/3418 , H01L27/115 , H01L27/11521 , H01L27/11558 , H01L29/7883
摘要： A method and corresponding structure for shielding a floating gate tunneling element. The method comprises disposing a floating gate over a gate oxide using standard CMOS processing in two active areas defined by first and second doped well regions formed in a substrate surrounded by field oxide, and forming a floating gate shield layer so as to enclose the floating gate. The floating gate includes a first floating gate portion over an active area in the first doped well region and a second floating gate portion over the active area in the second doped well region. The first floating gate portion is substantially smaller than the second floating gate portion so as to enable adequate voltage coupling for Fowler-Nordheim tunneling to occur between the first doped well region and the first floating gate portion. The direction of tunneling is determined by high voltage application to one of the doped well regions.
摘要翻译：一种用于屏蔽浮动栅极隧道元件的方法和相应的结构。该方法包括使用在由场氧化物包围的衬底中形成的第一和第二掺杂阱区域限定的两个有源区域中的标准CMOS处理在栅极氧化物上设置浮置栅极，以及形成浮置栅极屏蔽层以便包围浮置栅极。浮置栅极包括在第一掺杂阱区域中的有源区域上的第一浮动栅极部分和位于第二掺杂阱区域中的有源区域上的第二浮动栅极部分。第一浮栅部分基本上小于第二浮栅部分，以便能够在第一掺杂阱区域和第一浮栅部分之间产生用于Fowler-Nordheim隧道的足够的电压耦合。通过高压施加到掺杂阱区之一来确定隧道的方向。

95. 发明授权

US06645803B1 Method for modifying the doping level of a silicon layer 失效
标题翻译：修改硅层掺杂浓度的方法
公开(公告)号：US06645803B1
公开(公告)日：2003-11-11
申请号：US08713083
申请日：1996-09-12
申请人： Alexander Kalnitsky , Arnaud Lepert
发明人： Alexander Kalnitsky , Arnaud Lepert
IPC分类号： H01L218234
CPC分类号： H01L28/20 , H01C17/26 , H01L21/28061 , H01L21/321
摘要： A method for modifying the doping level of a doped silicon layer including the steps of coating the silicon layer with a silicide layer made of a refractory metal, and heating the interface region between the silicon and the silicide to a predetermined temperature. The method may be applied to the fabrication of an adjustable resistor or a MOS transistor having an adjustable threshold.
摘要翻译：一种用于修改掺杂硅层的掺杂水平的方法，包括以下步骤：用难熔金属制成的硅化物层涂覆硅层，并将硅和硅化物之间的界面区域加热至预定温度。该方法可以应用于具有可调阈值的可调电阻器或MOS晶体管的制造。

96. 发明授权

US06593640B1 Bipolar transistor and methods of forming bipolar transistors 失效
标题翻译：双极晶体管和形成双极晶体管的方法
公开(公告)号：US06593640B1
公开(公告)日：2003-07-15
申请号：US10114526
申请日：2002-04-01
申请人： Alexander Kalnitsky , Sudarsan Uppili
发明人： Alexander Kalnitsky , Sudarsan Uppili
IPC分类号： H01L27082
CPC分类号： H01L29/1004 , H01L29/161 , H01L29/167
摘要： A bipolar transistor comprises a base region and an an extrinsic base region being located generally adjacent to the base region. The extrinsic base region has implanted therein a dopant and a dopant diffusion-retarding substance. The dopant diffusion-retarding substance serves to reduce the diffusion of the dopant into the base region. Preferably, the dopant and diffusion-retarding substances are implanted such that there is a buffer zone in the extrinsic base region immediately adjacent to the base region into which the dopant may diffuse after implantation. The dopant may for example be boron, and the dopant diffusion-retarding substance may for example be a group IV element such as carbon or germanium.
摘要翻译：双极晶体管包括基本区域和大致相邻于基极区域的非本征基极区域。外部基极区域注入掺杂剂和掺杂剂扩散阻滞物质。掺杂剂扩散阻滞物质用于减少掺杂剂扩散到基极区域中。优选地，注入掺杂剂和扩散阻滞物质，使得在植入后掺杂剂可以扩散的基极区域紧邻的外在碱性区域中存在缓冲区。掺杂剂可以例如是硼，并且掺杂剂扩散阻滞物质可以例如是IV族元素，例如碳或锗。

97. 发明授权

US06380571B1 CMOS compatible pixel cell that utilizes a gated diode to reset the cell 有权
标题翻译： CMOS兼容像素单元，利用门控二极管复位单元
公开(公告)号：US06380571B1
公开(公告)日：2002-04-30
申请号：US09173276
申请日：1998-10-14
申请人： Alexander Kalnitsky , Albert Bergemont , Pavel Poplevine
发明人： Alexander Kalnitsky , Albert Bergemont , Pavel Poplevine
IPC分类号： H01L31113
CPC分类号： H01L27/14654 , H01L27/14609 , H01L27/1463
摘要： The potential on a pixel cell having a gated diode and a read out transistor is set to an initial level prior to an image integration period. During the image integration period, absorbed photons cause the potential on the pixel cell to change. After the image integration period, the pixel cell is then reset and read out by applying a number of pulses to the gated diode. Each of the pulses causes a fixed amount of charge to be injected into the cell. When the potential on the cell has again returned to the initial level, the number of absorbed photons is determined by counting the number of pulses that were required to return the potential to the initial level. The read out transistor is used to determine when the potential is at the initial level by biasing the transistor to output a current that corresponds to the potential on the pixel cell.
摘要翻译：具有门控二极管和读出晶体管的像素单元上的电位在图像积分周期之前被设置为初始电平。在图像积分期间，吸收的光子导致像素单元的电位发生变化。在图像积分周期之后，通过向门控二极管施加多个脉冲来复位和读出像素单元。每个脉冲导致固定量的电荷注入到电池中。当电池上的电位再次恢复到初始电平时，通过计算将电位恢复到初始电平所需的脉冲数来确定吸收光子的数量。读出晶体管用于通过偏置晶体管来输出对应于像素单元上的电位的电流来确定电位何时处于初始电平。

98. 发明授权

US06277724B1 Method for forming an array of sidewall-contacted antifuses having diffused bit lines 有权
标题翻译：用于形成具有扩散位线的侧壁接触反熔丝阵列的方法
公开(公告)号：US06277724B1
公开(公告)日：2001-08-21
申请号：US09233370
申请日：1999-01-19
申请人： Albert Bergemont , Alexander Kalnitsky
发明人： Albert Bergemont , Alexander Kalnitsky
IPC分类号： H01L2144
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： An array of sidewall-contacted antifuses is formed by a method that reduces the sensitivity of the array to masking alignment errors. The method forms a plurality of spaced-apart bit lines in a semiconductor material. Rows and columns of insulated contacts are formed on the semiconductor material such that each bit line is contacted a plurality of times by an insulated contact. In each row of contacts, each contact has an exposed sidewall. A plurality of word lines are then formed over the contacts such that a word line is formed over each exposed sidewall in a row of exposed sidewalls. The word lines include a dielectric layer and an overlying layer of conductive material.
摘要翻译：通过一种降低阵列对屏蔽对准误差的灵敏度的方法形成侧壁接触的反熔丝阵列。该方法在半导体材料中形成多个间隔开的位线。绝缘触点的行和列形成在半导体材料上，使得每个位线通过绝缘接触多次接触。在每排触点中，每个触点具有暴露的侧壁。然后在触点上形成多个字线，使得在一排暴露的侧壁中的每个暴露的侧壁上形成字线。字线包括电介质层和导电材料的上覆层。

99. 发明授权

US06262460B1 Long channel MOS transistor that utilizes a schottky diode to increase the threshold voltage of the transistor 有权
标题翻译：利用肖特基二极管来增加晶体管的阈值电压的长沟道MOS晶体管
公开(公告)号：US06262460B1
公开(公告)日：2001-07-17
申请号：US09480722
申请日：2000-01-07
申请人： Alexander Kalnitsky , Pavel Poplevine , Albert Bergemont
发明人： Alexander Kalnitsky , Pavel Poplevine , Albert Bergemont
IPC分类号： H01L2972
CPC分类号： H01L27/0629
摘要： When the threshold voltage of a long-channel transistor is set during the same dopant step of a manufacturing process that sets the threshold voltage of a short-channel transistor, the threshold voltage of the long-channel transistor is increased by connecting the long-channel transistor in series with a schottky diode.
摘要翻译：当在设定短沟道晶体管的阈值电压的制造过程的相同掺杂剂步骤期间设置长沟道晶体管的阈值电压时，通过连接长沟道晶体管的阈值电压来增加长沟道晶体管的阈值电压晶体管与肖特基二极管串联。

100. 发明授权

US06184557B2 I/O circuit that utilizes a pair of well structures as resistors to delay an ESD event and as diodes for ESD protection 有权
标题翻译：使用一对阱结构作为电阻延迟ESD事件的I / O电路和用于ESD保护的二极管
公开(公告)号：US06184557B2
公开(公告)日：2001-02-06
申请号：US09239344
申请日：1999-01-28
申请人： Pavel Poplevine , Alexander Kalnitsky , Hengyang (James) Lin , Albert Bergemont
发明人： Pavel Poplevine , Alexander Kalnitsky , Hengyang (James) Lin , Albert Bergemont
IPC分类号： H01L2362
CPC分类号： H01L27/0255 , H01L27/0288
摘要： The n-channel and p-channel driver transistors of an I/O circuit are electrostatic discharge (ESD) protected by utilizing a pair of well structures that resistively delay an ESD event from reaching the driver transistors, and that form diodes that direct the ESD event to the supply rail or ground of the circuit.
摘要翻译： I / O电路的n沟道和p沟道驱动器晶体管是通过利用一对阱电阻保护的静电放电（ESD），其阻止ESD事件到达驱动器晶体管，并且形成指示ESD的二极管事件到电路的电源轨或接地。

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