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91. 发明授权

US06525397B1 Extended drain MOSFET for programming an integrated fuse element to high resistance in low voltage process technology 有权
标题翻译：扩展漏极MOSFET，用于在低电压工艺技术中将集成保险丝元件编程为高电阻
公开(公告)号：US06525397B1
公开(公告)日：2003-02-25
申请号：US09376161
申请日：1999-08-17
申请人： Alexander Kalnitsky , Pavel Poplevine , Albert Bergemont
发明人： Alexander Kalnitsky , Pavel Poplevine , Albert Bergemont
IPC分类号： H01L2900
CPC分类号： H01L23/5256 , H01L27/101 , H01L2924/0002 , H01L2924/00
摘要： An integrated fuse element is capable of being programmed to high resistance in low voltage process technology. The fuse includes a stack of an undoped polysilicon layer and a silicide layer. A voltage applied across the stack is increases until a first agglomeration event occurs, whereby a discontinuity is formed in the silicide layer. The current is further increased to cause a second agglomeration event whereby the size of the discontinuity is increased. Each agglomeration event increases the resistance of the fuse. An extended-drain MOS transistor, capable of sustaining high voltage, is connected in series with the fuse for programming the fuse. The transistor includes: a well region in a substrate, the well region forming the drain of the transistor; an insulating trench in the well; and a polysilicon gate extending over a portion of the substrate, a portion of the well and a portion of the trench, wherein upon reverse-biasing the junction between the well and the substrate a depletion region is formed which encompasses at least the entire portion of the surface region of the well over which the polysilicon extends.
摘要翻译：集成的熔丝元件能够被编程为低电压工艺技术中的高电阻。熔丝包括未掺杂的多晶硅层和硅化物层的堆叠。施加在堆叠上的电压增加直到发生第一附聚事件，由此在硅化物层中形成不连续性。电流进一步增加以引起第二聚集事件，从而增加不连续性的大小。每个附聚事件会增加保险丝的电阻。能够保持高电压的延伸漏极MOS晶体管与保险丝串联连接，以对熔丝进行编程。晶体管包括：衬底中的阱区，形成晶体管的漏极的阱区; 井中的绝缘沟槽; 以及在所述衬底的一部分上延伸的多晶硅栅极，所述阱的一部分和所述沟槽的一部分，其中在反向偏置所述阱和所述衬底之间的结点时，形成耗尽区，所述耗尽区至少包括多晶硅延伸的阱的表面区域。

92. 发明授权

US06368917B1 Methods of fabricating floating gate semiconductor device with reduced erase voltage 有权
标题翻译：制造具有降低的擦除电压的浮栅半导体器件的方法
公开(公告)号：US06368917B1
公开(公告)日：2002-04-09
申请号：US09721604
申请日：2000-11-21
申请人： Alexander Kalnitsky , Albert Bergemont
发明人： Alexander Kalnitsky , Albert Bergemont
IPC分类号： H01L21336
CPC分类号： H01L29/66825 , H01L27/11553
摘要： The present invention provides a method for forming a shaped floating gate on an integrated circuit substrate. A trench is etched in a surface of the integrated circuit substrate such that a tip is formed. The tip may be defined by a first sidewall that is approximately perpendicular to the surface of the integrated circuit substrate and a second sidewall that is disposed at an angle to the surface of the integrated circuit substrate. A dielectric layer is then formed over the substrate surface and conforming to the trench. Next, a conductive layer is deposited above the dielectric layer such that it fills the trench. The conductive layer is then etched such that a floating gate is defined. A bottom portion of the floating gate is then contained by the trench. The resulting floating gate and semiconductor device includes a dielectric layer disposed above an integrated circuit substrate surface. The substrate surface defines a trench having a tip that may be defined by a first sidewall and a second sidewall. A conductive layer is formed above the dielectric layer such that it fills the trench and defines a floating gate having a tip contained by the trench. In addition, a diffusion region may be disposed in the integrated circuit substrate such that the tip of the floating gate points into the diffusion region.
摘要翻译：本发明提供一种在集成电路基板上形成成形浮栅的方法。在集成电路基板的表面中蚀刻沟槽，从而形成尖端。尖端可以由大致垂直于集成电路基板的表面的第一侧壁和与集成电路基板的表面成角度设置的第二侧壁限定。然后在衬底表面上形成电介质层并且与沟槽一致。接下来，在电介质层上方沉积导电层，使其填充沟槽。然后蚀刻导电层，使得限定浮动栅极。然后，浮动栅极的底部被沟槽包围。所得的浮栅和半导体器件包括设置在集成电路衬底表面上方的电介质层。衬底表面限定了具有可由第一侧壁和第二侧壁限定的尖端的沟槽。导电层形成在电介质层之上，使得它填充沟槽并且限定具有由沟槽包含的尖端的浮动栅极。此外，可以在集成电路基板中设置扩散区域，使得浮动栅极的尖端指向扩散区域。

93. 发明授权

US06365463B2 Method for forming a high-precision analog transistor with a low threshold voltage roll-up and a digital transistor with a high threshold voltage roll-up 有权
标题翻译：用于形成具有低阈值电压累加的高精度模拟晶体管和具有高阈值电压卷积的数字晶体管的方法
公开(公告)号：US06365463B2
公开(公告)日：2002-04-02
申请号：US09316450
申请日：1999-05-21
申请人： Alexander Kalnitsky , Albert Bergemont
发明人： Alexander Kalnitsky , Albert Bergemont
IPC分类号： H01L21336
CPC分类号： H01L21/823456 , H01L21/82345
摘要： A process for forming high-precision analog transistors with a low threshold voltage roll-up and digital transistors with a high threshold voltage roll-up is disclosed. The process selectively implants the polysilicon layer that forms the gates of the analog transistors so that the doping concentration of the analog gates is greater than the doping concentration of the digital gates.
摘要翻译：公开了一种用于形成具有低阈值电压卷积的高精度模拟晶体管和具有高阈值电压卷积的数字晶体管的工艺。该过程选择性地植入形成模拟晶体管的栅极的多晶硅层，使得模拟栅极的掺杂浓度大于数字栅极的掺杂浓度。

94. 发明授权

US06327187B1 EPROM and flash memory cells with source-side injection and a gate dielectric that traps hot electrons during programming 有权
标题翻译：具有源侧注入的EPROM和闪存单元以及在编程期间捕获热电子的栅极电介质
公开(公告)号：US06327187B1
公开(公告)日：2001-12-04
申请号：US09665612
申请日：2000-09-18
申请人： Albert Bergemont , Alexander Kalnitsky
发明人： Albert Bergemont , Alexander Kalnitsky
IPC分类号： G11C1604
CPC分类号： G11C16/10 , G11C16/0408 , H01L29/4232 , H01L29/792
摘要： An electrically-programmable read-only-memory (EPROM) and a flash memory cell having source-side injection are formed with a gate dielectric material, and a pair of gates that are both formed on the gate dielectric material. The gate dielectric material has substantially more electron traps than hole traps so that the gate dielectric material is capable of having a negative potential which is sufficient to inhibit the formation of a conductive channel during a read operation.
摘要翻译：具有电可编程只读存储器（EPROM）和具有源极侧注入的闪存单元由栅极电介质材料形成，并且一对栅极都形成在栅极电介质材料上。栅极电介质材料具有比空穴阱更多的电子陷阱，使得栅极电介质材料能够具有足够的负电位，以在读取操作期间抑制导电通道的形成。

95. 发明授权

US06238979B1 Process for fabricating EEPROM memory cell array embedded on core CMOS 有权
标题翻译：用于制造嵌入在核心CMOS上的EEPROM存储单元阵列的工艺
公开(公告)号：US06238979B1
公开(公告)日：2001-05-29
申请号：US09599052
申请日：2000-06-21
申请人： Albert Bergemont
发明人： Albert Bergemont
IPC分类号： H01L218247
CPC分类号： H01L27/11521 , G11C2216/10 , H01L27/115 , H01L27/11558
摘要： A process of fabricating an electrically erasable programmable read only memory cell embedded on core complementary metal oxide silicon for analog applications. First, a P-well region is formed. A first N-well region is formed within the P-well, and a second N-well region is formed within the P-well spaced apart from the first N-well. A first field oxide layer is deposited over the P-well, the first N-well, and the second N-well. A high-voltage oxide layer is grown over the first field oxide layer. A first photoresist mask which defines a tunneling window is then overlaid. The first field oxide layer and the high-voltage oxide layer are then etched. Afterwards, the first photoresist mask is stripped. A tunnel oxide layer is grown. A polysilicon layer is grown on top of the tunnel oxide layer and then doped. A second photoresist mask which defines a floating gate is overlaid on top of the polysilicon layer. The polysilicon layer is then etched, and the second photoresist mask is stripped away.
摘要翻译：制造嵌入在用于模拟应用的核心互补金属氧化物硅上的电可擦除可编程只读存储器单元的工艺。首先，形成P阱区域。在P阱内形成第一N阱区，并且在与第一N阱间隔开的P阱内形成第二N阱区。第一场氧化物层沉积在P阱，第一N阱和第二N阱上。在第一场氧化物层上生长高电压氧化物层。然后覆盖限定隧道窗的第一光致抗蚀剂掩模。然后蚀刻第一场氧化物层和高电压氧化物层。之后，剥去第一光致抗蚀剂掩模。生长隧道氧化物层。在隧道氧化物层的顶部生长多晶硅层，然后掺杂。限定浮动栅极的第二光致抗蚀剂掩模覆盖在多晶硅层的顶部上。然后蚀刻多晶硅层，剥离第二光致抗蚀剂掩模。

96. 发明授权

US06208557B1 EPROM and flash memory cells with source-side injection and a gate dielectric that traps hot electrons during programming 有权
公开(公告)号：US06208557B1
公开(公告)日：2001-03-27
申请号：US09316445
申请日：1999-05-21
申请人： Albert Bergemont , Alexander Kalnitsky
发明人： Albert Bergemont , Alexander Kalnitsky
IPC分类号： G11C1604
CPC分类号： G11C16/10 , G11C16/0408 , H01L29/4232 , H01L29/792
摘要： An electrically-programmable read-only-memory (EPROM) and a flash memory cell having source-side injection are formed with a gate dielectric material, and a pair of gates that are both formed on the gate dielectric material. The gate dielectric material has substantially more electron traps than hole traps so that the gate dielectric material is capable of having a negative potential which is sufficient to inhibit the formation of a conductive channel during a read operation.

97. 发明授权

US6146962A Method for forming a DRAM cell with a stacked capacitor 失效
标题翻译：用堆叠电容器形成DRAM单元的方法
公开(公告)号：US6146962A
公开(公告)日：2000-11-14
申请号：US40212
申请日：1998-03-17
申请人： Alexander Kalnitsky , Albert Bergemont
发明人： Alexander Kalnitsky , Albert Bergemont
IPC分类号： H01L21/02 , H01L21/20
CPC分类号： H01L28/87
摘要： A dynamic random-access-memory (DRAM) cell with a fin or wing-type stacked capacitor is fabricated by using a layer of polysilicon as an etch stop rather than the layer of nitride that is conventionally used. By using the layer of polysilicon, the problem of hydrogen-enhanced boron diffusion in dual work function CMOS transistors is eliminated while at the same time increasing the capacitance of the stacked capacitor without substantially increasing the step height of the capacitor.
摘要翻译：具有翅片或翼型叠层电容器的动态随机存取存储器（DRAM）单元通过使用多晶硅层作为蚀刻停止而不是常规使用的氮化物层来制造。通过使用多晶硅层，消除了双功函数CMOS晶体管中的氢增强硼扩散的问题，同时增加了层叠电容器的电容而基本上不增加电容器的台阶高度。

98. 发明授权

US6137722A Memory array having Frohmann-Bentchkowsky EPROM cells with a reduced number of access transistors 有权
标题翻译：具有减少数量的存取晶体管的Frohmann-Bentchkowsky EPROM单元的存储器阵列
公开(公告)号：US6137722A
公开(公告)日：2000-10-24
申请号：US301098
申请日：1999-04-28
申请人： Alexander Kalnitsky , Albert Bergemont
发明人： Alexander Kalnitsky , Albert Bergemont
IPC分类号： G11C11/56 , G11C16/04 , G11C16/10 , G11C16/26 , H01L27/115 , H01L29/788
CPC分类号： G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0408 , G11C16/0433 , G11C16/10 , G11C16/26 , H01L27/115 , H01L27/11519 , H01L29/7887 , G11C2216/10 , G11C7/06
摘要： A plurality of Frohmann-Bentchkowsky p-channel memory transistors which are arranged in rows and columns is disclosed. Each column of memory transistors has an associated output line. A row of n-channel MOS access transistors are connected to the output columns to select individual memory transistors in a row of memory transistors.
摘要翻译：公开了以行和列排列的多个Frohmann-Bentchkowsky p沟道存储晶体管。每列存储晶体管具有相关联的输出线。一排n沟道MOS存取晶体管连接到输出列，以选择一排存储晶体管中的各个存储晶体管。

99. 发明授权

US6136635A Method for forming a bipolar-based active pixel sensor cell with poly contact and increased capacitive coupling to the base region 失效
标题翻译：用于形成具有多点接触的双极性有源像素传感器单元和增加到基极区域的电容耦合的方法
公开(公告)号：US6136635A
公开(公告)日：2000-10-24
申请号：US89208
申请日：1998-06-02
申请人： Albert Bergemont , Min-Hwa Chi
发明人： Albert Bergemont , Min-Hwa Chi
IPC分类号： H01L21/8249 , H01L27/146 , H01L21/8238
CPC分类号： H01L21/8249 , H01L27/14609 , H01L27/14681
摘要： The dynamic range is increased and the noise level is reduced in a bipolar-based active pixel sensor cell with a capacitively coupled base region by forming the capacitor over a portion of the base region and the field oxide region of the cell. In addition, the noise levels are also reduced by heavily-doping the material which forms a portion of the bottom plate of the capacitor with the same conductivity type as the base region of the cell, and by placing the material which forms the portion of the bottom plate in direct contact with the base region.
摘要翻译：通过在电池的基极区域和场氧化物区域的一部分上形成电容器，动态范围增加，并且通过在具有电容耦合的基极区域的基于双极的有源像素传感器单元中降低噪声水平。此外，通过以与电池的基底区域相同的导电类型重叠掺杂形成电容器的底板的一部分的材料，并且通过将形成底板与基座区域直接接触。

100. 发明授权

US06080601A Method for forming a bipolar-based active pixel sensor cell with metal contact and increased capacitive coupling to the base region 失效
标题翻译：用于形成具有金属接触的双极性有源像素传感器单元和增加到基极区域的电容耦合的方法
公开(公告)号：US06080601A
公开(公告)日：2000-06-27
申请号：US115000
申请日：1998-07-14
申请人： Albert Bergemont , Min-hwa Chi
发明人： Albert Bergemont , Min-hwa Chi
IPC分类号： H01L27/146 , H01L27/082
CPC分类号： H01L27/14643 , H01L27/14681
摘要： The dynamic range is increased and the noise level is reduced in a bipolar-based active pixel sensor cell with a capacitively coupled base region by forming the capacitor over a portion of the base region and the field oxide region of the cell. In addition, the noise levels are also reduced by heavily-doping the material which forms a portion of the bottom plate of the capacitor with the same conductivity type as the base region of the cell, and by placing the material which forms the portion of the bottom plate in direct contact with the base region.
摘要翻译：通过在电池的基极区域和场氧化物区域的一部分上形成电容器，动态范围增加，并且通过在具有电容耦合的基极区域的基于双极的有源像素传感器单元中降低噪声水平。此外，通过以与电池的基底区域相同的导电类型重叠掺杂形成电容器的底板的一部分的材料，并且通过将形成底板与基座区域直接接触。

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