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1. 发明授权

US07078928B2 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US07078928B2
公开(公告)日：2006-07-18
申请号：US10736673
申请日：2003-12-17
申请人： Ryusuke Sahara , Kozaburo Kurita , Yuuji Suzuki , Mitsugu Kusunoki , Hideki Sakakibara
发明人： Ryusuke Sahara , Kozaburo Kurita , Yuuji Suzuki , Mitsugu Kusunoki , Hideki Sakakibara
IPC分类号： H03K19/00 , G01R31/28 , H03H11/26
CPC分类号： G01R31/318577
摘要： The present invention provides a semiconductor integrated circuit device equipped with at least one pulse generator which generates a pulse of a pulse with shorter than a rising time up to the full amplitude of a transfer signal.A first signal and a second signal supplied from outside through a first signal path and a second signal path are respectively transferred to the pulse generator. When a rising time up to the full amplitude at any one of buffers in the first signal path and the second signal path is longer than a pulse width of a pulse to be formed by the pulse generator, the difference in phase between the first signal and the second signal is caused to correspond to a pulse width of a first pulse.
摘要翻译：本发明提供一种配备有至少一个脉冲发生器的半导体集成电路器件，该脉冲发生器产生的脉冲脉冲短于传输信号的全幅度的上升时间。通过第一信号路径和第二信号路径从外部提供的第一信号和第二信号分别传送到脉冲发生器。当在第一信号路径和第二信号路径中的任何一个缓冲器上的上升时间达到全幅度时，脉冲发生器将形成的脉冲的脉冲宽度大于第一信号与第二信号路径之间的相位差使第二信号对应于第一脉冲的脉冲宽度。

2. 发明申请

US20110074385A1 SEMICONDUCTOR INTEGRATED CIRCUIT 审中-公开
标题翻译：半导体集成电路
公开(公告)号：US20110074385A1
公开(公告)日：2011-03-31
申请号：US12849807
申请日：2010-08-03
申请人： Yasuyoshi Sunaga , Hideki Sakakibara , Yuko Ito , Tomoji Nakamura , Atsushi Hazeyama , Kozaburo Kurita , Koki Tsutsumida
发明人： Yasuyoshi Sunaga , Hideki Sakakibara , Yuko Ito , Tomoji Nakamura , Atsushi Hazeyama , Kozaburo Kurita , Koki Tsutsumida
IPC分类号： G01R29/00 , G01F15/06
CPC分类号： G01R31/3016 , G01R19/0084 , G01R19/0092 , G01R21/00
摘要： There is provided a semiconductor integrated circuit in which a ring oscillator is formed by a variable delay circuit to cause the ring oscillator to oscillate (S2) at the test operation of the variable delay circuit and it is determined whether the variable delay circuit is normal or abnormal depending on whether the ring oscillator satisfies a predetermined monotonic increase condition (S6) and a predetermined linearity condition (S7).
摘要翻译：提供了一种半导体集成电路，其中环形振荡器由可变延迟电路形成，以在可变延迟电路的测试操作时使环形振荡器振荡（S2），并且确定可变延迟电路是正常的还是在取决于环形振荡器是否满足预定的单调增加条件（S6）和预定线性条件（S7）而异常。

3. 发明授权

US5506982A Data processing system generating clock signal from an input clock, phase locked to the input clock and used for clocking logic devices 失效
公开(公告)号：US5506982A
公开(公告)日：1996-04-09
申请号：US278245
申请日：1994-07-21
申请人： Takashi Hotta , Kozaburo Kurita , Masahiro Iwamura , Hideo Maejima , Shigeya Tanaka , Tadaaki Bandoh , Yasuhiro Nakatsuka , Kazuo Kato , Sin-ichi Sinoda
发明人： Takashi Hotta , Kozaburo Kurita , Masahiro Iwamura , Hideo Maejima , Shigeya Tanaka , Tadaaki Bandoh , Yasuhiro Nakatsuka , Kazuo Kato , Sin-ichi Sinoda
IPC分类号： G06F1/10 , H03K5/156 , H03L7/18 , G06F1/06
CPC分类号： H03K5/1565 , G06F1/10 , H03L7/18
摘要： An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K.sub.1 which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal K.sub.1, and the operation timing of an interface provided between at least one pair of logic devices is synchronously controlled by the clock signal K.sub.1.

4. 发明授权

US07777331B2 Semiconductor apparatus comprising a semiconductor chip with a power supply circuit and a smoothing circuit disposed outside the semiconductor chip 失效
标题翻译：半导体装置包括具有电源电路的半导体芯片和设置在半导体芯片外部的平滑电路
公开(公告)号：US07777331B2
公开(公告)日：2010-08-17
申请号：US11761764
申请日：2007-06-12
申请人： Kozaburo Kurita
发明人： Kozaburo Kurita
IPC分类号： G06F1/00 , H01L23/48
CPC分类号： H01L23/50 , H01L2924/0002 , H02J1/00 , H01L2924/00
摘要： A semiconductor apparatus including built-in power supply circuits capable of supplying a large current with high voltage accuracy. The semiconductor apparatus includes a semiconductor chip including a circuit area and power supply circuits, coils and capacitors. The semiconductor chip, coils and capacitors are provided in a package. Each power supply circuit, a coil and a capacitor compose a switching regulator. The semiconductor chip and the package are connected such that a power supply voltage which will be produced by the switching regulator is supplied to the circuit area. The power supply circuit is supplied with a power supply voltage from the outside of the semiconductor apparatus.
摘要翻译：一种具有能够以高电压精度提供大电流的内置电源电路的半导体装置。半导体装置包括具有电路区域和电源电路，线圈和电容器的半导体芯片。半导体芯片，线圈和电容器设置在封装中。每个电源电路，一个线圈和一个电容组成一个开关稳压器。连接半导体芯片和封装，使得由开关调节器产生的电源电压被提供给电路区域。电源电路从半导体装置的外部供给电源电压。

5. 发明授权

US06675311B2 Data processing system generating clock signal from an input clock, phase locked to the input clock and used for clocking logic devices 失效
标题翻译：数据处理系统从输入时钟产生时钟信号，锁相到输入时钟并用于时钟逻辑器件
公开(公告)号：US06675311B2
公开(公告)日：2004-01-06
申请号：US10002444
申请日：2001-12-06
申请人： Takashi Hotta , Kozaburo Kurita , Masahiro Iwamura , Hideo Maejima , Shigeya Tanaka , Tadaaki Bandoh , Yasuhiro Nakatsuka , Kazuo Kato , Sin-ichi Sinoda
发明人： Takashi Hotta , Kozaburo Kurita , Masahiro Iwamura , Hideo Maejima , Shigeya Tanaka , Tadaaki Bandoh , Yasuhiro Nakatsuka , Kazuo Kato , Sin-ichi Sinoda
IPC分类号： G06F104
CPC分类号： H03K5/1565 , G06F1/10 , H03L7/18
摘要： An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K1 which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal K1, And the operation timing of an interface provided between at least one pair oflogic devices is synchronously controlled by the clock signal K1.
摘要翻译：一种具有原始时钟振荡器的信息处理系统，用于传送被定义为第一时钟信号的至少一个原始时钟信号K和提供有原始时钟信号K的多个信息处理单元，其中每个信息处理单元包括时钟发生装置，用于产生至少一个第二时钟信号K1与原始时钟信号K锁相并具有预定的占空比，以及由第二时钟信号K1控制其操作定时的逻辑器件。至少一对逻辑设备由时钟信号K1同步控制。

6. 发明授权

US6163186A System including phase lock loop circuit 失效
标题翻译：系统包括锁相环电路
公开(公告)号：US6163186A
公开(公告)日：2000-12-19
申请号：US966786
申请日：1997-11-10
申请人： Kozaburo Kurita
发明人： Kozaburo Kurita
IPC分类号： G06F1/10 , H03K3/0231 , H03K3/354 , H03L7/07 , H03L7/089 , H03L7/099 , H03L7/10 , H03L7/18 , H03L7/06
CPC分类号： G06F1/10 , H03K3/0231 , H03K3/354 , H03L7/07 , H03L7/0891 , H03L7/0995 , H03L7/10 , H03L7/105 , H03L7/18 , Y10S331/02
摘要： A PLL circuit includes a phase comparator which makes a comparison between an internal clock signal and a clock signal supplied from an external terminal, a charge pump circuit which produces a charging-up or discharging current in accordance with the output of the phase comparator, so as to drive a filter capacitor, a voltage-controlled oscillator the oscillation frequency of which is controlled by the held voltage of the filter capacitor, and a frequency divider circuit which generates the internal clock signal on the basis of the oscillation output of the voltage-controlled oscillator. The PLL circuit is additionally provided with a voltage detector circuit which detects whether the held voltage of the filter capacitor has been raised to a predetermined voltage or higher, and the function of forcibly lowering the held voltage of the filter capacitor down to a predetermined potential in accordance with the detection output of the voltage detector circuit. Besides, a system is provided with a detection and setting circuit which detects a state brought about by the electrical disconnection of the feedback loop of the PLL circuit, and which brings the PLL circuit into a predetermined state.
摘要翻译： PLL电路包括相位比较器，用于比较内部时钟信号和从外部端子提供的时钟信号之间的比较，电荷泵电路根据相位比较器的输出产生充电或放电电流，因此为了驱动滤波电容器，其振荡频率由滤波电容器的保持电压控制的压控振荡器，以及基于电压互感器的振荡输出产生内部时钟信号的分频器电路，受控振荡器。 PLL电路另外设置有电压检测器电路，其检测滤波电容器的保持电压是否已经升高到预定电压或更高，并且将滤波电容器的保持电压强制降低到预定电位的功能按照检测电路的检测输出。此外，系统具有检测和设置电路，该检测和设置电路检测由PLL电路的反馈回路的电断开引起的状态，并且使PLL电路进入预定状态。

7. 发明授权

US4801983A Schottky diode formed on MOSFET drain 失效
标题翻译：在MOSFET漏极上形成肖特基二极管
公开(公告)号：US4801983A
公开(公告)日：1989-01-31
申请号：US899399
申请日：1986-08-22
申请人： Masahiro Ueno , Masahiro Iwamura , Kozaburo Kurita , Ikuro Masuda
发明人： Masahiro Ueno , Masahiro Iwamura , Kozaburo Kurita , Ikuro Masuda
IPC分类号： H03K19/0944 , H01L21/82 , H01L21/8249 , H01L27/06 , H01L27/07 , H03K17/687 , H03K17/693 , H03K19/094 , H03K19/0952 , H01L27/04 , G11C11/40
CPC分类号： H03K17/687 , H01L27/0727
摘要： A unidirectional switching circuit having no charge storage effect for performing a high-speed switching operation is disclosed in which one of the anode and cathode terminals of a Schottky-barrier diode is connected to one of the source and drain terminals of a field effect transistor to form the series combination of the Schottky-barrier diode and the field effect transistor, that one of end terminals of the series combination which exists on the anode side of the diode, is used as an input terminal, the other end terminal existing on the cathode side is used as an output terminal, the gate electrode of the field effect transistor is used as a switching control electrode, and a current flowing through the switching circuit in a direction from the input terminal to the output terminal is controlled in accordance with a signal applied to the switching control electrode.
摘要翻译：公开了一种不进行高速开关动作的电荷存储效应的单向开关电路，其中肖特基势垒二极管的阳极和阴极端子之一连接到场效应晶体管的源极和漏极端子之一，形成肖特基势垒二极管和场效应晶体管的串联组合，存在于二极管的阳极侧的串联组合的端子之一用作输入端子，另一端子存在于阴极侧用作输出端子，场效应晶体管的栅电极用作开关控制电极，并且根据信号控制沿着从输入端到输出端的方向流过开关电路的电流施加到开关控制电极。

8. 发明申请

US20090021227A1 POWER-SUPPLY DEVICE, IC CIRCUIT, AND INFORMATION PROCESSING APPARATUS, AND SOFT-START CONTROL METHOD 审中-公开
标题翻译：电源装置，IC电路和信息处理装置以及软启动控制方法
公开(公告)号：US20090021227A1
公开(公告)日：2009-01-22
申请号：US12019761
申请日：2008-01-25
申请人： Takashi Sase , Yosuke Kawakubo , Kozaburo Kurita
发明人： Takashi Sase , Yosuke Kawakubo , Kozaburo Kurita
IPC分类号： G05F1/44 , G05F1/00
CPC分类号： H02M1/36 , H02M3/156 , H02M2001/0009
摘要： An electric current flowing to an upper side power MOSFET during soft-start is detected according to an on-voltage of the MOSFET and an on-pulse width of a PWM pulse for driving the upper side power MOSFET is forced to be reset in the idle and decided according to a signal generated when the voltage falls below a predetermined specified voltage.
摘要翻译：根据MOSFET的导通电压检测软启动期间流向上侧功率MOSFET的电流，驱动上侧功率MOSFET的PWM脉冲的导通脉冲宽度被迫在空闲状态下复位并根据当电压低于预定的规定电压时产生的信号来决定。

9. 发明授权

US06735129B2 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US06735129B2
公开(公告)日：2004-05-11
申请号：US10153525
申请日：2002-05-24
申请人： Hiroshi Akasaki , Shuichi Miyaoka , Yuji Yokoyama , Masatoshi Hasegawa , Kozaburo Kurita
发明人： Hiroshi Akasaki , Shuichi Miyaoka , Yuji Yokoyama , Masatoshi Hasegawa , Kozaburo Kurita
IPC分类号： G11C700
CPC分类号： G11C7/1066 , G11C7/1006 , G11C7/1039 , G11C7/1072 , G11C2207/104
摘要： In a semiconductor integrated circuit device that includes macro cells (circuit blocks that can be designed independently) such as a storage circuit and operates synchronously with an external clock, total delay time from signal input to output is reduced and the speed of operation is increased. In the semiconductor integrated circuit device which has plural circuit blocks coupled in series for signal transmission and whose whole operation is controlled by a clock signal, the semiconductor integrated circuit device including first circuit blocks that receive input signals in response to a first timing signal based on a clock signal, and a second circuit block that forms output signals in response to a second timing signal based on the clock signal, a time difference between the first timing signal and the second timing signal is set to a non-integral multiple of the cycle of the clock signal.
摘要翻译：在包括诸如存储电路的宏单元（可独立设计的电路块）并且与外部时钟同步地操作的半导体集成电路器件中，从信号输入到输出的总延迟时间减少，并且操作速度增加。在具有串联耦合用于信号传输并且其整个操作由时钟信号控制的多个电路块的半导体集成电路器件中，半导体集成电路器件包括响应于基于第一定时信号接收输入信号的第一电路块时钟信号和响应于基于时钟信号的第二定时信号形成输出信号的第二电路块，第一定时信号和第二定时信号之间的时间差被设置为该周期的非整数倍的时钟信号。

10. 发明授权

US5666072A Semiconductor integrated circuit device having bipolar transistor and field effect transistor 失效
标题翻译：具有双极晶体管和场效应晶体管的半导体集成电路器件
公开(公告)号：US5666072A
公开(公告)日：1997-09-09
申请号：US223527
申请日：1994-04-05
申请人： Fumio Murabayashi , Yoji Nishio , Shoichi Kotoku , Kozaburo Kurita , Kazuo Kato
发明人： Fumio Murabayashi , Yoji Nishio , Shoichi Kotoku , Kozaburo Kurita , Kazuo Kato
IPC分类号： H01L29/73 , H01L21/331 , H01L21/82 , H01L27/06 , H01L27/118 , H01L29/732 , H03K17/04 , H03K17/16 , H03K17/567 , H03K19/00 , H03K19/003 , H03K19/08 , H03K19/0944 , H03K19/01
CPC分类号： H01L27/0623 , H03K19/001 , H03K19/00353 , H03K19/09448
摘要： A semiconductor integrated circuit device having a plurality of logic circuits integrated on a semiconductor substrate is provided which can operate with a power source potential difference substantially less than 5 V. The logic circuit includes a bipolar transistor having a base and its collector-emitter current path coupled between a first power source terminal and an output terminal, together with at least one field effect transistor having its gate responsive to an input signal applied to an input terminal and its source-drain current path coupled between the first power source terminal and the base of the bipolar transistor. A semiconductor switch means is also provided which is responsive to the input signal applied to the input terminal for performing ON/OFF operations complementary to the ON/OFF operations of the bipolar transistor and which has a current path between its paired main terminals coupled between the output terminal and the second power source terminal. In order to improve the operating speed, a potential difference reducing element is provided having a current path between its paired main terminals coupled between the first power source terminal and the output terminal for reducing the potential difference, which is present between the first power source terminal and the output terminal based on the base-emitter forward voltage of the bipolar transistor when the bipolar transistor is ON.
摘要翻译：提供了具有集成在半导体衬底上的多个逻辑电路的半导体集成电路器件，其可以以基本上小于5V的电源电位差工作。逻辑电路包括具有基极和其集电极 - 发射极电流路径的双极晶体管耦合在第一电源端子和输出端子之间，以及至少一个具有栅极的场效应晶体管，其响应于施加到输入端子的输入信号及其耦合在第一电源端子和基极之间的源极 - 漏极电流路径的双极晶体管。还提供一种半导体开关装置，其响应于施加到输入端子的输入信号，用于执行与双极晶体管的导通/截止操作互补的ON / OFF操作，并且在其双绞主端子之间具有电流通路输出端子和第二电源端子。为了提高工作速度，提供了一个电位差降低元件，其具有耦合在第一电源端子和输出端子之间的成对主端子之间的电流路径，用于减小电位差，该电位差存在于第一电源端子以及当双极晶体管导通时基于双极晶体管的基极 - 发射极正向电压的输出端子。

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