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1. 发明授权

US07885820B1 Expert system supported interactive product selection and recommendation 有权
标题翻译：专家系统支持交互式产品选择和推荐
公开(公告)号：US07885820B1
公开(公告)日：2011-02-08
申请号：US09909250
申请日：2001-07-19
申请人： Rod Mancisidor , Charles R. Erickson , Ahmed Gheith , William W. Chan
发明人： Rod Mancisidor , Charles R. Erickson , Ahmed Gheith , William W. Chan
IPC分类号： G06Q90/00
CPC分类号： G06N5/04 , G06Q10/10 , G06Q30/02
摘要： Expert system supported interactive product selection and recommendation. The invention assists an agent to interact with a customer and to provide selection and recommendation of available products and/or services that offer a workable solution for the customer. The invention allows for the use of agents of varying skill levels, including relatively low skill level, without suffering deleterious performance. From certain perspectives, an expert system employed using various aspects of the invention allows the agent to provide real time interaction with a customer and to provide a real time recommended solution to that customer. Many traditional approaches dealing in complex industries require that agent's have a high degree of skill and expertise. The invention allows even a novice agent to service a customer's needs without requiring a high skill level or up-front training that is often at the expense of the provider seeking to market its products and/or services.
摘要翻译：专家系统支持交互式产品选择和推荐。本发明帮助代理人与客户进行交互，并提供为客户提供可行解决方案的可用产品和/或服务的选择和推荐。本发明允许使用具有不同技能水平的试剂，包括技能水平较低，而不会产生有害的性能。从某些角度来看，使用本发明的各个方面的专家系统允许代理人提供与客户的实时交互并为该客户提供实时推荐的解决方案。处理复杂行业的许多传统方法要求代理人具有高度的技能和专业知识。本发明甚至允许新手代理服务于客户的需求，而不需要高技能水平或前期训练，这往往是以寻求上市的产品和/或服务为代价的牺牲品。

2. 发明授权

US07031951B2 Expert system adapted dedicated internet access guidance engine 有权
公开(公告)号：US07031951B2
公开(公告)日：2006-04-18
申请号：US09909241
申请日：2001-07-19
申请人： Rod Mancisidor , Charles R. Erickson , Gordon Gilpin
发明人： Rod Mancisidor , Charles R. Erickson , Gordon Gilpin
IPC分类号： G06F17/00
CPC分类号： H04L41/16 , H04L41/00 , H04L41/145
摘要： An expert system adapted dedicated Internet access guidance engine. The invention allows an agent to interact with a customer and to provide selection and recommendation of data network products and/or services for the customer. The invention allows for the use of agents of varying skill levels, including relatively low skill level, without suffering deleterious performance. The dedicated Internet access guidance engine is operable to perform selection and rating of Internet access products and/or services to provide a solution that meets the needs of a customer. The dedicated Internet access guidance engine is operable to select recommended solutions from among a number of potential solutions that may include compatible solutions. The dedicated Internet access guidance engine is one of the underlying engines within the expert system that allows the agent to provide real time interaction with a customer and to provide a real time recommended solution to that customer.

3. 发明授权

US06212639B1 Encryption of configuration stream 有权
标题翻译：加密配置流
公开(公告)号：US06212639B1
公开(公告)日：2001-04-03
申请号：US09342336
申请日：1999-06-29
申请人： Charles R. Erickson , Danesh Tavana , Victor A. Holen
发明人： Charles R. Erickson , Danesh Tavana , Victor A. Holen
IPC分类号： H04K100
CPC分类号： G06F21/57 , G06F12/1408 , G06F21/85
摘要： A method of communicating encrypted configuration data between a programmable logic device (PLD) and a storage device is included in one part of the invention. The method includes the following steps. Transmit encrypted configuration data stored in a storage device to the PLD. Decrypt the encrypted configuration data to generate a copy of the configuration data in the PLD. Configure the PLD using the copy of the configuration data. In one embodiment, the PLD transmits a key to the storage device. In another embodiment the key is separately entered into the storage device and the PLD and never transmitted between the PLD and the storage device. In another embodiment, the key is entered only into the PLD. The key is used to encrypt the configuration data.
摘要翻译：在可编程逻辑器件（PLD）和存储器件之间传送加密配置数据的方法包括在本发明的一部分中。该方法包括以下步骤。将存储在存储设备中的加密配置数据发送到PLD。解密加密的配置数据以生成PLD中的配置数据的副本。使用配置数据的副本配置PLD。在一个实施例中，PLD将密钥发送到存储设备。在另一个实施例中，密钥分别输入到存储设备和PLD中，并且从未在PLD和存储设备之间传送密钥。在另一个实施例中，键仅输入到PLD中。密钥用于加密配置数据。

4. 发明授权

US5990704A Internal drive circuit providing third input pin state 失效
标题翻译：内部驱动电路提供第三输入引脚状态
公开(公告)号：US5990704A
公开(公告)日：1999-11-23
申请号：US942858
申请日：1997-10-02
申请人： Charles R. Erickson , Brian D. Erickson
发明人： Charles R. Erickson , Brian D. Erickson
IPC分类号： H03K19/0175 , H03K19/20
CPC分类号： H03K19/0002 , H03K19/173
摘要： A multi-state input drive structure is provided to forward externally generated high and low input signals, as well as to receive at least a third, internally generated, comparatively weak signal, preferably an oscillating signal, which triggers a third internally forwarded signal when neither of the high and low input signals is received. The inventive circuit drives three internally forwarded output signals from a single external signal source. Since this circuit may be duplicated for every pin on a device for which two cycle delays do not affect performance, availability of a third input state on N inputs allows 3.sup.N input codes as opposed to 2.sup.N for the conventional "high" and "low" levels normally available.
摘要翻译：提供多状态输入驱动结构以转发外部产生的高和低输入信号，以及接收至少第三，内部产生的相对较弱的信号，优选振荡信号，其触发第三内部转发信号，当两者接收高低输入信号。本发明的电路驱动来自单个外部信号源的三个内部转发的输出信号。由于对于两个周期延迟不影响性能的设备上的每个引脚可能会复制此电路，所以N个输入上的第三个输入状态的可用性允许3N输入代码，而不是常规的“高”和“低”电平的2N 通常可用。

5. 发明授权

US5923614A Structure and method for reading blocks of data from selectable points in a memory device 失效
标题翻译：用于从存储器件中的可选点读取数据块的结构和方法
公开(公告)号：US5923614A
公开(公告)日：1999-07-13
申请号：US71144
申请日：1998-04-30
申请人： Charles R. Erickson , Robert O. Conn , Lois D. Cartier
发明人： Charles R. Erickson , Robert O. Conn , Lois D. Cartier
IPC分类号： G11C8/04 , H03K19/177 , G11C8/00 , G06F7/38
CPC分类号： H03K19/17772 , G11C8/04 , H03K19/1776
摘要： A self-addressing memory device is provided that can provide blocks of data starting from more than one initial location in the device, and may have the option of reading in either direction. This memory device can efficiently store multiple bitstreams, which may be of different sizes, that are used to configure one or more configurable logic devices. Each stored bitstream can be accessed in any order. In one embodiment, the configurable logic device is a Field Programmable Gate Array ("FPGA"). In one embodiment, the memory device is a Read-Only Memory ("ROM") that is either read up from all zeros or down from all ones. In one embodiment, the ROM includes a bidirectional chip enable chain that permits cascading multiple ROMs.
摘要翻译：提供了自寻址存储器件，其可以从设备中的多于一个初始位置开始提供数据块，并且可以具有在任一方向上读取的选项。该存储设备可以有效地存储用于配置一个或多个可配置逻辑设备的多个可能具有不同大小的比特流。可以以任何顺序访问每个存储的比特流。在一个实施例中，可配置逻辑器件是现场可编程门阵列（“FPGA”）。在一个实施例中，存储器件是从全零读取或从全部读取的只读存储器（“ROM”）。在一个实施例中，ROM包括允许级联多个ROM的双向芯片使能链。

6. 发明授权

US5592105A Configuration logic to eliminate signal contention during reconfiguration 失效
标题翻译：在配置过程中消除信号争用的配置逻辑
公开(公告)号：US5592105A
公开(公告)日：1997-01-07
申请号：US375763
申请日：1995-01-20
申请人： Edmond Y. Cheung , Charles R. Erickson
发明人： Edmond Y. Cheung , Charles R. Erickson
IPC分类号： G06F17/50 , H03K19/173 , H03K19/177 , G11C19/00 , G11C19/28
CPC分类号： G06F17/5054 , H03K19/1737 , H03K19/17748 , H03K19/1776 , H03K19/17772
摘要： A method of eliminating signal contention during reconfiguration of a programmable logic device includes the steps of: arranging a plurality of memory cells in sets and selectively programing the memory cells one set at a time, either in a first direction or a second direction. A structure for providing that selective programming includes a plurality of synchronous flip-flops, and a plurality of associated two-input multiplexers. A control signal in a first logic state provided to the multiplexers provides a first signal propagation direction through the flip-flops, whereas the control signal in a second logic state provides a second signal propagation direction through the flip-flops.
摘要翻译：一种在可编程逻辑器件的重新配置期间消除信号争用的方法包括以下步骤：将多个存储器单元布置成集合并且选择性地对存储单元进行编程，所述存储器单元在一个时间上在第一方向或第二方向上编程。用于提供选择性编程的结构包括多个同步触发器和多个相关联的双输入多路复用器。提供给多路复用器的第一逻辑状态的控制信号提供通过触发器的第一信号传播方向，而处于第二逻辑状态的控制信号通过触发器提供第二信号传播方向。

7. 发明授权

US5581199A Interconnect architecture for field programmable gate array using variable length conductors 失效
标题翻译：使用可变长度导体的现场可编程门阵列的互连架构
公开(公告)号：US5581199A
公开(公告)日：1996-12-03
申请号：US368692
申请日：1995-01-04
申请人： Kerry M. Pierce , Charles R. Erickson , Chih-Tsung Huang , Douglas P. Wieland
发明人： Kerry M. Pierce , Charles R. Erickson , Chih-Tsung Huang , Douglas P. Wieland
IPC分类号： H01L21/82 , H03K19/173 , H03K19/177
CPC分类号： H03K19/17736 , H03K19/1737 , H03K19/17728
摘要： An FPGA architecture is provided which uses logic unit output lines of more than one length and provides extension lines to increase the reach of a logic unit output line. The architecture allows extremely fast connections between one logic unit and another. Also, all logic unit output lines drive about the same number of buffered programmable interconnection points (PIPs) so that the signal delay between one logic unit and the next can be predicted regardless of the functions and routing which have been selected by a user. The frequency of PIPs decreases as distance from the originating logic unit increases. This has the benefit of cooperating with software which tends to place interconnected logic in close proximity. The architecture is preferably implemented with a tile layout with one logic unit in each tile, and logic unit input and output lines extending through several tiles. Thus one tile boundary is like another and there is minimum hierarchy.
摘要翻译：提供了FPGA架构，其使用多于一个长度的逻辑单元输出线，并提供扩展线以增加逻辑单元输出线的覆盖范围。该架构允许一个逻辑单元与另一个逻辑单元之间的极快连接。而且，所有逻辑单元输出线驱动大约相同数量的缓冲可编程互连点（PIP），使得可以预测一个逻辑单元与下一个逻辑单元之间的信号延迟，而不管用户选择的功能和路由。 PIP的频率随着与起始逻辑单元的距离增加而减小。这有利于与易于将互联的逻辑紧邻的软件配合。该架构优选地实现为具有在每个瓦片中具有一个逻辑单元的瓦片布局，以及延伸穿过若干瓦片的逻辑单元输入和输出线。因此，一个瓦片边界与另一个瓦片边界相似，并且具有最小层次。

8. 发明授权

US4106090A Monolithic microcomputer central processor 失效
标题翻译：单片微机中央处理器
公开(公告)号：US4106090A
公开(公告)日：1978-08-08
申请号：US760063
申请日：1977-01-17
申请人： Charles R. Erickson , Hemraj K. Hingarh , Robert Moeckel , Dan Wilnai
发明人： Charles R. Erickson , Hemraj K. Hingarh , Robert Moeckel , Dan Wilnai
IPC分类号： G06F9/38 , G06F15/78 , G06F7/48
CPC分类号： G06F15/7864
摘要： A central processing unit (CPU) is utilized in combination with external memories and input/output devices to form a Microcomputer System. The CPU is a 16-bit fixed word length processor monolithically integrated onto a single semiconductor chip which uses two's complement arithmetic for computations. The CPU includes an arithmetic logic unit (ALU), accumulators, data path multiplexers, program counter means, and programmable logic arrays to control operation of the processor.The processor of this invention is capable of using a homogeneous memory, wherein instructions and data are both stored in the same memory. In the disclosed embodiment, 15 of the 16-bits are used for addressing the memory. Thus, the processor is capable of directly addressing 32,768 16-bit words in the memory.An external 16-bit bus is used to interconnect the external memory and input/output devices with the CPU. Bidirectional three-state logic is used to enable both input and output data, as well as memory addresses, to be transmitted over the same bus thereby simplifying design. In addition, provision is made for coupling an operator console into a system formed around the processor of this invention, thus allowing for a user to interface with the system.
摘要翻译：中央处理单元（CPU）与外部存储器和输入/输出设备结合使用以形成微计算机系统。 CPU是一个16位固定字长处理器，单片集成到单个半导体芯片上，采用二进制补码运算进行计算。 CPU包括算术逻辑单元（ALU），累加器，数据路径多路复用器，程序计数器装置和可编程逻辑阵列，以控制处理器的操作。

9. 发明授权

US5815016A Phase-locked delay loop for clock correction 失效
标题翻译：用于时钟校正的锁相延迟环
公开(公告)号：US5815016A
公开(公告)日：1998-09-29
申请号：US665169
申请日：1996-06-14
申请人： Charles R. Erickson
发明人： Charles R. Erickson
IPC分类号： G06F1/10 , H03L7/081 , H03L7/085 , H03L7/00 , H03K5/00
CPC分类号： G06F1/10 , H03L7/0812 , H03L7/085
摘要： A controlled delay path inserts a selected delay into a clock distribution circuit to create a total clock delay that is equal to an integer number of clock cycles relative to a reference dock signal or which produces a selected phase relationship to the reference dock signal. The delay path correction of the invention is particularly useful in circuits having a wide range of possible system clock frequencies or having programmable routing of clock signals, and therefore a wide range of operating delays. A reference clock signal is directed to a range of selectable voltage controlled delay elements by a phase detector that receives the reference clock signal and a feedback signal, and that produces an error voltage which adjusts the voltage controlled delay elements to produce an output clock signal. Additional selectable delays may be included that create offset options and allow selection of a leading, lagging, or in-phase reference dock/output clock relationship. In one embodiment both the positive and negative edges of a clock signal are corrected. As another feature, if correction is consistently in the same direction an error flag is generated.
摘要翻译：受控的延迟路径将选定的延迟插入到时钟分配电路中，以创建等于相对于参考停靠信号的整数个时钟周期的总时钟延迟，或者产生与参考停靠信号的选择的相位关系。本发明的延迟路径校正在具有宽范围的可能的系统时钟频率或具有时钟信号的可编程路由以及因此具有宽范围的操作延迟的电路中特别有用。参考时钟信号通过接收参考时钟信号和反馈信号的相位检测器被引导到可选择的受电压控制的延迟元件的范围，并产生一个误差电压，该误差电压调节电压控制的延迟元件以产生输出时钟信号。可以包括额外的可选择的延迟，其创建偏移选项并且允许选择引导，滞后或同相参考停靠/输出时钟关系。在一个实施例中，时钟信号的正和负边缘都被校正。作为另一个特征，如果校正始终在相同的方向上，则产生错误标志。

10. 发明授权

US5789938A Structure and method for reading blocks of data from selectable points in a memory device 失效
公开(公告)号：US5789938A
公开(公告)日：1998-08-04
申请号：US707545
申请日：1996-09-04
申请人： Charles R. Erickson , Robert O. Conn , Lois D. Cartier
发明人： Charles R. Erickson , Robert O. Conn , Lois D. Cartier
IPC分类号： G11C8/04 , H03K19/177 , H03K7/38
CPC分类号： H03K19/17772 , G11C8/04 , H03K19/1776
摘要： A self-addressing memory device is provided that can provide blocks of data starting from more than one initial location in the device, and may have the option of reading in either direction. This memory device can efficiently store multiple bitstreams, which may be of different sizes, that are used to configure one or more configurable logic devices. Each stored bitstream can be accessed in any order. In one embodiment, the configurable logic device is a Field Programmable Gate Array ("FPGA"). In one embodiment, the memory device is a Read-Only Memory ("ROM") that is either read up from all zeros or down from all ones. In one embodiment, the ROM includes a bidirectional chip enable chain that permits cascading multiple ROMs.

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