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1. 发明授权

US5581199A Interconnect architecture for field programmable gate array using variable length conductors 失效
标题翻译：使用可变长度导体的现场可编程门阵列的互连架构
公开(公告)号：US5581199A
公开(公告)日：1996-12-03
申请号：US368692
申请日：1995-01-04
申请人： Kerry M. Pierce , Charles R. Erickson , Chih-Tsung Huang , Douglas P. Wieland
发明人： Kerry M. Pierce , Charles R. Erickson , Chih-Tsung Huang , Douglas P. Wieland
IPC分类号： H01L21/82 , H03K19/173 , H03K19/177
CPC分类号： H03K19/17736 , H03K19/1737 , H03K19/17728
摘要： An FPGA architecture is provided which uses logic unit output lines of more than one length and provides extension lines to increase the reach of a logic unit output line. The architecture allows extremely fast connections between one logic unit and another. Also, all logic unit output lines drive about the same number of buffered programmable interconnection points (PIPs) so that the signal delay between one logic unit and the next can be predicted regardless of the functions and routing which have been selected by a user. The frequency of PIPs decreases as distance from the originating logic unit increases. This has the benefit of cooperating with software which tends to place interconnected logic in close proximity. The architecture is preferably implemented with a tile layout with one logic unit in each tile, and logic unit input and output lines extending through several tiles. Thus one tile boundary is like another and there is minimum hierarchy.
摘要翻译：提供了FPGA架构，其使用多于一个长度的逻辑单元输出线，并提供扩展线以增加逻辑单元输出线的覆盖范围。该架构允许一个逻辑单元与另一个逻辑单元之间的极快连接。而且，所有逻辑单元输出线驱动大约相同数量的缓冲可编程互连点（PIP），使得可以预测一个逻辑单元与下一个逻辑单元之间的信号延迟，而不管用户选择的功能和路由。 PIP的频率随着与起始逻辑单元的距离增加而减小。这有利于与易于将互联的逻辑紧邻的软件配合。该架构优选地实现为具有在每个瓦片中具有一个逻辑单元的瓦片布局，以及延伸穿过若干瓦片的逻辑单元输入和输出线。因此，一个瓦片边界与另一个瓦片边界相似，并且具有最小层次。

2. 发明授权

US5801546A Interconnect architecture for field programmable gate array using variable length conductors 失效
公开(公告)号：US5801546A
公开(公告)日：1998-09-01
申请号：US667571
申请日：1996-06-21
申请人： Kerry M. Pierce , Charles R. Erickson , Chih-Tsung Huang , Douglas P. Wieland
发明人： Kerry M. Pierce , Charles R. Erickson , Chih-Tsung Huang , Douglas P. Wieland
IPC分类号： H01L21/82 , H03K19/173 , H03K19/177 , H03K7/38
CPC分类号： H03K19/17736 , H03K19/1737 , H03K19/17728
摘要： An FPGA architecture is provided which uses logic unit output lines of more than one length and provides extension lines to increase the reach of a logic unit output line. The architecture allows extremely fast connections between one logic unit and another. Also, all logic unit output lines drive about the same number of buffered programmable interconnection points (PIPs) so that the signal delay between one logic unit and the next can be predicted regardless of the functions and routing which have been selected by a user. The frequency of PIPs decreases as distance from the originating logic unit increases. This has the benefit of cooperating with software which tends to place interconnected logic in close proximity. The architecture is preferably implemented with a tile layout with one logic unit in each tile, and logic unit input and output lines extending through several tiles. Thus one tile boundary is like another and there is minimum hierarchy.

3. 发明授权

US5760604A Interconnect architecture for field programmable gate array 失效
标题翻译：现场可编程门阵列的互连架构
公开(公告)号：US5760604A
公开(公告)日：1998-06-02
申请号：US656752
申请日：1996-06-03
申请人： Kerry M. Pierce , Charles R. Erickson , Chih-Tsung Huang , Douglas P. Wieland
发明人： Kerry M. Pierce , Charles R. Erickson , Chih-Tsung Huang , Douglas P. Wieland
IPC分类号： H01L21/82 , H03K19/173 , H03K19/177 , H03K7/38
CPC分类号： H03K19/17736 , H03K19/1737 , H03K19/17728
摘要： An FPGA architecture is provided which uses logic unit output lines of more than one length and provides extension lines to increase the reach of a logic unit output line. The architecture allows extremely fast connections between one logic unit and another. Also, all logic unit output lines drive about the same number of buffered programmable interconnection points (PIPs) so that the signal delay between one logic unit and the next can be predicted regardless of the functions and routing which have been selected by a user. The frequency of PIPs decreases as distance from the originating logic unit increases. This has the benefit of cooperating with software which tends to place interconnected logic in close proximity. The architecture is preferably implemented with a tile layout with one logic unit in each tile, and logic unit input and output lines extending through several tiles. Thus one tile boundary is like another and there is minimum hierarchy.
摘要翻译：提供了FPGA架构，其使用多于一个长度的逻辑单元输出线，并提供扩展线以增加逻辑单元输出线的覆盖范围。该架构允许一个逻辑单元与另一个逻辑单元之间的极快连接。而且，所有逻辑单元输出线驱动大约相同数量的缓冲可编程互连点（PIP），使得可以预测一个逻辑单元与下一个逻辑单元之间的信号延迟，而不管用户选择的功能和路由。 PIP的频率随着与起始逻辑单元的距离增加而减小。这有利于与易于将互联的逻辑紧邻的软件配合。该架构优选地实现为具有在每个瓦片中具有一个逻辑单元的瓦片布局，以及延伸穿过若干瓦片的逻辑单元输入和输出线。因此，一个瓦片边界与另一个瓦片边界相似，并且具有最小层次。

4. 发明申请

US20140032591A1 SYSTEM AND METHOD FOR IMPROVING HARDWARE UTILIZATION FOR A BIDIRECTIONAL ACCESS CONTROL LIST IN A LOW LATENCY HIGH-THROUGHPUT NETWORK 有权
标题翻译：用于改善低延迟高通量网络中双向访问控制列表的硬件利用的系统和方法
公开(公告)号：US20140032591A1
公开(公告)日：2014-01-30
申请号：US13560154
申请日：2012-07-27
申请人： Mingzhe Li , Alessandro Fulli , Putu Harry Subagio , Chih-Tsung Huang
发明人： Mingzhe Li , Alessandro Fulli , Putu Harry Subagio , Chih-Tsung Huang
IPC分类号： G06F17/30
CPC分类号： H04L63/101 , G06F17/30595 , H04L63/0236
摘要： A method in an example embodiment includes creating a first search key from variable data of a message received in a network environment, creating a second search key from constant data of the message, identifying a first database entry in a first database based on the first search key, and identifying a second database entry in a second database based on the second search key. The method can also include performing an action associated with the first database entry when a correlation is identified between the first and second database entries. In specific embodiments, the variable data are modified and the constant data are not modified. The first search key can be created prior or subsequent to forwarding the message. In further embodiments, the correlation is identified when an offset of the first database entry is the same as an offset of the second database entry.
摘要翻译：示例实施例中的方法包括从在网络环境中接收的消息的可变数据创建第一搜索关键字，从所述消息的常数数据创建第二搜索关键字，基于所述第一搜索来识别第一数据库中的第一数据库条目密钥，以及基于第二搜索关键字识别第二数据库中的第二数据库条目。该方法还可以包括当在第一和第二数据库条目之间识别相关性时执行与第一数据库条目相关联的动作。在具体实施例中，修改变量数据并且不修改常量数据。可以在转发消息之前或之后创建第一个搜索关键字。在另外的实施例中，当第一数据库条目的偏移量与第二数据库条目的偏移量相同时，识别相关性。

5. 发明申请

US20120054437A1 INCREASING DATA ACCESS PERFORMANCE 有权
标题翻译：提高数据访问性能
公开(公告)号：US20120054437A1
公开(公告)日：2012-03-01
申请号：US12870596
申请日：2010-08-27
申请人： WEI-JEN HUANG , Chih-Tsung Huang , Sachin Agarwal , Sha Ma
发明人： WEI-JEN HUANG , Chih-Tsung Huang , Sachin Agarwal , Sha Ma
IPC分类号： G06F12/02 , G06F12/08
CPC分类号： G06F3/0613 , G06F3/064 , G06F3/0656 , G06F3/0659 , G06F3/0674 , G06F3/0679 , G06F11/108 , G06F12/06 , G06F12/0864 , G06F13/1642 , G06F13/1673 , H04L45/60 , H04L45/745
摘要： Techniques are described for increasing data access performance for a memory device. In various embodiments, a scheduler/controller is configured to manage data as it read to or written from a memory. Read access is increased by partitioning a memory into a group of sub-blocks, associating a parity block with the sub-blocks, and accessing the sub-blocks to read data as needed. Write speeds may be improved by adding a pending write buffer to a group of memory sub-blocks. Such a buffer may be sized to be equal to the group of memory sub-blocks. The pending write buffer is used to handle collisions for write accesses to the same block, allowing two simultaneous writes to any regular memory block to occur. Additionally, a set-associative memory block may be used to improve write speed.
摘要翻译：描述了用于增加存储器设备的数据访问性能的技术。在各种实施例中，调度器/控制器被配置为在从存储器读取或从存储器写入时管理数据。通过将存储器分割成一组子块，将奇偶校验块与子块相关联，以及根据需要访问子块以读取数据来增加读取访问。通过将一个待处理的写入缓冲区添加到一组存储器子块可以改善写入速度。这样的缓冲器的大小可以等于存储器子块组。待处理写缓冲区用于处理对同一块的写入访问的冲突，允许发生任何常规内存块的两次同时写入。另外，可以使用集合关联存储器块来提高写入速度。

6. 发明授权

US08107499B2 Speed negotiation for multi-speed communication devices 有权
标题翻译：多速通信设备的速度协商
公开(公告)号：US08107499B2
公开(公告)日：2012-01-31
申请号：US11821251
申请日：2007-06-21
申请人： Wei-Jen Huang , Chih-Tsung Huang , Claudio DeSanti
发明人： Wei-Jen Huang , Chih-Tsung Huang , Claudio DeSanti
IPC分类号： H04L3/06
CPC分类号： H04L5/1438
摘要： A method includes defining a pattern of time intervals, each time interval having a respective assigned communication speed, which alternates among multiple communication speeds supported by a first communication device. Synchronization requests are transmitted over a communication medium from the first communication device to a second communication device at the respective communication speed that is assigned in each interval in accordance with the pattern. While transmitting the synchronization requests, synchronization replies sent over the communication medium in response to the synchronization requests are received only at the respective communication speed that is assigned in each interval. Responsively to receiving the synchronization replies from the second communication device, one or more common communication speeds that are supported by both the first and the second communication devices are identified. Communication is established between the first and second communication devices over the communication medium using one of the common communication speeds.
摘要翻译：一种方法包括定义时间间隔的模式，每个时间间隔具有各自分配的通信速度，其在由第一通信设备支持的多个通信速度之间交替。同步请求通过通信介质从第一通信设备以按照该模式在每个间隔中分配的相应通信速度被发送到第二通信设备。在发送同步请求的同时，响应于同步请求通过通信介质发送的同步回复仅在每个间隔中分配的相应通信速度下被接收。响应于从第二通信设备接收同步响应，识别由第一和第二通信设备支持的一个或多个通用通信速度。使用公共通信速度之一，通过通信介质在第一和第二通信设备之间建立通信。

7. 发明申请

US20080317069A1 Speed negotiation for multi-speed communication devices 有权
标题翻译：多速通信设备的速度协商
公开(公告)号：US20080317069A1
公开(公告)日：2008-12-25
申请号：US11821251
申请日：2007-06-21
申请人： Wei-Jen Huang , Chih-Tsung Huang , Claudio DeSanti
发明人： Wei-Jen Huang , Chih-Tsung Huang , Claudio DeSanti
IPC分类号： H04J3/06
CPC分类号： H04L5/1438
摘要： A method includes defining a pattern of time intervals, each time interval having a respective assigned communication speed, which alternates among multiple communication speeds supported by a first communication device. Synchronization requests are transmitted over a communication medium from the first communication device to a second communication device at the respective communication speed that is assigned in each interval in accordance with the pattern. While transmitting the synchronization requests, synchronization replies sent over the communication medium in response to the synchronization requests are received only at the respective communication speed that is assigned in each interval. Responsively to receiving the synchronization replies from the second communication device, one or more common communication speeds that are supported by both the first and the second communication devices are identified. Communication is established between the first and second communication devices over the communication medium using one of the common communication speeds.
摘要翻译：一种方法包括定义时间间隔的模式，每个时间间隔具有各自分配的通信速度，其在由第一通信设备支持的多个通信速度之间交替。同步请求通过通信介质从第一通信设备以按照该模式在每个间隔中分配的相应通信速度被发送到第二通信设备。在发送同步请求的同时，响应于同步请求通过通信介质发送的同步回复仅在每个间隔中分配的相应通信速度下被接收。响应于从第二通信设备接收同步响应，识别由第一和第二通信设备支持的一个或多个通用通信速度。使用公共通信速度之一，通过通信介质在第一和第二通信设备之间建立通信。

8. 发明授权

US09929829B1 System and method for provisioning resources for lossless operation in a network environment 有权
公开(公告)号：US09929829B1
公开(公告)日：2018-03-27
申请号：US13397062
申请日：2012-02-15
申请人： Wei-Jen Huang , Chih-Tsung Huang
发明人： Wei-Jen Huang , Chih-Tsung Huang
IPC分类号： H04L1/00
CPC分类号： H04L1/00 , H04L47/10
摘要： A method is provided in one example embodiment that includes measuring a delay between a transmitter and a receiver in a network environment, where the receiver is associated with a buffer. A minimum absorption buffer size for lossless transmission to a queue may be determined based on the delay and a transmission bandwidth, and buffer units for the queue can be allocated based on the minimum absorption buffer size. The transmitter may also be rate-limited if the minimum absorption buffer size exceeds available storage of the buffer. In other embodiments, buffer units can be reclaimed if the available buffer storage exceeds the minimum absorption buffer size.

9. 发明申请

US20120054427A1 INCREASING DATA ACCESS PERFORMANCE 审中-公开
标题翻译：提高数据访问性能
公开(公告)号：US20120054427A1
公开(公告)日：2012-03-01
申请号：US12870566
申请日：2010-08-27
申请人： WEI-JEN HUANG , Chih-Tsung Huang , Sachin Agarwal , Sha Ma
发明人： WEI-JEN HUANG , Chih-Tsung Huang , Sachin Agarwal , Sha Ma
IPC分类号： G06F12/00 , G06F15/173
CPC分类号： G06F3/061 , G06F3/06 , G06F3/0659 , G06F3/067
摘要： Techniques are described for increasing data access performance for a memory device. In various embodiments, a scheduler/controller is configured to manage data as it read to or written from a memory. Read access is increased by partitioning a memory into a group of sub-blocks, associating a parity block with the sub-blocks, and accessing the sub-blocks to read data as needed. Write speeds may be improved by adding a pending write buffer to a group of memory sub-blocks. Such a buffer may be sized to be equal to the group of memory sub-blocks. The pending write buffer is used to handle collisions for write accesses to the same block, allowing two simultaneous writes to any regular memory block to occur.
摘要翻译：描述了用于增加存储器设备的数据访问性能的技术。在各种实施例中，调度器/控制器被配置为在从存储器读取或从存储器写入时管理数据。通过将存储器划分成一组子块，将奇偶校验块与子块相关联，以及根据需要访问子块以读取数据来增加读取访问。通过将一个待处理的写入缓冲区添加到一组存储器子块可以改善写入速度。这样的缓冲器的大小可以等于存储器子块组。待处理写缓冲区用于处理对同一块的写入访问的冲突，允许发生任何常规内存块的两次同时写入。

10. 发明授权

US09049200B2 System and method for improving hardware utilization for a bidirectional access controls list in a low latency high-throughput network 有权
标题翻译：用于在低延迟高吞吐量网络中提高双向访问控制列表的硬件利用率的系统和方法
公开(公告)号：US09049200B2
公开(公告)日：2015-06-02
申请号：US13560154
申请日：2012-07-27
申请人： Mingzhe Li , Alessandro Fulli , Putu Harry Subagio , Chih-Tsung Huang
发明人： Mingzhe Li , Alessandro Fulli , Putu Harry Subagio , Chih-Tsung Huang
IPC分类号： H04L12/28 , H04L9/32 , H04N7/16 , G06F17/30 , H04L29/06
CPC分类号： H04L63/101 , G06F17/30595 , H04L63/0236
摘要： A method in an example embodiment includes creating a first search key from variable data of a message received in a network environment, creating a second search key from constant data of the message, identifying a first database entry in a first database based on the first search key, and identifying a second database entry in a second database based on the second search key. The method can also include performing an action associated with the first database entry when a correlation is identified between the first and second database entries. In specific embodiments, the variable data are modified and the constant data are not modified. The first search key can be created prior or subsequent to forwarding the message. In further embodiments, the correlation is identified when an offset of the first database entry is the same as an offset of the second database entry.
摘要翻译：示例实施例中的方法包括从在网络环境中接收的消息的可变数据创建第一搜索关键字，从所述消息的常数数据创建第二搜索关键字，基于所述第一搜索来识别第一数据库中的第一数据库条目密钥，以及基于第二搜索关键字识别第二数据库中的第二数据库条目。该方法还可以包括当在第一和第二数据库条目之间识别相关性时执行与第一数据库条目相关联的动作。在具体实施例中，修改变量数据并且不修改常量数据。可以在转发消息之前或之后创建第一个搜索关键字。在另外的实施例中，当第一数据库条目的偏移量与第二数据库条目的偏移量相同时，识别相关性。

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