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1. 发明授权

US06212639B1 Encryption of configuration stream 有权
标题翻译：加密配置流
公开(公告)号：US06212639B1
公开(公告)日：2001-04-03
申请号：US09342336
申请日：1999-06-29
申请人： Charles R. Erickson , Danesh Tavana , Victor A. Holen
发明人： Charles R. Erickson , Danesh Tavana , Victor A. Holen
IPC分类号： H04K100
CPC分类号： G06F21/57 , G06F12/1408 , G06F21/85
摘要： A method of communicating encrypted configuration data between a programmable logic device (PLD) and a storage device is included in one part of the invention. The method includes the following steps. Transmit encrypted configuration data stored in a storage device to the PLD. Decrypt the encrypted configuration data to generate a copy of the configuration data in the PLD. Configure the PLD using the copy of the configuration data. In one embodiment, the PLD transmits a key to the storage device. In another embodiment the key is separately entered into the storage device and the PLD and never transmitted between the PLD and the storage device. In another embodiment, the key is entered only into the PLD. The key is used to encrypt the configuration data.
摘要翻译：在可编程逻辑器件（PLD）和存储器件之间传送加密配置数据的方法包括在本发明的一部分中。该方法包括以下步骤。将存储在存储设备中的加密配置数据发送到PLD。解密加密的配置数据以生成PLD中的配置数据的副本。使用配置数据的副本配置PLD。在一个实施例中，PLD将密钥发送到存储设备。在另一个实施例中，密钥分别输入到存储设备和PLD中，并且从未在PLD和存储设备之间传送密钥。在另一个实施例中，键仅输入到PLD中。密钥用于加密配置数据。

2. 发明授权

US5883525A FPGA architecture with repeatable titles including routing matrices and logic matrices 失效
标题翻译：具有可重复标题的FPGA架构，包括路由矩阵和逻辑矩阵
公开(公告)号：US5883525A
公开(公告)日：1999-03-16
申请号：US943890
申请日：1997-10-03
申请人： Danesh Tavana , Wilson K. Yee , Victor A. Holen
发明人： Danesh Tavana , Wilson K. Yee , Victor A. Holen
IPC分类号： H03K19/177 , H03K7/38
CPC分类号： H03K19/17736 , H03K19/17704 , H03K19/17796
摘要： An FPGA architecture offers logic elements with direct connection to neighboring logic elements and indirect connection through a routing matrix. A logic element and a portion of the routing matrix are formed as part of a tile, and tiles are joined to form arrays of selectable size. The routing matrix includes routing lines which connect just from one tile to the next and routing lines which extend longer distances through several tiles or through the entire chip. This combination is achieved by the formation of individual tiles, all of which are identical.
摘要翻译： FPGA架构提供了通过路由矩阵直接连接到相邻逻辑元件和间接连接的逻辑元件。逻辑元件和路由矩阵的一部分被形成为瓦片的一部分，并且瓦片被连接以形成可选择尺寸的阵列。路由矩阵包括仅从一个瓦片连接到下一个瓦片的路由线路，以及通过几个瓦片或整个芯片延长更长距离的路由线路。这种组合是通过形成各个瓷砖来实现的，所有这些瓷砖都是相同的。

3. 发明授权

US5682107A FPGA architecture with repeatable tiles including routing matrices and logic matrices 失效
标题翻译：具有可重复瓦片的FPGA架构，包括路由矩阵和逻辑矩阵
公开(公告)号：US5682107A
公开(公告)日：1997-10-28
申请号：US618445
申请日：1996-03-19
申请人： Danesh Tavana , Wilson K. Yee , Victor A. Holen
发明人： Danesh Tavana , Wilson K. Yee , Victor A. Holen
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H03K19/17704 , H03K19/17796
摘要： An FPGA architecture offers logic elements with direct connection to neighboring logic elements and indirect connection through a routing matrix. A logic element and a portion of the routing matrix are formed as part of a tile, and tiles are joined to form arrays of selectable size. The routing matrix includes routing lines which connect just from one tile to the next and routing lines which extend longer distances through several tiles or through the entire chip. This combination is achieved by the formation of individual tiles, all of which are identical.
摘要翻译： FPGA架构提供了通过路由矩阵直接连接到相邻逻辑元件和间接连接的逻辑元件。逻辑元件和路由矩阵的一部分被形成为瓦片的一部分，并且瓦片被连接以形成可选择尺寸的阵列。路由矩阵包括仅从一个瓦片连接到下一个瓦片的路由线路，以及通过几个瓦片或整个芯片延长更长距离的路由线路。这种组合是通过形成各个瓷砖来实现的，所有这些瓷砖都是相同的。

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