会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 7. 发明公开
    • 자기 정렬되는 메모리 소자 및 워드라인
    • 自对准的记忆元素和WORDLINE
    • KR1020050085417A
    • 2005-08-29
    • KR1020057010298
    • 2003-09-08
    • 어드밴스드 마이크로 디바이시즈, 인코포레이티드
    • 츄엉패트릭케이.카츄리아애쇽엠.
    • H01L27/10
    • H01L27/28
    • An organic polymer memory cell is provided having an organic polymer layer (116, 2108, 2132, 2168) and an electrode layer (120, 2112, 2128, 2164) formed over a first conductive (e. g., copper) layer (e.g., bitline) (104, 108). The memory cells are connected to a second conductive layer (e.g., forming a wordline) (136, 2148, 2160), and more particularly the top of the electrode layer of the memory cells to the second conductive layer. Optionally, a conductivity facilitating layer (112, 2136) is formed over the conductive layer. Dielectric material separates the memory cells. The memory cells are self- aligned with the bitlines formed in the first conductive layer and the wordlines formed in the second conductive layer.
    • 提供了一种有机聚合物记忆单元,其具有形成在第一导电(例如铜)层(例如,位线)上的有机聚合物层(116,210,2132,2168)和电极层(120,2112,2128,2644) (104,108)。 存储器单元连接到第二导电层(例如,形成字线)(136,2148,2160),更具体地,将存储器单元的电极层的顶部连接到第二导电层。 可选地,在导电层上形成导电促进层(112,2166)。 电介质材料分离存储单元。 存储单元与在第一导电层中形成的位线和在第二导电层中形成的字线自对准。
    • 8. 发明公开
    • 수직나노튜브를 이용한 메모리
    • 使用垂直纳米管的记忆
    • KR1020040060370A
    • 2004-07-06
    • KR1020020087158
    • 2002-12-30
    • 삼성전자주식회사
    • 정병호최원봉
    • H01L27/115B82Y10/00
    • H01L51/0048B82Y10/00G11C13/025G11C2213/16H01L27/28H01L27/285Y10S438/962Y10S977/943
    • PURPOSE: A memory using a vertical nano-tube is provided to increase a degree of integration and capacity by using a vertical carbon nano-tube. CONSTITUTION: A memory using a vertical nano-tube includes the first electrode array, a dielectric layer, a nano-tube array, the second electrode array, a memory cell, and a gate electrode. The first electrode array is formed with stripe patterns. The dielectric layer(12) is laminated on the first electrode array. A plurality of holes are arranged on the dielectric layer. The nano-tube array is close to the first electrode array in order to emit electrons. The second electrode array is formed on the dielectric layer. The memory cell(15) is installed on the second electrode array in order to capture the electrons from the nano-tube array. The gate electrode(17) is laminated on the memory cell in order to form the electric field around the nano-tube array.
    • 目的:提供使用垂直纳米管的记忆体,以通过使用垂直碳纳米管来增加一体化程度和容量。 构成:使用垂直纳米管的存储器包括第一电极阵列,电介质层,纳米管阵列,第二电极阵列,存储单元和栅电极。 第一电极阵列形成条纹图案。 电介质层(12)层压在第一电极阵列上。 多个孔布置在电介质层上。 纳米管阵列靠近第一电极阵列以发射电子。 第二电极阵列形成在电介质层上。 存储单元(15)安装在第二电极阵列上,以便从纳米管阵列捕获电子。 为了形成纳米管阵列周围的电场,将栅电极(17)层叠在存储单元上。