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1. 发明公开

KR1020160018098A 반도체 장치의 테스트 회로 및 테스트 방법 审中-实审
标题翻译：半导体器件的测试电路和测试方法
公开(公告)号：KR1020160018098A
公开(公告)日：2016-02-17
申请号：KR1020140102176
申请日：2014-08-08
申请人： 에스케이하이닉스 주식회사
发明人： 구기봉 , 윤병국
IPC分类号： G01R31/26
CPC分类号： H03K21/08 , G01R31/30 , G11C29/021 , G11C29/12015 , G11C29/50 , G11C29/50012
摘要： 반도체장치의테스트회로는주기신호카운팅부, 클럭신호카운팅부및 업데이트레지스터를포함한다. 상기주기신호카운팅부는주기신호를기설정된횟수만큼카운팅한후 오버플로우신호를인에이블시킨다. 상기클럭신호카운팅부는상기오버플로우신호가인에이블될때까지내부클럭신호를카운팅하여클럭카운팅코드를출력한다. 상기업데이트레지스터는상기오버플로우신호에기초하여상기클럭카운팅코드를수신하여저장한다.
摘要翻译：半导体器件测试电路包括周期性信号计数单元，时钟信号计数单元和更新电阻器。周期信号计数单元对周期信号进行计数直到预定时间，并使能溢出信号。时钟信号计数单元对内部时钟信号进行计数，直到溢出信号使能为止，并输出时钟计数代码。更新电阻根据溢出信号接收并存储时钟计数码。

2. 发明公开

KR1020090107615A 피오이 스위치 테스트 장치 有权
标题翻译：以太网切换测试装置的电源
公开(公告)号：KR1020090107615A
公开(公告)日：2009-10-14
申请号：KR1020080032969
申请日：2008-04-10
申请人： (주)한드림넷
发明人： 이승민
IPC分类号： G01R31/00
CPC分类号： G01R31/30 , G01R31/282 , H01C10/14 , H04L43/00
摘要： PURPOSE: A PoE(Power over Ethernet) switch test apparatus is provided to perform various test mode simply by testing the PoE switch while changing a resistor value and a PoE class. CONSTITUTION: A test controller receives power/data from a PoE switch, separates the power, and supplies the separated power. A variable resistor(250) consumes the power according to the power supplied by the test controller. A cooler(270) cools down the heat generated in a variable resistor and consumes the power supplied by the test controller. A resistor selection switch(260) selects the resistance value of the variable resistor. A PoE class selection switch(390) selects the PoE class indicating the maximum allowable power. The PoE class selection switch determines the class of the PoE switch test apparatus based on the consumed current.
摘要翻译：目的：提供PoE（以太网供电）开关测试装置，只需通过在改变电阻值和PoE等级的同时测试PoE开关来执行各种测试模式。规定：测试控制器从PoE交换机接收电源/数据，分离电源，并提供分离的电源。可变电阻（250）根据测试控制器提供的电源消耗电力。冷却器（270）冷却可变电阻器中产生的热量并消耗由测试控制器提供的电力。电阻选择开关（260）选择可变电阻器的电阻值。 PoE类选择开关（390）选择表示最大允许功率的PoE类。 PoE类选择开关根据消耗电流决定PoE交换机测试设备的类别。

3. 发明公开

KR1020070120289A ＤＣ 아웃 릴레이의 자가 진단 방법 有权
标题翻译：直流输出继电器自诊断方法
公开(公告)号：KR1020070120289A
公开(公告)日：2007-12-24
申请号：KR1020060054858
申请日：2006-06-19
申请人： 주식회사 에이티테크놀러지
发明人： 현병철
IPC分类号： G01R31/3187
CPC分类号： G01R31/3187 , G01R31/2831 , G01R31/30
摘要： A method for self-diagnosing a DC-out relay is provided to self-diagnose whether the DC-out relay is normally operated, through the on/off control of the DC-out relay, a DC pulse relay and a DC diagnosis relay in a main test apparatus. A method for self-diagnosing a DC-out relay comprises the following steps of: inputting a reference signal to a DC unit for diagnosing an operating state of the DC-out relay(S1); inputting the reference signal to a pulse driving part through the DC-out relay of the DC unit(S3); outputting the reference signal from the pulse driving part to the DC unit again(S5); measuring an potential difference which is generated while the reference signal passes through the internal resistance of the DC unit(S7); and determining the on/off operating state of the DC-out relay according to a size of the measured potential difference(S9).
摘要翻译：提供一种用于自诊断DC输出继电器的方法，通过直流输出继电器的开/关控制，直流脉冲继电器和直流诊断继电器自诊断直流输出继电器是否正常工作主要测试仪器。一种用于自诊断DC输出继电器的方法包括以下步骤：将参考信号输入到用于诊断DC输出继电器的运行状态的DC单元（S1）; 通过DC单元的DC-out继电器将参考信号输入到脉冲驱动部分（S3）; 将参考信号从脉冲驱动部分再次输出到DC单元（S5）; 测量在参考信号通过DC单元的内部电阻时产生的电位差（S7）; 以及根据所测量的电位差的大小确定所述DC输出继电器的接通/断开操作状态（S9）。

4. 发明授权

KR100212608B1 CMOS 집적 회로 고장 진단 장치 및 진단 방법 失效
标题翻译： CMOS集成电路故障诊断设备和诊断方法
公开(公告)号：KR100212608B1
公开(公告)日：1999-08-02
申请号：KR1019970000594
申请日：1997-01-11
申请人： 닛본 덴끼 가부시끼가이샤
发明人： 사까구찌가즈히로
IPC分类号： G01R31/28
CPC分类号： G01R31/3008 , G01R31/30 , G01R31/3004 , G01R31/318342 , G06F11/22 , G06F11/261
摘要： A failure diagnosis apparatus is provided which predicts failure locations in a CMOS integrated circuit in which an Iddq has been discovered, this apparatus having a test pattern storage unit 1 for storing test patterns used to perform a functional test of the CMOS integrated circuit, an LSI tester 3 which performs a functional test and an Iddq test on the CMOS integrated circuit based on the test patterns, a test results storage unit 6 to store test results, a circuit data storage unit 2 to store various information with regard to the device under test, a logic simulator 5 for receiving the above-noted test patterns and circuit data and performing a logic simulation of the internal operation of the circuit, a simulation results storage unit 7, and a failure location judgment unit 8 for outputting the diagnosis results based on test results and simulation results. This diagnosis apparatus predicts short circuit failures between signal lines and between a signal line and either a power supply line or a ground line, based, on the results of a simulation of internal circuit signal values at a point in time at which a test pattern is applied for which an abnormality is not detected in an Iddq test.

5. 发明授权

KR100138114B1 집적 회로의 다중 전원 접속부 검사 방법 및 그 장치 失效
标题翻译：用于在印刷电路板上测试多个电源连接集成电路的方法和装置
公开(公告)号：KR100138114B1
公开(公告)日：1998-06-15
申请号：KR1019890010125
申请日：1989-07-18
申请人： 코닌클리케 필립스 엔.브이.
发明人： 디르크반데라게마트
IPC分类号： G01R31/00
CPC分类号： G01R31/30 , G01R31/2853 , H01L2224/48091 , H01L2924/00011 , H01L2924/00014 , H01L2924/01005 , H01L2924/01034 , H01L2224/45147 , H01L2224/45099
摘要： 내용 없음
摘要翻译：描述了一个测试组织，用于测试集成电路相同额定电源电压的多个电源连接的正确操作。该集成电路设置有测试比较电路，其能够通过相应的测试线测量电压差（如果有的话）。如果一个电源连接不能正确连接，则电压差可能会变得太高; 这通过错误信号的方式发信号。

6. 发明授权

KR1019930011704B1 반도체 집적 회로장치 및 그 테스트방법 失效
标题翻译：半导体集成电路装置及其测试方法
公开(公告)号：KR1019930011704B1
公开(公告)日：1993-12-18
申请号：KR1019900010486
申请日：1990-07-11
申请人： 후지쯔 가부시끼가이샤
发明人： 야마무라다께시
IPC分类号： H01L21/66 , H01L27/00
CPC分类号： G01R31/318555 , G01R31/30 , G01R31/31855 , G06F11/27
摘要： 내용 없음.

7. 发明授权

KR1019930000209B1 회로판내의 고장 검사장치 失效
标题翻译：电路板中的故障检测装置
公开(公告)号：KR1019930000209B1
公开(公告)日：1993-01-14
申请号：KR1019890010688
申请日：1989-07-28
申请人： 디지탈 이큅먼트 코포레이션
发明人： 다비드시.브라운
IPC分类号： G01R31/00 , G06F11/22
CPC分类号： G01R31/318505 , G01R31/2818 , G01R31/30
摘要： 내용 없음.

8. 发明授权

KR1019920004653B1 반도체장치 失效
标题翻译：半导体集成电路
公开(公告)号：KR1019920004653B1
公开(公告)日：1992-06-12
申请号：KR1019830005979
申请日：1983-12-17
申请人： 가부시기가이샤히다찌세이사꾸쇼 , 히다찌마이크로콤퓨우터엔지니어링가부시기가이샤
发明人： 호리료이찌 , 이도교요오 , 다나가히도오시
IPC分类号： H01L27/00
CPC分类号： G01R31/30 , G05F1/465 , G11C5/145 , G11C5/147 , H01L27/0218
摘要： A voltage converter is disposed in a semiconductor integrated circuit so as to lower an external supply voltage (VCC) and to feed the lowered voltage (VL) to a partial circuit of the integrated circuit. The voltage converter is constructed so as to produce an output voltage (VL) suited to ordinary operation in the ordinary operation state of the semiconductor integrated circuit and an aging voltage in the aging test of the circuit.
摘要翻译：电压转换器设置在半导体集成电路中以降低外部电源电压（VCC）并将降低的电压（VL）馈送到集成电路的部分电路。电压转换器被构造成产生适于在半导体集成电路的正常操作状态下的正常操作的输出电压（VL）和电路的老化测试中的老化电压。

9. 发明公开

KR1020140014408A 시험장치용 전원장치 및 이를 이용한 시험장치 有权
标题翻译：用于测试设备的电源设备，以及使用设备的测试设备
公开(公告)号：KR1020140014408A
公开(公告)日：2014-02-06
申请号：KR1020120016077
申请日：2012-02-16
申请人： 가부시키가이샤 어드밴티스트
发明人： 시미즈,타카히코 , 데가와,카츠히코
IPC分类号： G01R31/28
CPC分类号： G01R31/2839 , G01R31/30 , G01R31/31721 , G01R31/3173
摘要： The present invention provides a power apparatus for performing the most optimal control for overload or parasitic impedance. In order to solve the problem, a first Analog-to-Digital (A/D) converter (22) converts an analog value (S2') which is supplied to a power source terminal (P1) of a Device under Test (DUT) (1) corresponding to the analog value (S2') to a digital value (S3). A digital signal processing circuit (24) is produced by a digital operation process of a control value (S4) which is to be adjusted to match a reference value Ref to the digital value (S3). A first Digital-to-Analog (D/A) converter (26) provides an analog source signal (S1) obtained from converting a control value (S4) from digital to analog to start a power supply line (4) to the power source terminal (P1) of DUT (1). A load estimator (40) authorizes a test signal (S7) which includes some of frequency components that provides the supply line (4) to a node (N1) of which the power source terminal (P1) needs to be connected to, and it generates a control parameter (S8) of the digital signal processing circuit (24) corresponding to the test signal (S7) and the analog value of an observation signal (S2'). [Reference numerals] (48) Calculation unit
摘要翻译：本发明提供一种用于对过载或寄生阻抗执行最佳控制的电力设备。为了解决该问题，第一模数（A / D）转换器（22）转换提供给被测器件（DUT）的电源端子（P1）的模拟值（S2'），（1）对应于模拟值（S2'）到数字值（S3）。数字信号处理电路（24）通过数字操作处理产生控制值（S4），该控制值（S4）将被调整以匹配参考值Ref与数字值（S3）。第一数模（D / A）转换器（26）提供通过将控制值（S4）从数字转换为模拟而获得的模拟源信号（S1），以将电源线（4）启动到电源 DUT（1）的端子（P1）。负载估计器（40）授权测试信号（S7），其包括将电源线（4）提供给电源端子（P1）需要连接到的节点（N1）的一些频率分量，并且产生对应于测试信号（S7）的数字信号处理电路（24）和观测信号（S2'）的模拟值的控制参数（S8）。（附图标记）（48）计算单元

10. 发明授权

KR101357368B1 복수의 온칩 모니터 회로들 및 제어 회로를 구비한 회로 장치 및 상응하는 방법 有权
标题翻译：具有多个片上监视器电路的电路布置以及控制电路和相应的方法
公开(公告)号：KR101357368B1
公开(公告)日：2014-02-03
申请号：KR1020120032115
申请日：2012-03-29
申请人： 인텔 도이칠란드 게엠베하
发明人： 바우만토마스 , 파차크리스티앙
IPC分类号： G01R31/28
CPC分类号： G01R31/2843 , G01D18/002 , G01R31/30
摘要： 여기에서 복수의 온칩 모니터 회로들 및 제어기를 포함하는 구현예들이 제시된다. 복수의 온칩 모니터 회로들 각각은 반도체 칩의 파라미터를 계측하도록 구성된다. 제어기는 복수의 온칩 모니터 회로들에 연결된다. 제어기는 복수의 온칩 모니터 회로들 중 적어도 한 개로부터 계측 결과를 수신하며 그 계측 결과에 따라 복수의 온칩 모니터 회로들 중 또 다른 한 개의 교정을 제어하도록 구성된다.

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