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1. 发明公开

KR1020120036429A 인쇄회로기판 형성 방법 无效
标题翻译：形成印刷电路板的方法
公开(公告)号：KR1020120036429A
公开(公告)日：2012-04-18
申请号：KR1020100098093
申请日：2010-10-08
申请人： 에스케이하이닉스 주식회사
发明人： 이준호 , 김현석 , 정부호 , 조선기 , 김양희 , 김영원
IPC分类号： H05K9/00 , H05K3/32
摘要： PURPOSE: A method for forming a printed circuit board is provided to reduce distortion of a signal inputted to a signal line by suppressing noises applied to a power voltage and a ground voltage. CONSTITUTION: A wire connected to a signal, a power voltage, and a ground voltage is formed on a substrate(10). A signal line unit(20) includes a first signal line(21) and a second signal line(22). A power line unit(30) includes a first power line unit(31) and a second power line unit(32). The first power line unit includes a first power line(31a), a first via(31b), and a first plate(31c). The second power line unit includes a second power line(32a), a second via(32b), and a second plate(32c).
摘要翻译：目的：提供一种用于形成印刷电路板的方法，以通过抑制施加于电源电压和接地电压的噪声来减少输入到信号线的信号的失真。构成：在基板（10）上形成连接到信号，电源电压和接地电压的电线。信号线单元（20）包括第一信号线（21）和第二信号线（22）。电力线单元（30）包括第一电力线单元（31）和第二电力线单元（32）。第一电力线单元包括第一电力线（31a），第一通孔（31b）和第一板（31c）。第二电力线单元包括第二电力线（32a），第二通孔（32b）和第二板（32c）。

2. 发明公开

KR1020120019690A 캐패시터 형성 방법과 이를 이용한 반도체 소자 无效
标题翻译：用于形成电容器和使用该电容器的半导体器件的方法
公开(公告)号：KR1020120019690A
公开(公告)日：2012-03-07
申请号：KR1020100083052
申请日：2010-08-26
申请人： 에스케이하이닉스 주식회사
发明人： 김현석 , 이준호 , 정부호 , 조선기 , 김양희 , 김영원
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L28/90 , H01L27/0808 , H01L27/0811 , H01L29/94
摘要： PURPOSE: A method for forming a capacitor and a semiconductor device using the same are provided to improve the noise attenuation efficiency of a decoupling capacitor by decreasing the resistance of a wire which connects the decoupling capacitor to a power voltage. CONSTITUTION: A first MOS capacitor(MOS_CP1) includes a first gate and a first source/drain. A second MOS capacitor(MOS_ CP2) includes a second gate and a second source/drain. A first cylinder capacitor(CYL_CP1) includes a top electrode, a first dielectric layer, and a first bottom electrode. A second cylinder capacitor(CYL_CP2) includes a top electrode, a second dielectric layer, and a second bottom electrode. A metal wire(10A,10B) connects the gate to the bottom electrode.
摘要翻译：目的：提供一种用于形成电容器的方法和使用该电容器的半导体器件，以通过降低将去耦电容器连接到电源电压的电线的电阻来改善去耦电容器的噪声衰减效率。构成：第一MOS电容器（MOS_CP1）包括第一栅极和第一源极/漏极。第二MOS电容器（MOS_CP2）包括第二栅极和第二源极/漏极。第一气缸电容器（CYL_CP1）包括顶电极，第一电介质层和第一底电极。第二气缸电容器（CYL_CP2）包括顶电极，第二电介质层和第二底电极。金属线（10A，10B）将栅极连接到底部电极。

3. 发明授权

KR101047061B1 반도체 장치의 출력 회로 失效
标题翻译：半导体存储器的输出电路
公开(公告)号：KR101047061B1
公开(公告)日：2011-07-06
申请号：KR1020100009911
申请日：2010-02-03
申请人： 에스케이하이닉스 주식회사
发明人： 정부호 , 이준호 , 김현석 , 김양희
IPC分类号： G11C7/10 , G11C11/21 , G11C11/24
CPC分类号： H01L25/00 , H01L2924/0002 , H01L2924/00
摘要： PURPOSE: An output circuit of a semiconductor memory apparatus is provided to minimize power noise in all frequency bands by arranging first and second capacitors which have different properties. CONSTITUTION: First and second pads(112,114) supply a power voltage and a ground voltage. A main output part(120) provides the power voltage and the ground voltage from the first and second pads. One end of a decoupling capacitor area(130a) is connected to the first pad. The other end of the decoupling capacitor area is connected to the second pad. The decoupling capacitor area comprises first and second decoupling capacitor areas. The first decoupling capacitor area is formed by a first distance from a part of the main output unit. The second decoupling capacitor area is formed by a second distance from the main output unit. The second distance is longer than the first distance.
摘要翻译：目的：提供半导体存储装置的输出电路，通过布置具有不同性质的第一和第二电容器来最小化所有频带的功率噪声。构成：第一和第二焊盘（112,114）提供电源电压和接地电压。主输出部分（120）提供来自第一和第二焊盘的电源电压和接地电压。去耦电容器区域（130a）的一端连接到第一焊盘。去耦电容器区域的另一端连接到第二焊盘。去耦电容器区域包括第一和第二去耦电容器区域。第一去耦电容器区域由与主输出单元的一部分的第一距离形成。第二去耦电容器区域与主输出单元形成第二距离。第二距离比第一距离长。

4. 发明授权

KR101046275B1 파워 메쉬 구조를 갖는 반도체 메모리 장치 失效
标题翻译：半导体存储器包括功率结构
公开(公告)号：KR101046275B1
公开(公告)日：2011-07-04
申请号：KR1020100027820
申请日：2010-03-29
申请人： 에스케이하이닉스 주식회사
发明人： 정부호 , 이준호 , 김현석 , 조선기 , 김양희 , 김영원
IPC分类号： G11C8/14 , G11C7/18 , G11C8/12 , H01L21/28
CPC分类号： G11C5/063 , G11C5/025 , G11C7/06 , G11C8/08 , G11C8/14
摘要： PURPOSE: A semiconductor memory apparatus including a power-meshed structure is provided to improve power supply capability by connecting a plate electrode or a stable pattern to a power line connected to a column control block. CONSTITUTION: A plurality of banks comprises a semiconductor memory device for having a plurality of cell mat power mesh structures. A plurality of power lines are arranged in the prescribed part of a plurality of banks. A column control area is arranged in at least one region of the edge of the bank. A conductive plate is arranged on the top side of a column control region. The conductive plate is electrically connected to the plural power lines.
摘要翻译：目的：提供一种包括电源网格结构的半导体存储装置，通过将平板电极或稳定图案连接到连接到列控制块的电力线来提高电力供应能力。构成：多个存储体包括用于具有多个电池垫功率网格结构的半导体存储器件。多个电源线布置在多个银行的规定部分中。列控制区域布置在堤岸的边缘的至少一个区域中。导电板设置在列控制区域的顶侧。导电板电连接到多条电源线。

5. 发明公开

KR1020140082180A 반도체 장치의 데이터 출력 회로 审中-实审
标题翻译：半导体器件的数据输出电路
公开(公告)号：KR1020140082180A
公开(公告)日：2014-07-02
申请号：KR1020120151746
申请日：2012-12-24
申请人： 에스케이하이닉스 주식회사
发明人： 오익수 , 이준호 , 김현석 , 정부호 , 조선기 , 김양희
IPC分类号： G11C7/10 , G11C7/12
CPC分类号： G11C7/1051 , G11C7/22 , G11C17/16 , G11C17/18 , G11C2207/105
摘要： A data output circuit of a semiconductor apparatus comprises: a free driver which drives data according to a strength control signal and a slew rate control signal and generates a pull up signal and a pull down signal; a data output driver which drives a data input/output pad in response to the pull up signal and the pull down signal; and a control signal generating unit which generates the driving strength control signal corresponding to preset driving strength, detects a driving strength change degree according to the driving strength control signal, and generates the slew rate control signal to control a slew rate suitable for the detected driving strength change degree.
摘要翻译：半导体装置的数据输出电路包括：根据强度控制信号和转换速率控制信号驱动数据的自由驱动器，并产生上拉信号和下拉信号; 数据输出驱动器，其响应于上拉信号和下拉信号驱动数据输入/输出焊盘; 产生与预先设定的驱动强度对应的驱动强度控制信号的控制信号生成部，根据驱动强度控制信号，检测驱动强度变化程度，生成转换速度控制信号，控制适合检测到的驱动的转换速度力量变化程度。

6. 发明公开

KR1020130134071A 관통 전극을 갖는 반도체 집적 회로 장치 无效
标题翻译：具有电极的半导体集成电路设备
公开(公告)号：KR1020130134071A
公开(公告)日：2013-12-10
申请号：KR1020120057329
申请日：2012-05-30
申请人： 에스케이하이닉스 주식회사
发明人： 이준호 , 김현석 , 정부호 , 조선기 , 김양희 , 김영원
IPC分类号： H01L21/28
CPC分类号： H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： Provided is a semiconductor integrated circuit device capable of improving a signal transmission property. The semiconductor integrated circuit device according to one embodiment of the present invention includes a semiconductor substrate, a plurality of through silicon via which is formed on the semiconductor substrate and has mutual potential differences, and an impedance path blocking unit which is located between the through silicon via.
摘要翻译：提供能够提高信号传输性能的半导体集成电路器件。根据本发明的一个实施例的半导体集成电路器件包括半导体衬底，形成在半导体衬底上并具有互电位差的多个贯通硅，以及位于贯通硅之间的阻抗通路阻断单元通过。

7. 发明公开

KR1020130072043A 반도체 소자 및 제조방법 无效
标题翻译：半导体器件及其制造方法
公开(公告)号：KR1020130072043A
公开(公告)日：2013-07-01
申请号：KR1020110139588
申请日：2011-12-21
申请人： 에스케이하이닉스 주식회사
发明人： 김영원 , 이준호 , 김현석 , 정부호 , 조선기 , 김양희
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L28/40 , H01L21/7687 , H01L28/60
摘要： PURPOSE: A semiconductor device and a manufacturing method thereof are provided to reduce equivalent series resistance by replacing a MOS capacitor structure with a dummy layer having a low resistance value. CONSTITUTION: The shape of a storage electrode (230) corresponds to the shape of a plate electrode (210). A dielectric layer (220) is formed between the plate electrode and the storage electrode. The dielectric layer is the capacitor (CAP) of a cell capacitor structure. A metal line (240) connects storage electrodes electrically. A dummy layer (250) supports a structure formed on the metal line.
摘要翻译：目的：提供半导体器件及其制造方法，通过用具有低电阻值的虚设层代替MOS电容器结构来降低等效的串联电阻。构成：存储电极（230）的形状对应于平板电极（210）的形状。在平板电极和存储电极之间形成介电层（220）。电介质层是电池电容器结构的电容器（CAP）。金属线（240）电连接存储电极。虚拟层（250）支撑形成在金属线上的结构。

8. 发明公开

KR1020110098039A 멀티 칩 패키지 有权
标题翻译： MUTI芯片包
公开(公告)号：KR1020110098039A
公开(公告)日：2011-09-01
申请号：KR1020100017458
申请日：2010-02-26
申请人： 에스케이하이닉스 주식회사
发明人： 김영원 , 이준호 , 김현석 , 정부호 , 조선기 , 김양희
IPC分类号： G11C5/06 , G11C5/04 , G11C7/10
CPC分类号： H01L25/0657 , H01L23/48 , H01L2225/06531 , H01L2924/00013 , H01L2924/0002 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2924/00
摘要： 본 발명은 멀티 칩 패키지에 관한 것으로, 다수의 칩이 적층된 멀티 칩 패키지에 있어서, 상기 다수의 칩 각각은 서로 전원 또는 신호를 전달하도록 구성된 다수의 인덕터 패드를 포함하되, 상기 다수의 인덕터 패드 중 어느 하나인 기준 인덕터 패드의 양측에는 서로 다른 자속 방향을 가지는 제1 및 제2 인덕터 패드가 형성된다.

9. 发明公开

KR1020110076138A 반도체 메모리 장치 无效
标题翻译：半导体存储器
公开(公告)号：KR1020110076138A
公开(公告)日：2011-07-06
申请号：KR1020090132767
申请日：2009-12-29
申请人： 에스케이하이닉스 주식회사
发明人： 김양희 , 이준호 , 김현석 , 정부호
IPC分类号： G11C5/14 , G11C7/22
CPC分类号： G11C5/14 , G11C5/063 , G11C7/22
摘要： PURPOSE: A semiconductor memory apparatus is provided to improve operation reliability by supplying a stable driving voltage to an internal circuit regardless of an operation frequency. CONSTITUTION: In a semiconductor memory apparatus, the frequency of a clock is over a predetermined value. A clock period sensing unit(100) enables a counting start. A counter(200) counts a counting signal. A power line voltage stabilizing unit(300) applies the voltage of the power line to a capacitor through a resistor. The power line voltage stabilizing unit applies the voltage of the power line to the capacitor directly.
摘要翻译：目的：提供一种半导体存储装置，通过向内部电路提供稳定的驱动电压来提高操作可靠性，而与操作频率无关。构成：在半导体存储装置中，时钟的频率超过规定值。时钟周期检测单元（100）启用计数开始。计数器（200）计数计数信号。电力线电压稳定单元（300）通过电阻将电力线的电压施加到电容器。电力线电压稳定单元将电力线的电压直接施加到电容器。

10. 发明公开

KR1020140028691A 반도체 장치의 출력 데이터 노이즈 제거 방법 및 이를 구현하는 반도체 장치 审中-实审
标题翻译：用于实现方法的半导体装置和半导体装置的输出数据噪声减少方法
公开(公告)号：KR1020140028691A
公开(公告)日：2014-03-10
申请号：KR1020120095552
申请日：2012-08-30
申请人： 에스케이하이닉스 주식회사
发明人： 한성우 , 오익수 , 이준호 , 정부호 , 조선기 , 김양희 , 김태훈
IPC分类号： G11C7/10
CPC分类号： H03K3/013 , G06F17/5022 , H03K5/12
摘要： A semiconductor device includes a plurality of output buffers and a data noise measurement unit. The output buffers are driven by a power voltage and a ground voltage, and outputs received data. The data noise measurement unit measures the size of data noise from output data of a specific output buffer of the output buffers, and generates a slew rate adjustment signal for adjusting a slew rate of the output buffers, based on the measurement result. [Reference numerals] (210) AC component extractor; (220) Amplifier; (230) Rectifier; (240) Analog-to-digital converter
摘要翻译：半导体器件包括多个输出缓冲器和数据噪声测量单元。输出缓冲器由电源电压和接地电压驱动，并输出接收到的数据。数据噪声测量单元基于输出缓冲器的特定输出缓冲器的输出数据来测量数据噪声的大小，并且基于测量结果生成用于调整输出缓冲器的转换速率的转换速率调整信号。（附图标记）（210）交流分量提取器; （220）放大器; （230）整流器; （240）模数转换器

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