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1. 发明授权

KR101732645B1 에스램 셀을 포함하는 반도체 소자 및 그 제조 방법 有权
标题翻译：包括ESRAM单元的半导体器件及其制造方法
公开(公告)号：KR101732645B1
公开(公告)日：2017-05-08
申请号：KR1020100031480
申请日：2010-04-06
申请人： 삼성전자주식회사
发明人： 권오겸 , 김병선 , 이태정
IPC分类号： H01L27/11 , H01L27/02
CPC分类号： H01L27/1104 , H01L27/0207 , H01L27/11 , Y10S257/909
摘要： 에스램셀을포함하는반도체소자및 그제조방법을제공한다. 이소자는기판에형성된로드트랜지스터, 구동트랜지스터및 액세스트랜지스터를포함할수 있다. 로드, 구동및 액세스트랜지스터들의제1 소오스/드레인들은일 노드에연결된다. 파워라인, 접지라인및 비트라인이로드트랜지스터의제2 소오스/드레인, 구동트랜지스터의제2 소오스/드레인및 액세스트랜지스터의제2 소오스/드레인에각각전기적으로접속된다. 파워, 접지및 비트라인들은제1 방향으로나란히연장되고서로동일한레벨에위치한다. 워드라인이액세스트랜지스터의게이트에전기적으로연결되고, 제2 방향으로연장된다. 워드라인은파워, 접지및 비트라인들과다른레벨에위치한다.
摘要翻译：提供了一种包括Srammell的半导体器件及其制造方法。异丁烷可为负载晶体管，驱动晶体管和形成在基板上的存取晶体管。所述负载的第一源极/漏极，驱动器和存取晶体管被连接到一个节点。电源线，地线线和位线分别电连接到所述第二源极/漏极，第二源极/漏极的第二源极/漏极和所述负载晶体管的驱动晶体管的存取晶体管。电源，地，和位线在位于彼此相同的电平的第一方向延伸的并列。与字线电连接到所述存取晶体管的栅极和在第二方向上延伸。字线位于与电源，地和位线不同的级别。

2. 发明公开

KR1020140124272A 전자 장치 및 그 결합 구조 审中-实审
标题翻译：电子设备及其组装结构
公开(公告)号：KR1020140124272A
公开(公告)日：2014-10-24
申请号：KR1020130041810
申请日：2013-04-16
申请人： 삼성전자주식회사
发明人： 박승화 , 김병선 , 정현미
IPC分类号： H05K5/02 , G06F1/16
CPC分类号： G06F1/1662 , G06F1/1626 , G06F1/1656 , H05K5/02 , G06F1/16 , G06F1/1601 , H05K5/0217
摘要： 본 개시의 다양한 실시예들에 따르며, 전자 장치는 전자 장치의 전방에 배치되는 프론트 하우징과, 상기 프론트 하우징에 결합되고, 다수의 전자 부품들이 고정되는 브라켓 및 레일에서 이탈되지 않고 탄성 지지를 받으면서 미끄럼 이동 가능한 적어도 하나의 슬라이더를 가지고, 상기 적어도 하나의 슬라이더에 의해 상기 브라켓에 탈부착 가능하며, 상기 전자 장치의 후방에 배치되는 리어 하우징을 가질 수 있다. 다양한 실시예들이 가능하다.
摘要翻译：根据本公开的各种实施例，电子设备具有布置在电子设备的前表面上的前壳体; 与前壳体结合并固定在电子部件上的支架; 以及后壳体，其具有至少一个滑块，所述至少一个滑块可以通过弹性地支撑在轨道上而不与所述轨道分离，所述滑块可以通过所述至少一个滑块附接到所述支架或从所述支架拆下，并且布置在电子设备的背面。各种实施例是可用的。

3. 发明公开

KR1020140118499A 전자 기기의 입력 장치 审中-实审
标题翻译：电子设备输入装置
公开(公告)号：KR1020140118499A
公开(公告)日：2014-10-08
申请号：KR1020130034542
申请日：2013-03-29
申请人： 삼성전자주식회사
发明人： 김병선 , 김철희
IPC分类号： H01H13/14 , H04B1/38
CPC分类号： H01H13/14 , G06F3/02 , H04M1/23
摘要： The present disclosure relates to an input device for an electronic apparatus capable of improving usability. The input device for the electronic apparatus includes a body which forms the outer appearance of the input device and a key base which is made of soft materials and is partially combined with the inner side of the body. The key base includes a press protrusion which is formed on the lower side of the key base and a receiving unit which is formed on the upper side thereof and is opposite to the press protrusion. The body includes a hard protrusion part which is received in the receiving unit of the key base.
摘要翻译：本公开涉及一种能够改善可用性的电子设备的输入装置。电子设备的输入装置包括形成输入装置的外观的主体和由软材料制成并与主体的内侧部分组合的键座。钥匙基座包括形成在钥匙基座的下侧的按压突起和形成在其上侧并与按压突起相对的接收单元。主体包括容纳在键座的接收单元中的硬突出部分。

4. 发明公开

KR1020130093223A 휴대용 단말기의 키패드 조명 장치 审中-实审
标题翻译：便携式终端键盘照明装置
公开(公告)号：KR1020130093223A
公开(公告)日：2013-08-22
申请号：KR1020120014617
申请日：2012-02-14
申请人： 삼성전자주식회사
发明人： 김병선
IPC分类号： H01H13/70 , H01H9/18 , H01L33/00
CPC分类号： H01H13/83 , G06F1/1662 , H04M1/22
摘要： PURPOSE: A keypad lighting device for portable terminal is provided to reduce the concentration of lighting in a specific direction, thereby improving the uniformity of lighting. CONSTITUTION: A keypad member is formed with the arrangement of key tops. A plurality of key tops is formed on the keypad member. At least one light emitting device (331) is arranged in the lower part of the keypad member. A light guide panel member (303) illuminates the key tops with light from the light emitting device. An incident surface (333b) of the light guide panel member is formed with a curved surface or a plurality of slopes.
摘要翻译：目的：提供便携式终端的键盘照明装置，以减少特定方向的照明浓度，从而提高照明的均匀性。构成：键盘构件形成有键顶的布置。多个键顶形成在键盘构件上。至少一个发光装置（331）布置在键盘构件的下部。导光板构件（303）用来自发光装置的光照亮键顶。导光板构件的入射表面（333b）形成有弯曲表面或多个斜面。

5. 发明公开

KR1020120059866A 휴대용 단말기의 키패드 조립체 有权
标题翻译：键盘组件用于便携式终端
公开(公告)号：KR1020120059866A
公开(公告)日：2012-06-11
申请号：KR1020100121351
申请日：2010-12-01
申请人： 삼성전자주식회사
发明人： 김병선 , 정민수 , 김철희
IPC分类号： H04M1/23 , H01H13/705
CPC分类号： H01H13/705 , H01H2221/056 , H01H2223/036 , H01H2231/022 , H01H2233/03 , H04M1/23
摘要： PURPOSE: A keypad assembly of a portable terminal is provided to extend space for arranging key tops by including a combination member combined with an inner wall of a housing unit in a terminal. CONSTITUTION: An operating member(221) is changed according to the operation of a user. The operating member operates key witch units. A combination member(223) is arranged on an upper surface of the operating member. A combination piece(241) covers a side of the operating member at a boundary of the combination member. A controlling member(225) is arranged on the upper side of the combination member. The controlling member includes one or more key tops. The combination piece is combined on the inner wall of a housing unit in a terminal.
摘要翻译：目的：提供便携式终端的键盘组件，以通过将与壳体单元的内壁组合在一起的组合构件延伸到端子中来延伸用于布置键顶的空间。构成：操作构件（221）根据用户的操作而改变。操作构件操作关键的女巫单元。组合构件（223）布置在操作构件的上表面上。组合件（241）在组合构件的边界处覆盖操作构件的一侧。控制构件（225）布置在组合构件的上侧。控制构件包括一个或多个键顶。组合件组合在终端中的壳体单元的内壁上。

6. 发明公开

KR1020090009653A 정전압 방전 보호 회로를 포함하는 반도체 소자 및 그 제조방법 有权
标题翻译：具有静电放电保护电路的半导体器件及其制造方法
公开(公告)号：KR1020090009653A
公开(公告)日：2009-01-23
申请号：KR1020070073115
申请日：2007-07-20
申请人： 삼성전자주식회사
发明人： 박명규 , 김병선 , 이태정 , 방기인
IPC分类号： H01L27/04
CPC分类号： H01L27/0814 , H01L27/0255
摘要： A semiconductor device including a constant voltage discharge protection circuit and a manufacturing method thereof are provided to use a diode pair comprising a junction diode and a schottky diode connected in parallel, thereby protecting an internal circuit and achieving a high speed operation. A semiconductor device(1000A) comprises a first conductive region(210) of a semiconductor substrate(200), a second conductive region(220) contacting with the first conductive region and a metallic type material layer(230) formed on the first conductive region. The first conductive region and the second conductive region provide a junction diode(52). The first conductive region and the metallic type material layer of the semiconductor substrate contact each other and provide a schottky diode(51). The junction diode and the schottky diode are connected to each in parallel. A diode pair(50) is provided. The first conductivity type is N type. The second conductive type is P-type. The second conductive region surrounds at least a part of the first conductive region in a depth direction of the semiconductor substrate, and performs a guard-ring function of the schottky diode.
摘要翻译：提供包括恒压放电保护电路及其制造方法的半导体器件，以使用包括并联连接的结二极管和肖特基二极管的二极管对，从而保护内部电路并实现高速操作。半导体器件（1000A）包括半导体衬底（200）的第一导电区域（210），与第一导电区域接触的第二导电区域（220）和形成在第一导电区域上的金属类型材料层。第一导电区域和第二导电区域提供结二极管（52）。半导体衬底的第一导电区域和金属型材料层彼此接触并提供肖特基二极管（51）。结二极管和肖特基二极管并联连接。提供二极管对（50）。第一种导电类型是N型。第二导电类型是P型。第二导电区域围绕半导体衬底的深度方向上的第一导电区域的至少一部分，并且执行肖特基二极管的保护环功能。

7. 发明公开

KR1020080068220A 반도체 소자 无效
标题翻译：半导体器件
公开(公告)号：KR1020080068220A
公开(公告)日：2008-07-23
申请号：KR1020070005667
申请日：2007-01-18
申请人： 삼성전자주식회사
发明人： 이태정 , 김병선 , 김성환 , 이은영
IPC分类号： H01L21/76 , H01L29/72
CPC分类号： H01L29/0619 , H01L21/76224
摘要： A semiconductor device is provided to relieving electric field in an edge of shallow trench isolation. A semiconductor device includes a first conductivity semiconductor substrate, an active region, a first conductivity guarding-ring region, and a conductive layer pattern(230). The active region has a second conductivity drain region(130) and a second conductivity source region(110) formed in the semiconductor substrate. The first conductivity guarding-ring region is spaced apart from the drain region in order to apply a well bias. The conductive layer pattern is electrically connected to the guarding-ring, and extends from the guarding-ring region to be positioned between the drain region and the guarding-ring region.
摘要翻译：提供半导体器件以减轻浅沟槽隔离边缘中的电场。半导体器件包括第一导电半导体衬底，有源区，第一导电保护环区和导电层图案（230）。有源区具有形成在半导体衬底中的第二导电漏极区（130）和第二导电源区（110）。为了施加阱偏压，第一导电保护环区域与漏极区域间隔开。导电层图案与保护环电连接，并从保护环区域延伸到位于漏区和保护环区之间。

8. 发明授权

KR100660903B1 프로그래밍 속도를 개선한 이이피롬, 이의 제조 방법 및이의 동작 방법 失效
标题翻译： Ipylium具有改进的编程速度，其制造方法和操作方法
公开(公告)号：KR100660903B1
公开(公告)日：2006-12-26
申请号：KR1020050128746
申请日：2005-12-23
申请人： 삼성전자주식회사
发明人： 박근숙 , 김병선 , 이상배 , 황호익 , 박혜영 , 김명희
IPC分类号： H01L27/115 , H01L21/8247

9. 发明公开

KR1020040069823A 듀얼 포트 반도체 메모리 장치 有权
标题翻译：具有双端口的半导体存储器件
公开(公告)号：KR1020040069823A
公开(公告)日：2004-08-06
申请号：KR1020030006365
申请日：2003-01-30
申请人： 삼성전자주식회사
发明人： 이태정 , 김병선 , 이준형
IPC分类号： G11C5/02
CPC分类号： H01L27/1104 , G09G3/3611 , G11C7/02 , G11C8/16 , G11C11/4125 , H01L27/11
摘要： PURPOSE: A semiconductor memory device provided with a dual port is provided to improve the electrical characteristics of the semiconductor memory device by increasing the noise margin in comparison with the semiconductor memory device. CONSTITUTION: A semiconductor memory device provided with a dual port includes a semiconductor substrate provided with a plurality of memory cells, a word line and scan address line, a pair of bitlines and a scan data outline. Each of the memory cells is provided with a first CMOS inverter, a second CMOS inverter, a third NMOS transistor(N3), a fourth NMOS transistor(N4) and a third PMOS transistor(P3). The first CMOS inverter includes a first NMOS transistor(N1), a first PMOS transistor(P1), an input terminal and an output transistor. The second CMOS inverter includes a second NMOS transistor(N2), a second PMOS transistor(P2), an input terminal and an output terminal. The gate of the third NMOS transistor(N3) is connected to the word line, the drain of the third NMOS transistor(N3) is connected to the bitline and the source of the third NMOS transistor(N3) is connected to the second memory node. The gate of the fourth NMOS transistor(N4) is connected to the word line, the drain of the fourth NMOS transistor(N4) is connected to the complementary bitline and the source of the fourth NMOS transistor(N4) is connected to the second memory node. And, the gate of the third PMOS transistor(P3) is connected to the scan address line and the source of the third PMOS transistor(P3) is connected to the second memory node.
摘要翻译：目的：提供一种设置有双端口的半导体存储器件，用于通过增加与半导体存储器件相比的噪声容限来改善半导体存储器件的电特性。构成：设置有双端口的半导体存储器件包括设置有多个存储单元的半导体衬底，字线和扫描地址线，一对位线和扫描数据轮廓。每个存储单元设置有第一CMOS反相器，第二CMOS反相器，第三NMOS晶体管（N3），第四NMOS晶体管（N4）和第三PMOS晶体管（P3）。第一CMOS反相器包括第一NMOS晶体管（N1），第一PMOS晶体管（P1），输入端子和输出晶体管。第二CMOS反相器包括第二NMOS晶体管（N2），第二PMOS晶体管（P2），输入端子和输出端子。第三NMOS晶体管（N3）的栅极连接到字线，第三NMOS晶体管（N3）的漏极连接到位线，并且第三NMOS晶体管（N3）的源极连接到第二存储器节点。第四NMOS晶体管（N4）的栅极连接到字线，第四NMOS晶体管（N4）的漏极连接到互补位线，并且第四NMOS晶体管（N4）的源极连接到第二存储器节点。并且，第三PMOS晶体管（P3）的栅极连接到扫描地址线，并且第三PMOS晶体管（P3）的源极连接到第二存储器节点。

10. 发明授权

KR100389929B1 트렌치 소자분리막을 구비하는 ＳＯＩ 소자 및 그 제조 방법 有权
标题翻译： 렌SO SO SO SO SO SO SO SOI소자및그제조방
公开(公告)号：KR100389929B1
公开(公告)日：2003-07-04
申请号：KR1020010045693
申请日：2001-07-28
申请人： 삼성전자주식회사
发明人： 이태정 , 김병선 , 오명환 , 유승한 , 신명선 , 박상욱
IPC分类号： H01L21/76
CPC分类号： H01L29/66772 , H01L21/76264 , H01L21/76283 , H01L29/78615 , H01L29/78636
摘要： An isolation layer (170) that is formed in a trench has an oxide liner and a nitride liner that are sequentially formed along surface of trench and dielectric layer that fills the trench. The trench has gate and drain/source regions having thickness less than or equal to that of a semiconductor layer. An independent claim is included for semiconductor device manufacturing method.
摘要翻译：在沟槽中形成的隔离层（170）具有氧化物衬垫和氮化物衬垫，其沿着填充沟槽的沟槽和介电层的表面顺序地形成。沟槽具有厚度小于或等于半导体层的栅极和漏极/源极区域。包括半导体器件制造方法的独立权利要求。

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