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1. 发明授权

KR102067173B1 적층 세라믹 커패시터 및 그 제조 방법 有权
公开(公告)号：KR102067173B1
公开(公告)日：2020-01-15
申请号：KR1020130019959
申请日：2013-02-25
申请人： 삼성전기주식회사
发明人： 이종호 , 김응수 , 최재열 , 김두영 , 김유나 , 김성우
IPC分类号： H01G4/12 , H01G4/30

2. 发明授权

KR101771724B1 적층 세라믹 전자부품 및 이의 제조방법 有权
标题翻译：多层陶瓷电子部件及其制造方法
公开(公告)号：KR101771724B1
公开(公告)日：2017-08-25
申请号：KR1020120040389
申请日：2012-04-18
申请人： 삼성전기주식회사
发明人： 이진우 , 김태형 , 김응수 , 노치현 , 조항규
IPC分类号： H01G4/12 , H01G4/30
CPC分类号： H01G4/30 , H01G4/0085 , H01G4/012 , H01G4/12 , Y10T29/435
摘要： 본발명은적층세라믹전자부품에관한것으로, 본발명은유전체층을포함하는세라믹본체; 및상기세라믹본체내에서상기유전체층을사이에두고서로대향하도록배치되는제1 및제2 내부전극;을포함하며, 상기제1 및제2 내부전극의중심선평균거칠기를 Ra라할 때, 상기 Ra에대응하는가상선으로부터그 하부에형성된피트(d)까지의최대거리가 0.1 μm 내지 13 μm을만족하는적층세라믹전자부품을제공하며, 본발명에따르면, 내부전극인쇄면의표면조도를개선하여쇼트발생불량을개선하는효과가있다.
摘要翻译：多层陶瓷电子元件技术领域本发明涉及一种多层陶瓷电子元件，并且更具体地涉及一种多层陶瓷电子元件，其包括具有介电层和布置成把彼此相对的电介质层之间的陶瓷主体内的第一mitje第二内部电极;商船不响应并且包括第一mitje中心线平均粗糙度在Ra中的第二内部电极的，当R a拉哈勒从提供满足英尺到的距离的多层陶瓷电子器件为0.1μm至形成在下部，根据本发明为13μmkkajiui（d），通过改善电极打印面的表面粗糙度，以提高发生短路不良这是有效的。

3. 发明公开

KR1020140058841A 적층 세라믹 커패시터 有权
标题翻译：多层陶瓷电容器
公开(公告)号：KR1020140058841A
公开(公告)日：2014-05-15
申请号：KR1020120125174
申请日：2012-11-07
申请人： 삼성전기주식회사
发明人： 이종호 , 최재열 , 김두영 , 조항규 , 김응수 , 한병우
IPC分类号： H01G4/12 , H01G4/30
CPC分类号： H01G2/103 , H01G4/012 , H01G4/12 , H01G4/232 , H01G4/30 , H01L41/0472 , H01L41/0533
摘要： A multilayer ceramic electronic component according to one aspect of the present invention includes a ceramic body including a dielectric layer; an oxide layer formed on the ceramic body; first and second external electrodes formed at both sides of the oxide layer on one surface of the ceramic body; a first internal electrode including a first electrode withdrawing part formed on the dielectric layer and exposed to the first external electrode, and a first insulating withdrawing part exposed to the oxide layer and having a complex metallic oxide region formed in an exposed end; and a second internal electrode including a second electrode withdrawing part exposed to the second external electrode and a second insulating withdrawing part exposed to the oxide layer, having a complex metallic oxide region formed in an exposed end, and being superposed with the first insulating withdrawing part to form an additional capacity, wherein the second internal electrode oppositely faces the first internal electrode across the dielectric layer.
摘要翻译：根据本发明的一个方面的多层陶瓷电子部件包括：陶瓷体，包括电介质层; 形成在所述陶瓷体上的氧化物层; 形成在陶瓷体的一个表面上的氧化物层的两侧的第一和第二外部电极; 第一内部电极，包括形成在所述电介质层上并暴露于所述第一外部电极的第一电极取出部和暴露于所述氧化物层并且具有形成在暴露端的复合金属氧化物区域的第一绝缘退避部; 以及第二内部电极，其包括暴露于所述第二外部电极的第二电极取出部和暴露于所述氧化物层的第二绝缘退避部，具有形成在露出端部的复合金属氧化物区域，并且与所述第一绝缘引出部以形成额外的容量，其中第二内部电极跨过电介质层相对地面向第一内部电极。

4. 发明公开

KR1020140050210A 적층 세라믹 전자 부품 无效
标题翻译：多层陶瓷电子元件
公开(公告)号：KR1020140050210A
公开(公告)日：2014-04-29
申请号：KR1020120116170
申请日：2012-10-18
申请人： 삼성전기주식회사
发明人： 김종한 , 최재열 , 김응수 , 이승호 , 이종호 , 김두영
IPC分类号： H01G4/12 , H01G4/30
摘要： The present invention provides a multilayered ceramic electronic component which includes: a ceramic element on which a plurality of dielectric layers are laminated; a plurality of first and second internal electrodes which are formed on at least one side of the dielectric layer and are alternatively exposed through both cross sections of the ceramic element in the lamination direction of the dielectric layer; at least one first slit part and at least one second slit part which are formed on the first and second internal electrodes to be drawn through at least one side of the first and second internal electrodes and become de-binder paths. The overlap area of the first and second internal electrodes is 80-98% of the total area of the dielectric layer when the dielectric layer is laminated.
摘要翻译：本发明提供一种多层陶瓷电子部件，其包括：层叠有多个电介质层的陶瓷元件; 多个第一和第二内部电极，其形成在所述电介质层的至少一侧上，并且在所述电介质层的层叠方向上交替地暴露于所述陶瓷元件的两个横截面; 至少一个第一狭缝部分和至少一个第二狭缝部分，其形成在所述第一和第二内部电极上，以被拉伸通过所述第一和第二内部电极的至少一个侧面并且变成脱粘合剂路径。当层压电介质层时，第一和第二内部电极的重叠面积为电介质层总面积的80-98％。

5. 发明公开

KR1020140030665A 적층형 세라믹 커패시터 및 그 제조방법 无效
标题翻译：多层陶瓷电容器及其制造方法
公开(公告)号：KR1020140030665A
公开(公告)日：2014-03-12
申请号：KR1020120097118
申请日：2012-09-03
申请人： 삼성전기주식회사
发明人： 김태형 , 노치현 , 김응수 , 홍용민 , 김기룡 , 정진만 , 김성애
IPC分类号： H01G4/12 , H01G4/30
摘要： The present invention relates to a multi-layered ceramic capacitor and a manufacturing method thereof. The multi-layered ceramic capacitor according to the present invention comprises: ceramic green sheets laminated in multiple layers to form a capacitor body; and internal electrodes formed on surfaces of the ceramic green sheets to have small base angles with the surfaces by printing and electrically connected to external electrodes. According to the present invention, since the internal electrodes are formed in a small base angled structure, empty spaces formed by the laminated green sheets and the internal electrodes can be reduced in comparison with a conventional big base angled structure, thereby reducing defects such as delamination or cracks of the green sheets during post processes.
摘要翻译：多层陶瓷电容器及其制造方法技术领域本发明涉及一种多层陶瓷电容器及其制造方法。根据本发明的多层陶瓷电容器包括：层叠多层的陶瓷生片以形成电容器本体; 以及形成在陶瓷生片的表面上的内部电极，通过印刷和与外部电极电连接而与表面具有小的底角。根据本发明，由于内部电极形成为小的底部倾斜结构，所以与传统的大的底座成角度的结构相比，可以减少由层压的生片和内部电极形成的空间，从而减少诸如分层或在后期处理中的生片的裂纹。

6. 发明公开

KR1020130125106A 적층 세라믹 부품 有权
标题翻译：多层陶瓷元件
公开(公告)号：KR1020130125106A
公开(公告)日：2013-11-18
申请号：KR1020120048609
申请日：2012-05-08
申请人： 삼성전기주식회사
发明人： 이승호 , 김종한 , 김응수
IPC分类号： H01G4/12 , H01G4/30
CPC分类号： H01G4/30 , H01G4/0085 , H01G4/12
摘要： Disclosed is a multi-layered ceramic element having a structure in which an inner electrode layer and a dielectric layer are alternately multi-layered, wherein the inner electrode layer includes 3 to 12 wt% of an inhibitor compared with the weight of metal powder, and an average particle size of the inhibitor is less than 30% of an average particle size of a dielectric base metal. According to the embodiment of the present invention, it is possible to manufacture a multi-layered ceramic element with excellent reliability by increasing the capacity of the multi-layered ceramic element by controlling the particle size and added quantity of the inhibitor included in the inner electrode layer which is squeezed out during burning at high temperature.
摘要翻译：公开了具有内电极层和电介质层交替多层结构的多层陶瓷元件，其中内电极层与金属粉末的重量相比包含3〜12重量％的抑制剂，以及抑制剂的平均粒径小于电介质贱金属的平均粒径的30％。根据本发明的实施方式，可以通过控制包含在内部电极中的抑制剂的粒径和添加量来增加多层陶瓷元件的容量来制造具有优异的可靠性的多层陶瓷元件在高温燃烧过程中被挤出的层。

7. 发明公开

KR1020130117292A 적층 세라믹 전자부품 및 이의 제조방법 有权
标题翻译：层压陶瓷电子部件及其制造方法
公开(公告)号：KR1020130117292A
公开(公告)日：2013-10-25
申请号：KR1020120040389
申请日：2012-04-18
申请人： 삼성전기주식회사
发明人： 이진우 , 김태형 , 김응수 , 노치현 , 조항규
IPC分类号： H01G4/12 , H01G4/30
CPC分类号： H01G4/30 , H01G4/0085 , H01G4/012 , H01G4/12 , Y10T29/435
摘要： PURPOSE: A laminated ceramic electronic component and a manufacturing method thereof reduce short defects by improving the surface illuminance of a printed surface of an internal electrode. CONSTITUTION: A ceramic main body includes a dielectric layer (1). A first internal electrode (21) and a second internal electrode (22) face each other across the dielectric layer. The maximum distance from a virtual line corresponding to the average roughness (Ra) of a central line of the first and second internal electrodes to a pit is 0.1 to 13 μm. The average thickness (td) of the dielectric layer is 2.0 μm or less. The average thickness (te) of the first and second internal electrodes is 2.0 μm or less.
摘要翻译：目的：一种层叠陶瓷电子部件及其制造方法，其通过提高内部电极的印刷面的表面照度来减少短缺陷。构成：陶瓷主体包括电介质层（1）。第一内部电极（21）和第二内部电极（22）跨过电介质层彼此面对。从与第一和第二内部电极的中心线到凹坑的平均粗糙度（Ra）对应的虚拟线的最大距离为0.1〜13μm。电介质层的平均厚度（td）为2.0μm以下。第一和第二内部电极的平均厚度（te）为2.0μm以下。

8. 发明授权

KR100455892B1 빌드업 인쇄회로기판 및 이의 제조방법 失效
标题翻译： 빌드업인쇄회로기판및이의제조방법
公开(公告)号：KR100455892B1
公开(公告)日：2004-11-06
申请号：KR1020020087417
申请日：2002-12-30
申请人： 삼성전기주식회사
发明人： 송창규 , 류창섭 , 이존태 , 김응수
IPC分类号： H05K3/46
摘要： PURPOSE: A build-up printed circuit board and a method for manufacturing the same are provided to achieve improved connection between layers by forming a conductor layer through the use of a stacking press. CONSTITUTION: A method for manufacturing a build-up printed circuit board, comprises a step of forming an insulation resin layer by depositing a photosensitive insulation resin(4) on a core substrate where via holes and a first circuit pattern are formed; a step of solidifying the insulation resin layer by using a photomask; a step of forming a photovia(7) on the first circuit pattern by developing the solidified photosensitive insulation resin layer; a step of filling a conductive paste(9) into the portion where the photovia is formed; a step of forming a conductor layer by pressing a copper foil(11) on the substrate filled with the conductive paste; a step of forming a photoresist pattern on the substrate; a step of forming a second circuit pattern by etching the conductor layer; and a step of removing the photoresist pattern.
摘要翻译：目的：提供一种积层印刷电路板及其制造方法，以通过使用堆叠压机形成导体层来实现层间连接的改进。用于制造积层印刷电路板的方法包括以下步骤：通过在形成有通孔和第一电路图案的核心基板上沉积光敏绝缘树脂（4）来形成绝缘树脂层; 使用光掩模使绝缘树脂层固化的工序; 通过对固化的光敏绝缘树脂层进行显影而在第一电路图案上形成光电层（7）的步骤; 将导电膏（9）填充到形成有所述太阳能电池的部分中的步骤; 通过在填充有导电糊的基板上压制铜箔（11）来形成导体层的步骤; 在衬底上形成光致抗蚀剂图案的步骤; 通过蚀刻导体层形成第二电路图案的步骤; 以及去除光刻胶图案的步骤。

9. 发明授权

KR101771737B1 적층 세라믹 전자부품 및 이의 제조방법 有权
标题翻译：多层陶瓷电子部件及其制造方法
公开(公告)号：KR101771737B1
公开(公告)日：2017-08-25
申请号：KR1020120110781
申请日：2012-10-05
申请人： 삼성전기주식회사
发明人： 김유나 , 김두영 , 이종호 , 최재열 , 김응수 , 김성우
IPC分类号： H01G4/12 , H01G4/30
摘要： 본발명은신뢰성이우수한대용량적층세라믹전자부품및 이의제조방법에관한것으로, 구체적으로는 L 마진부단차를개선하고외부전극의도포를일정하게하여외부전극의치수정밀도를개선할수 있는적층세라믹전자부품및 이의제조방법에한 것이다. 본발명에따르면그린데라미네이션및 크랙을억제시킬뿐만아니라신뢰성이우수한대용량적층세라믹전자부품을구현할수 있다.
摘要翻译：本发明已经可靠的大容量多层陶瓷电子器件及其制造方法，特别是为了改进将L余量不间断汽车和堆叠可以由陶瓷电子部件的外部电极的恒定应用提高外部电极的尺寸精度及其制造方法。根据本发明，仅抑制绿色层压和开裂，而且还可以实现高容量的多层陶瓷电子器件的可靠性。

10. 发明授权

KR101761945B1 적층 커패시터 有权
标题翻译：层压电容器
公开(公告)号：KR101761945B1
公开(公告)日：2017-07-26
申请号：KR1020120118460
申请日：2012-10-24
申请人： 삼성전기주식회사
发明人： 김태형 , 김응수 , 노치현
IPC分类号： H01G4/12 , H01G4/30
摘要： 본발명은적층커패시터에관한것으로, 적층누적에의한응력을완화하기위하여, 제1 내부전극이인쇄된세라믹시트및 제2 내부전극이인쇄된세라믹시트가교대로복수개 적층되어이루어진세라믹본체와, 상기세라믹본체의양 측부에구비된한 쌍의외부단자로구성된적층커패시터에있어서, 상기세라믹시트의상측선과상기제1 내부전극의상측선사이의간격(W1)은상기세라믹시트의상측선과상기제2 내부전극의상측선사이의간격(W2)과다르고, 상기세라믹시트의하측선과상기제1 내부전극의하측선사이의간격(W3)은상기세라믹시트의하측선과상기제2 내부전극의하측선사이의간격(W4)과다른적층커패시터를제시한다.
摘要翻译：本发明涉及一种层叠电容器，以将应力松弛由于层叠，层叠时，第一内部电极是多个层叠的陶瓷片和第二内部电极是由陶瓷体的陶瓷片的交联印刷，该陶瓷并且，在主体的两侧部设置有一对外部端子，陶瓷片外轮廓线与第一内部电极轮廓线（W1）之间的间隙（W1）过载的横向线（W2），之间的距离，其中，所述第一内部电极的（W3）之间的较低的运输间隔第二内部电极对另一eunsanggi陶瓷片（W4）的下端线之间较低的运输间隔的陶瓷片的下部线展示了一个叠层电容器。

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