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    • 3. 发明专利
    • Metal-oxide-semiconductor device including buried lightly-doped drain region
    • 金属氧化物半导体器件,包括埋入式轻型漏水区域
    • JP2013225685A
    • 2013-10-31
    • JP2013123280
    • 2013-06-12
    • Agere Systems Incアギア システムズ インコーポレーテッド
    • MUHAMMED AIMAN SHIBIBXU SHUMING
    • H01L21/336H01L29/78H01L23/58H01L29/06H01L29/08H01L29/40H01L29/417H01L29/76H01L31/062
    • H01L29/402H01L29/0615H01L29/0847H01L29/4175H01L29/66659H01L29/7835
    • PROBLEM TO BE SOLVED: To reduce the on-resistance of a MOS device without significantly increasing HCD and/or the gate-to-drain capacitance, thereby improving high-frequency performance and reliability.SOLUTION: A MOS device comprises: a semiconductor layer 204 of a first conductivity type; a source region 206 of a second conductivity type formed in the semiconductor layer; and a drain region 208 of the second conductivity type formed in the semiconductor layer and separated from the source region. A gate 210 is formed in the vicinity of an upper surface of the semiconductor layer and at least partially between the source region and the drain region. The MOS device further includes a buried LDD region 216 of the second conductivity type formed in the semiconductor layer between the gate region and the drain region. The buried LDD region is separated laterally from the drain region, and a second LDD region 214 of the first conductivity type is formed in the buried LDD region in the vicinity of the upper surface of the semiconductor layer. The second LDD region is self-aligned with the gate and separated laterally from the gate such that the gate does not overlap with the second LDD region.
    • 要解决的问题:为了降低MOS器件的导通电阻而不显着增加HCD和/或栅极至漏极电容,从而提高高频性能和可靠性。解决方案:MOS器件包括:半导体层204 的第一导电类型; 形成在半导体层中的第二导电类型的源极区206; 以及形成在半导体层中并与源极区分离的第二导电类型的漏极区域208。 栅极210形成在半导体层的上表面附近,并且至少部分地形成在源极区域和漏极区域之间。 MOS器件还包括形成在栅极区域和漏极区域之间的半导体层中的第二导电类型的埋入LDD区域216。 埋入的LDD区域从漏极区域侧向分离,并且在半导体层的上表面附近的掩埋LDD区域中形成第一导电类型的第二LDD区域214。 第二LDD区域与栅极自对准并且从栅极横向分离,使得栅极不与第二LDD区域重叠。