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1. 发明专利

JP6164604B2 半導体装置有权
公开(公告)号：JP6164604B2
公开(公告)日：2017-07-19
申请号：JP2013043406
申请日：2013-03-05
申请人：ローム株式会社
发明人：中野佑紀 , 中村亮太
IPC分类号： H01L29/06 , H01L29/12 , H01L29/49 , H01L29/423 , H01L29/78
CPC分类号： H01L29/063 , H01L29/0619 , H01L29/0657 , H01L29/0661 , H01L29/0696 , H01L29/1602 , H01L29/1608 , H01L29/2003 , H01L29/36 , H01L29/407 , H01L29/41741 , H01L29/4236 , H01L29/4238 , H01L29/4925 , H01L29/511 , H01L29/517 , H01L29/518 , H01L29/7811 , H01L29/7813 , H01L29/7825 , H01L29/0649 , H01L29/1095 , H01L29/41766 , H01L29/42372 , H01L29/42376

2. 发明专利

JP2016092338A トレンチゲート構造を備えた半導体装置およびその製造方法有权
标题翻译：具有闸门结构及其制造方法的半导体器件
公开(公告)号：JP2016092338A
公开(公告)日：2016-05-23
申请号：JP2014228459
申请日：2014-11-10
申请人：ローム株式会社
发明人：奥田肇 , 濱澤靖史
IPC分类号： H01L21/76 , H01L21/336 , H01L27/088 , H01L21/8234 , H01L27/08 , H01L21/8238 , H01L27/092 , H01L29/423 , H01L29/49 , H01L29/417 , H01L29/788 , H01L29/792 , H01L21/8247 , H01L27/115 , H01L27/10 , H01L29/78
CPC分类号： H01L29/7813 , H01L21/823878 , H01L27/092 , H01L27/0922 , H01L29/0653 , H01L29/0696 , H01L29/0865 , H01L29/0882 , H01L29/407 , H01L29/41766 , H01L29/42368 , H01L29/4925 , H01L29/66734 , H01L29/1095 , H01L29/456
摘要：【課題】トレンチゲート構造における温度上昇を抑制でき、優れた信頼性を有する半導体装置およびその製造方法を提供すること。複雑な構造を回避でき、低抵抗化を図ることができる半導体装置およびその製造方法を提供すること。【解決手段】ゲートトレンチ14が形成されたエピタキシャル層12と、ゲートトレンチ14の内面に沿って形成されたゲート絶縁膜20と、ゲート絶縁膜20を介してゲートトレンチ14に埋設され、中間絶縁膜24を挟んで上下に分離された下部電極層26および上部電極層30を有するゲート電極25と、上部電極層30および中間絶縁膜24を貫通して、下部電極層26に至るようにゲートトレンチ14内に形成され、下部電極層26と上部電極層30とを電気的に接続するゲートコンタクト43とを含む、半導体装置1を形成する。【選択図】図4
摘要翻译：要解决的问题：提供一种可以抑制沟槽栅极结构中的温度升高并且具有优异的可靠性并提供半导体器件的制造方法的半导体器件; 并提供能够避免复杂结构并实现低电阻并提供半导体器件的制造方法的半导体器件。解决方案：半导体器件1包括：形成栅极沟槽14的外延层12; 沿栅极沟槽14的内表面形成的栅极绝缘膜20; 具有下电极层26和上电极层30的栅极25，其经由栅极绝缘膜20嵌入栅极沟槽14，并在垂直方向上跨越中间绝缘膜24分离; 以及形成在栅沟槽14中以刺穿上电极层30和中间绝缘膜24以到达下电极层26的栅极接触43，用于电连接下电极层26和上电极层30。图4

3. 发明专利

JP2016058601A 半導体装置审中-公开
标题翻译：半导体器件
公开(公告)号：JP2016058601A
公开(公告)日：2016-04-21
申请号：JP2014184893
申请日：2014-09-11
申请人：株式会社東芝
发明人：鈴木正道 , 東悠介 , 高石理一郎 , 富田充裕 , 佐久間究 , 三谷祐一郎
IPC分类号： H01L27/115 , H01L27/10 , H01L21/336 , H01L29/788 , H01L29/792 , H01L21/8234 , H01L27/088 , H01L21/8247
CPC分类号： H01L29/4925 , H01L21/28273 , H01L27/11541 , H01L29/42324 , H01L29/7885 , H01L23/485 , H01L2924/0002
摘要：【課題】水素の拡散に伴う信頼性の劣化を、僅かな工程の追加により、しかも装置の大型化を招くことなく効果的に抑制する半導体装置を提供する。【解決手段】フラッシュメモリセルトランジスタと周辺トランジスタとが混載された半導体装置において、チャネル層の表面上に形成されたゲート絶縁膜14a,14bと、ゲート絶縁膜14a,14bの上面に形成されたゲート電極15a,15bと、チャネル層に形成された拡散層12a,12bとを備える。更にこの半導体装置は、ゲート電極15a,15b及び拡散層12a,12bの表面を覆うように形成された多結晶シリコン膜22と、ゲート電極15a,15b及び多結晶シリコン膜22を覆うように形成された層間絶縁膜23とを備える。【選択図】図1
摘要翻译：要解决的问题：提供一种半导体器件，其通过一点额外的工艺有效地抑制与氢扩散相关的可靠性劣化，而不会导致器件尺寸的增加。解决方案：一种其中闪存单元晶体管和外围晶体管被合并的半导体器件包括：形成在沟道层的表面上的栅极绝缘膜14a，14b; 分别形成在栅极绝缘膜14a，14b的顶面上的栅电极15a，15b; 以及形成在沟道层中的扩散层12a，12b。半导体器件还包括：形成为覆盖栅电极15a，15b和扩散层12a，12b的表面的多晶硅膜22; 以及形成为覆盖栅电极15a，15b和多晶硅膜22的层间绝缘膜23.图示

4. 发明专利

JP5467616B2 A method of forming a stacked trench contact 有权
公开(公告)号：JP5467616B2
公开(公告)日：2014-04-09
申请号：JP2011509802
申请日：2009-06-26
申请人：インテル・コーポレーション
发明人：セル、バーンハード , ゴロンズカ、オレグ
IPC分类号： H01L21/768 , H01L21/28 , H01L23/522
CPC分类号： H01L23/535 , H01L21/28052 , H01L21/28123 , H01L21/76805 , H01L21/76889 , H01L21/76895 , H01L21/76897 , H01L21/823425 , H01L21/823468 , H01L21/823475 , H01L23/485 , H01L23/5226 , H01L23/528 , H01L23/53257 , H01L23/53266 , H01L27/088 , H01L29/0847 , H01L29/4175 , H01L29/4925 , H01L29/66666 , H01L29/7827 , H01L2924/0002 , H01L2924/00
摘要： Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a structure comprising a first contact metal disposed on a source/drain contact of a substrate, and a second contact metal disposed on a top surface of the first contact metal, wherein the second contact metal is disposed within an IID disposed on a top surface of a metal gate disposed on the substrate.

5. 发明专利

JP2014060286A Semiconductor device and manufacturing method of the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2014060286A
公开(公告)日：2014-04-03
申请号：JP2012204838
申请日：2012-09-18
申请人： Renesas Electronics Corp , ルネサスエレクトロニクス株式会社
发明人： YAMAMOTO KENICHI , SASAKI HIROMI , MORITA TOMOTAKE , MORIKAZU MASASHIGE
IPC分类号： H01L21/28 , H01L21/336 , H01L21/768 , H01L21/8234 , H01L23/522 , H01L27/088 , H01L29/417 , H01L29/78
CPC分类号： H01L29/7848 , H01L21/02164 , H01L21/0217 , H01L21/26513 , H01L21/266 , H01L21/28035 , H01L21/283 , H01L21/31111 , H01L21/823418 , H01L21/823425 , H01L21/823468 , H01L21/823814 , H01L27/088 , H01L29/0847 , H01L29/161 , H01L29/165 , H01L29/41783 , H01L29/4925 , H01L29/66477 , H01L29/665 , H01L29/66568 , H01L29/66575 , H01L29/66628 , H01L29/78 , H01L29/7834
摘要： PROBLEM TO BE SOLVED: To improve performance of a semiconductor device.SOLUTION: A semiconductor device comprises: a gate electrode GE formed on a semiconductor substrate SUB via an insulation film GI for a gate insulation film; an insulation film IL1 extending from on a side wall of the gate electrode GE toward on the semiconductor substrate SUB; and a semiconductor layer EP1 as an epitaxial layer for a source/drain formed on the semiconductor substrate SUB at a part exposed from the insulation film IL1. The insulation film IL1 includes a part extending on a side wall of the gate electrode GE and a part extending on the semiconductor substrate SUB. A part of the semiconductor layer EP1 lies on the insulation film IL1 at the part extending on the semiconductor substrate SUB.
摘要翻译：要解决的问题：提高半导体器件的性能。解决方案：半导体器件包括：通过栅极绝缘膜的绝缘膜GI形成在半导体衬底SUB上的栅电极GE; 从栅电极GE的侧壁朝向半导体基板SUB延伸的绝缘膜IL1; 以及半导体层EP1作为在绝缘膜IL1露出的部分处形成在半导体衬底SUB上的用于源极/漏极的外延层。绝缘膜IL1包括在栅电极GE的侧壁上延伸的部分和在半导体衬底SUB上延伸的部分。半导体层EP1的一部分位于在半导体衬底SUB上延伸的部分处的绝缘膜IL1上。

6. 发明专利

JP2013191808A Semiconductor device and method for manufacturing semiconductor device 审中-公开
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：JP2013191808A
公开(公告)日：2013-09-26
申请号：JP2012058781
申请日：2012-03-15
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： FUJIMOTO HIROYUKI
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L29/4925 , H01L27/10829 , H01L27/10885 , H01L27/10888
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which includes an embedded gate transistor for a memory cell and a peripheral transistor, while a bit line on the memory cell and a gate electrode of the peripheral transistor are easy to be processed.SOLUTION: An embedded gate transistor includes a first interlayer insulating film and a second conductor film constituting a bit line stacked on the first interlayer insulating film. In a peripheral transistor region, a gate insulating film and a gate electrode laminate formed on the gate insulating film are provided. On the gate electrode laminate, at least a metal gate film, an upper gate film, and a third conductor film whose material and thickness are identical with the second conductor film are stacked. The height from the semiconductor substrate to an upper surface of the metal gate film is shorter than that from the semiconductor substrate to an upper surface of the first interlayer insulating film. A height of an upper surface of the upper gate film is equal to or less than that of an upper surface of the first interlayer insulating film.
摘要翻译：要解决的问题：提供一种半导体器件，其包括用于存储单元的嵌入式栅极晶体管和外围晶体管，而存储单元上的位线和外围晶体管的栅电极易于被处理。解决方案：嵌入式栅极晶体管包括构成层叠在第一层间绝缘膜上的位线的第一层间绝缘膜和第二导体膜。在外围晶体管区域中，设置形成在栅极绝缘膜上的栅极绝缘膜和栅极电极层叠体。在栅极电极层叠体上，至少形成材料和厚度与第二导体膜相同的金属栅极膜，上部栅极膜和第三导体膜。从半导体基板到金属栅极膜的上表面的高度比从半导体基板到第一层间绝缘膜的上表面的高度短。上栅极膜的上表面的高度等于或小于第一层间绝缘膜的上表面的高度。

7. 发明专利

JP2012151498A Power semiconductor device 审中-公开
标题翻译：功率半导体器件
公开(公告)号：JP2012151498A
公开(公告)日：2012-08-09
申请号：JP2012071019
申请日：2012-03-27
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： OTSUKA KENICHI , MIURA NARIHISA , IMAIZUMI MASAYUKI , OMORI TATSUO
IPC分类号： H01L29/78 , H01L21/28 , H01L21/336 , H01L29/12
CPC分类号： H01L29/7802 , H01L29/0878 , H01L29/1095 , H01L29/1608 , H01L29/45 , H01L29/4925 , H01L29/4941 , H01L29/66068 , H01L29/7828
摘要： PROBLEM TO BE SOLVED: To provide a power semiconductor device in which the reaction between a metallic material of wiring and an electrode connected to a semiconductor region hardly occurs in high-temperature operation, and strain hardly occurs in the high-temperature operation.SOLUTION: A first metal layer 14 is formed above and on a gate electrode 9 and a source electrode 11, and contains at least one of Pt, Ti, Mo, W, and Ta. A second metal layer 15 is formed on the first metal layer 14, and contains at least one of Mo, W, and Cu. An interlayer insulating film 10 is formed in a region other than the region in which the source electrode 11 is formed, that is, in a region on surfaces of a p-type SiC region 13 and the gate insulating film 8 or the gate electrode 9. The first metal layer 14 and the second metal layer 15 extend on the interlayer insulating film 10.
摘要翻译：要解决的问题：提供一种功率半导体器件，其中在高温操作中几乎不发生布线的金属材料与连接到半导体区域的电极之间的反应，并且在高温操作中几乎不发生应变。解决方案：第一金属层14形成在栅电极9和源电极11的上方，栅极电极11上，并且包含Pt，Ti，Mo，W和Ta中的至少一种。在第一金属层14上形成第二金属层15，并且包含Mo，W和Cu中的至少一种。层间绝缘膜10形成在除了形成源电极11的区域以外的区域，即在p型SiC区域13和栅极绝缘膜8或栅电极9的表面上的区域中第一金属层14和第二金属层15在层间绝缘膜10上延伸。版权所有（C）2012，JPO＆INPIT

8. 发明专利

JP4945055B2 Semiconductor device and a method of manufacturing the same 有权
公开(公告)号：JP4945055B2
公开(公告)日：2012-06-06
申请号：JP2003286142
申请日：2003-08-04
申请人：ルネサスエレクトロニクス株式会社
发明人：芳人中沢 , 正樹白石
IPC分类号： H01L29/78 , H01L21/265 , H01L21/336 , H01L29/08 , H01L29/10 , H01L29/423 , H01L29/45 , H01L29/49
CPC分类号： H01L29/7813 , H01L21/26586 , H01L24/05 , H01L29/0878 , H01L29/1095 , H01L29/41766 , H01L29/4236 , H01L29/4238 , H01L29/456 , H01L29/4925 , H01L29/4933 , H01L29/66727 , H01L29/66734 , H01L29/7811 , H01L2224/05552 , H01L2224/0603 , H01L2924/1305 , H01L2924/1306 , H01L2924/13062 , H01L2924/13091 , H01L2924/00
摘要： A technology is provided to reduce ON-resistance, and the prevention of punch through is achieved with respect to a trench gate type power MISFET. Input capacitance and a feedback capacitance are reduced by forming a groove in which a gate electrode is formed so as to have a depth as shallow as about 1 μm or less, a p−type semiconductor region is formed to a depth so as not to cover the bottom of the groove, and a p-type semiconductor region higher in impurity concentration than the p−type semiconductor region is formed under a n+type semiconductor region serving as a source region of the trench gate type power MISFET, causing the p-type semiconductor region to serve as a punch-through stopper layer of the trench gate type power MISFET.

9. 发明专利

JP4818903B2 Trench Power mosfet having a gate bus flattened 有权
公开(公告)号：JP4818903B2
公开(公告)日：2011-11-16
申请号：JP2006501216
申请日：2004-03-04
申请人：アドバンスト・アナロジック・テクノロジーズ(ホンコン)・リミテッドAdvanced Analogic Technologies (Hong Kong) Limited , アドバンスト・アナロジック・テクノロジーズ・インコーポレイテッドAdvanced Analogic Technologies, Inc.
发明人：ウィリアムズ、リチャード・ケイ , コーネル、マイケル・イー , チャン、ワイ・シェン
IPC分类号： H01L29/78 , H01L21/336 , H01L21/76 , H01L29/423 , H01L29/45 , H01L29/49
CPC分类号： H01L29/66734 , H01L29/1095 , H01L29/4236 , H01L29/42368 , H01L29/456 , H01L29/4925 , H01L29/4933 , H01L29/4941 , H01L29/7813
摘要： Power MOSFET's and fabrication processes for power MOSFET's use a continuous conductive gate structure within trenches to avoid device topology problems caused when a gate bus extends above a substrate. The conductive gate structure forms trench gates in an active device region and forms a gate bus in a gate bus trench. The gate bus trench connects to device trenches and can be wide to facilitate forming a contact to the gate bus. The device trenches can be narrow to maximize device density. The gate bus and/or gates contain a metal/silicide to reduce resistance, and polysilicon surrounds the metal/silicide to prevent metal atoms from penetrating the gate oxide layers. A CMP process can planarize the conductive gate structure and/or overlying insulating layers. The processes are compatible with forming self-aligned or conventional contacts in the active device region.

10. 发明专利

JP2011210999A Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2011210999A
公开(公告)日：2011-10-20
申请号：JP2010077993
申请日：2010-03-30
申请人： Renesas Electronics Corp , ルネサスエレクトロニクス株式会社
发明人： CHO SHIEN
IPC分类号： H01L29/78 , H01L21/283 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L21/28247 , H01L21/28282 , H01L29/4925 , H01L29/78 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To suppress deterioration of a gate insulation film by preventing hydrogen from diffusing into a gate electrode, thereby providing a highly reliable semiconductor device.SOLUTION: A semiconductor device 10 includes a gate electrode 14 that contains polysilicon, and a hydrogen storage layer that covers at least a top surface of the gate electrode and has a function of storing hydrogen. Favorably, the barrier layer includes an oxynitride film having a composition formula of SiNO, wherein the ratio of x:y:z is 1:1:0.1-0.7.
摘要翻译：要解决的问题：通过防止氢扩散到栅极电极中来抑制栅极绝缘膜的劣化，从而提供高度可靠的半导体器件。解决方案：半导体器件10包括含有多晶硅的栅极14和氢存储层，其覆盖栅电极的至少顶表面，并具有储存氢的功能。有利地，阻挡层包括组成式为SiNO的氧氮化物膜，其中x:y:z的比例为1:1:0.1-0.7。

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