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1. 发明专利

JP4109830B2 Electrostatically controlled by tunneling transistor 有权
公开(公告)号：JP4109830B2
公开(公告)日：2008-07-02
申请号：JP2000614517
申请日：2000-04-21
申请人：エイコーン・テクノロジイズ・インコーポレーテッド
发明人：グルップ，ダニエル・イー
IPC分类号： H01L29/66 , H01L29/78 , H01L29/772 , H01L29/786 , H01L45/00
CPC分类号： H01L45/00 , H01L29/772 , Y10S977/937
摘要： A transistor operated by changing the electrostatic potential of an island disposed between two tunnel junctions. The transistor has an island of material which has a band gap (e.g. semiconductor material). Source and drain contacts are provided. The transistor has a first tunnel junction barrier disposed between island and source, and a second tunnel junction barrier disposed between island and drain. The island is Ohmically isolated from other parts of the transistor as well as a substrate. A gate electrode is capacitively coupled to the island so that a voltage applied to the gate can change the potential of the island. The transistor has n- and p-type embodiments. In operation, applying a gate voltage lowers (e.g., for positive gate bias) or raises (e.g., for negative gate bias) the conduction band and valence band of the island. When the conduction band or valence band aligns with the Fermi energy of the source and drain, tunneling current can pass between the source, island and drain.

2. 发明专利

JP4713884B2 Insulated-gate field-effect transistor having a Passhibuto Schottky barrier for the channel 有权
公开(公告)号：JP4713884B2
公开(公告)日：2011-06-29
申请号：JP2004527994
申请日：2003-08-08
申请人：エイコーン・テクノロジイズ・インコーポレーテッド
发明人：グルップ，ダニエル・イー , コンリー，ダニエル・ジェイ
IPC分类号： H01L29/786 , H01L21/285 , H01L21/329 , H01L21/336 , H01L29/08 , H01L29/45 , H01L29/47 , H01L29/78 , H01L29/812 , H01L29/872
CPC分类号： H01L29/47 , H01L21/28537 , H01L23/535 , H01L29/0649 , H01L29/0895 , H01L29/456 , H01L29/4908 , H01L29/66143 , H01L29/66636 , H01L29/66643 , H01L29/66666 , H01L29/66772 , H01L29/66795 , H01L29/66848 , H01L29/78 , H01L29/7827 , H01L29/7839 , H01L29/785 , H01L29/78696 , H01L29/812 , H01L29/8126 , Y10S438/958
摘要： A transistor includes a semiconductor channel disposed nearby a gate and in an electrical path between a source and a drain, wherein the channel and at least one of the source or the drain are separated by an interface layer so as to form a channel-interface layer-source/drain junction in which a Fermi level of the semiconductor channel is depinned in a region near the junction and the junction has a specific contact resistance of less than approximately 1000 Omega-mum . The interface layer may include a passivating material such as a nitride, a fluoride, an oxide, an oxynitride, a hydride and/or an arsenide of the semiconductor of the channel. In some cases, the interface layer consists essentially of a monolayer configured to depin the Fermi level of the semiconductor of the channel, or an amount of passivation material sufficient to terminate all or a sufficient number of dangling bonds of the semiconductor channel to achieve chemical stability of the surface. Also, the interface layer may include a separation layer of a material different than the passivating material. Where used, the separation layer has a thickness sufficient to reduce effects of metal-induced gap states in the semiconductor channel.

3. 发明专利

JP2005536047A Insulated-gate field-effect transistor having a Passhibuto Schottky barrier for the channel 有权
公开(公告)号：JP2005536047A
公开(公告)日：2005-11-24
申请号：JP2004527994
申请日：2003-08-08
申请人：エイコーン・テクノロジイズ・インコーポレーテッド
发明人：グルップ，ダニエル・イー , コンリー，ダニエル・ジェイ
IPC分类号： H01L21/285 , H01L21/329 , H01L21/336 , H01L29/08 , H01L29/45 , H01L29/47 , H01L29/78 , H01L29/786 , H01L29/812 , H01L29/872
CPC分类号： H01L29/47 , H01L21/28537 , H01L23/535 , H01L29/0649 , H01L29/0895 , H01L29/456 , H01L29/4908 , H01L29/66143 , H01L29/66636 , H01L29/66643 , H01L29/66666 , H01L29/66772 , H01L29/66795 , H01L29/66848 , H01L29/78 , H01L29/7827 , H01L29/7839 , H01L29/785 , H01L29/78696 , H01L29/812 , H01L29/8126 , Y10S438/958
摘要：トランジスタは、ゲート（２７０）の近くでありかつソース（２５０）とドレイン（２６０）との間の電気経路内に配置された半導体チャネル（２２０）を含み、チャネルとソースまたは当該ドレインの少なくとも一方とは、チャネル−界面層−ソース／ドレイン接合を形成するように界面層（２３０、２４０）によって分離されており、この接合の近くの領域内では半導体チャネルのフェルミ準位がピン止め解除されかつこの接合が約１０００Ω−μｍ
2 未満の固有接触抵抗を有している。界面層は、チャネルの半導体の窒化物やフッ化物、酸化物、酸窒化物、水素化物、および／またはヒ化物などのパッシブ材料を含むことができる。場合によっては界面層は、本質的に、チャネルの半導体のフェルミ準位をピン止め解除するよう構成された単層、あるいは表面の化学的安定性が実現されるように半導体チャネルのすべてのまたは十分な数のダングリング・ボンドを終結させるのに十分な量のパッシブ材料からなる。また界面層は、パッシブ材料とは異なる材料の分離層を含んでもよい。分離層は、これを使用する場合、半導体チャネルの金属誘起ギャップ状態の影響を低減させるのに十分な厚さを有する。

4. 发明专利

JP4847699B2 Device incorporating the method and the junction to pin release the Fermi level of the semiconductor in the electrical junction 有权
标题翻译：空值
公开(公告)号：JP4847699B2
公开(公告)日：2011-12-28
申请号：JP2004539828
申请日：2003-08-08
申请人：エイコーン・テクノロジイズ・インコーポレーテッド
发明人：グルップ，ダニエル・イー , コネリー，ダニエル・ジェイ
IPC分类号： H01L29/47 , H01L21/285 , H01L21/329 , H01L21/336 , H01L29/08 , H01L29/45 , H01L29/78 , H01L29/786 , H01L29/812 , H01L29/872
CPC分类号： H01L29/456 , H01L21/28537 , H01L29/0895 , H01L29/16 , H01L29/1608 , H01L29/161 , H01L29/45 , H01L29/47 , H01L29/66143 , H01L29/66643 , H01L29/78 , H01L29/7839 , H01L29/785 , H01L29/806 , H01L29/812 , H01L29/872
摘要： There is described an electrical junction comprising an interface layer disposed between a metal and a semiconductor. The interface layer includes a passivating material for passivating the surface of the semiconductor. The interface layer has a thickness configured to reduce contact resistance between the metal and the semiconductor from that which would exist at a junction between the metal and the semiconductor without the interface layer disposed therebetween.
摘要翻译：描述了一种电连接，其包括设置在金属和半导体之间的界面层。界面层包括用于钝化半导体表面的钝化材料。界面层具有被配置为降低金属和半导体之间的接触电阻与在金属和半导体之间的结处存在的接触电阻的厚度，而其间不设置界面层。

5. 发明专利

JP4717855B2 Electrostatically controlled by tunneling transistor 有权
公开(公告)号：JP4717855B2
公开(公告)日：2011-07-06
申请号：JP2007107995
申请日：2007-04-17
申请人：エイコーン・テクノロジイズ・インコーポレーテッド
发明人：グルップ，ダニエル・イー
IPC分类号： H01L29/66 , H01L29/78 , H01L29/772 , H01L29/786 , H01L39/22 , H01L45/00
CPC分类号： H01L45/00 , H01L29/772 , Y10S977/937
摘要： A transistor operated by changing the electrostatic potential of an island disposed between two tunnel junctions. The transistor has an island of material which has a band gap (e.g. semiconductor material). Source and drain contacts are provided. The transistor has a first tunnel junction barrier disposed between island and source, and a second tunnel junction barrier disposed between island and drain. The island is Ohmically isolated from other parts of the transistor as well as a substrate. A gate electrode is capacitively coupled to the island so that a voltage applied to the gate can change the potential of the island. The transistor has n- and p-type embodiments. In operation, applying a gate voltage lowers (e.g., for positive gate bias) or raises (e.g., for negative gate bias) the conduction band and valence band of the island. When the conduction band or valence band aligns with the Fermi energy of the source and drain, tunneling current can pass between the source, island and drain.

6. 发明专利

JP2007281489A Electrostatically controlled tunneling transistor 有权
标题翻译：静电控制隧道晶体管
公开(公告)号：JP2007281489A
公开(公告)日：2007-10-25
申请号：JP2007107995
申请日：2007-04-17
申请人： Acorn Technologies Inc , エイコーン・テクノロジイズ・インコーポレーテッド
发明人： GRUPP DANIEL E
IPC分类号： H01L29/66 , H01L29/78 , H01L29/772 , H01L29/786 , H01L39/22 , H01L45/00
CPC分类号： H01L45/00 , H01L29/772 , Y10S977/937
摘要： PROBLEM TO BE SOLVED: To provide a transistor operated by changing the electrostatic potential of an island disposed between two tunnel junctions.
SOLUTION: The transistor has an island 26 having a band gap, a source contact 28 and a drain contact 30, and a first tunnel junction barrier 36 between the island 26 and the drain 30. The island is ohmically isolated from other parts of the transistor as well as a substrate. A gate electrode 24 is capacitively coupled to the island 26 so that a gate voltage can change the potential of the island. The transistor has n- and p-type embodiments. In operation, the conduction band of the island is lowered when a positive gate voltage is applied and a valence band is raised when a negative gate voltage is applied. When the conduction band or the valence band aligns with the Fermi energy of the source and drain, the tunneling current can pass between the source, island, and drain.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供通过改变设置在两个隧道结之间的岛的静电电位来操作的晶体管。解决方案：晶体管具有带隙的岛26，源极接触28和漏极接触30，以及在岛26和漏极30之间的第一隧道结阻挡层36.岛与其它部分欧姆地隔离的晶体管以及衬底。栅电极24电容耦合到岛26，使得栅极电压可以改变岛的电位。晶体管具有n型和p型实施例。在工作时，当施加正栅极电压时，岛的导带降低，并且当施加负栅极电压时，导频带升高。当导带或价带与源极和漏极的费米能量对准时，隧道电流可以在源极，岛极和漏极之间通过。版权所有（C）2008，JPO＆INPIT

7. 发明专利

JP2005536070A Device incorporating the method and the junction to pin release the Fermi level of the semiconductor in the electrical junction 有权
标题翻译：空值
公开(公告)号：JP2005536070A
公开(公告)日：2005-11-24
申请号：JP2004539828
申请日：2003-08-08
申请人：エイコーン・テクノロジイズ・インコーポレーテッド
发明人：グルップ，ダニエル・イー , コネリー，ダニエル・ジェイ
IPC分类号： H01L21/285 , H01L21/329 , H01L21/336 , H01L29/08 , H01L29/45 , H01L29/47 , H01L29/78 , H01L29/786 , H01L29/812 , H01L29/872
CPC分类号： H01L29/456 , H01L21/28537 , H01L29/0895 , H01L29/16 , H01L29/1608 , H01L29/161 , H01L29/45 , H01L29/47 , H01L29/66143 , H01L29/66643 , H01L29/78 , H01L29/7839 , H01L29/785 , H01L29/806 , H01L29/812 , H01L29/872
摘要：界面層５２０が金属とＳｉベースの半導体との間に配置されかつそれらと接触する電気デバイスであって、界面層は金属と半導体との間に電流を通すことを依然として可能にしながら半導体のフェルミ準位をピン止め解除するのに有効な厚さとまっている。この界面層は例えば、（窒素、酸素、酸窒化物、ヒ素、水素、および／またはフッ素から作られた）パシベーション材料の１枚の層、ときに分離層も含む。ある場合には、界面層は半導体パシベーション材料の単層であってよい。界面層の厚さは電気デバイスに対して１０Ω−μｍ
2 以下あるいはさらに１Ω−μｍ
2 以下の最小固有接触抵抗に対応する。
摘要翻译：描述了一种电连接，其包括设置在金属和半导体之间的界面层。界面层包括用于钝化半导体表面的钝化材料。界面层具有被配置为降低金属和半导体之间的接触电阻与在金属和半导体之间的结处存在的接触电阻的厚度，而其间不设置界面层。

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