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1. 发明专利

JP6268259B2 発光デバイス有权
公开(公告)号：JP6268259B2
公开(公告)日：2018-01-24
申请号：JP2016208006
申请日：2016-10-24
申请人：エルジーイノテックカンパニーリミテッド
发明人：リー, ジョン−ラム , ジョン, イン−クォン , ヨー, ミュンチョル
IPC分类号： H01L33/38 , H01L33/32
CPC分类号： H01L33/12 , H01C7/006 , H01C7/008 , H01L27/0802 , H01L28/20 , H01L33/0025 , H01L33/007 , H01L33/0079 , H01L33/0095 , H01L33/06 , H01L33/32 , H01L33/36 , H01L33/38 , H01L33/40 , H01L33/44 , H01L33/62 , Y10S438/958 , Y10S438/977

2. 发明专利

JP6061590B2 表面保護部材および加工方法有权
标题翻译：光面侧保护件和处理方法
公开(公告)号：JP6061590B2
公开(公告)日：2017-01-18
申请号：JP2012214123
申请日：2012-09-27
申请人：株式会社ディスコ
发明人：カールプリワッサ
IPC分类号： H01L21/304
CPC分类号： H01L29/06 , H01L21/6835 , H01L21/78 , H01L2221/68318 , H01L2221/68327 , H01L2221/6834 , H01L2221/68381 , Y10S438/977

3. 发明专利

JP5626450B2 電子部品の製造方法及びチップ集合体有权
标题翻译：电子部件的制造方法和芯片组件的
公开(公告)号：JP5626450B2
公开(公告)日：2014-11-19
申请号：JP2013505642
申请日：2011-03-18
申请人：富士通株式会社
发明人：元久保田 , 元久保田 , 伊東　雅之 , 雅之伊東 , 正一岸 , 正一岸
IPC分类号： H03H3/08
CPC分类号： H01L21/02076 , H01L21/302 , H01L21/30625 , H01L23/00 , H01L23/58 , H01L24/95 , H03H3/08 , Y10S438/977

4. 发明专利

JPWO2012127582A1 電子部品の製造方法及びチップ集合体有权
公开(公告)号：JPWO2012127582A1
公开(公告)日：2014-07-24
申请号：JP2013505642
申请日：2011-03-18
申请人：富士通株式会社
发明人：元久保田 , 元久保田 , 伊東　雅之 , 雅之伊東 , 正一岸 , 正一岸
IPC分类号： H03H3/08
CPC分类号： H01L21/02076 , H01L21/302 , H01L21/30625 , H01L23/00 , H01L23/58 , H01L24/95 , H03H3/08 , Y10S438/977
摘要：ウエハ(1)を切断してパターン形成前のチップ(10)を取得する切断工程(ステップS11)と、取得された複数のチップ(10)をまとめて、各チップ(10)の切断面(10A)をバレル研磨する研磨工程(ステップS12)とを有する。更に、研磨された複数のチップ(10B)の表面(10C)が天方向(M1)に向くように各チップ(10B)を整列させる整列工程(ステップS13)を有する。更に、整列されたチップ(10B)の切断面(10A)同士を接着剤(30)で接着することでチップ集合体(20)を形成する接着工程(ステップS14)を有する。チップ集合体(20)の各チップ(10B)に回路パターン(15)を形成するパターン形成工程(ステップS16)と、チップ集合体(20)の接着剤(30)を溶融してパターン形成後のチップ(10E)に分解する溶融工程(ステップS17)とを有する。

5. 发明专利

JP2014123681A Semiconductor device manufacturing method and semiconductor device 有权
标题翻译：半导体器件制造方法和半导体器件
公开(公告)号：JP2014123681A
公开(公告)日：2014-07-03
申请号：JP2012280071
申请日：2012-12-21
申请人： Lapis Semiconductor Co Ltd , ラピスセミコンダクタ株式会社
发明人： YOSHINARI MASATAKA
IPC分类号： H01L21/336 , H01L29/739 , H01L29/78
CPC分类号： H01L29/66348 , H01L21/02016 , H01L21/0209 , H01L21/26513 , H01L21/268 , H01L21/304 , H01L21/306 , H01L21/30625 , H01L21/324 , H01L21/463 , H01L29/36 , H01L29/4916 , H01L29/66712 , H01L29/7397 , H01L29/7813 , Y10S438/977
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method which can ensure removal of an unintended impurity adhering to a semiconductor substrate with etching of the semiconductor substrate and which enables elaborate designing of a concentration profile of an impurity of the semiconductor substrate; and provide a semiconductor device manufactured by the manufacturing method.SOLUTION: A semiconductor device manufacturing method comprises: a process of a first semiconductor region including an active element for controlling a current flowing in a surface of a substrate in a thickness direction of the substrate; a process of grinding a rear face of the substrate; a first etching process of etching the rear face of the substrate after grinding by a phosphorous-containing medicinal solution; a second etching process of etching the rear face after the first etching by an etching method of an etching rate lower than that of the first etching; and a process of implanting an impurity from the rear face of the substrate after the second etching to form a second semiconductor region where a current flows.
摘要翻译：要解决的问题：提供一种半导体器件制造方法，其可以通过蚀刻半导体衬底来确保去除附着在半导体衬底上的非预期杂质，并且能够精细地设计半导体衬底的杂质的浓度分布; 并提供通过制造方法制造的半导体器件。解决方案：一种半导体器件制造方法，包括：第一半导体区域的工艺，其包括用于控制在衬底的厚度方向上在衬底的表面中流动的电流的有源元件; 研磨基板的背面的工序; 用含磷药物溶液研磨后蚀刻基板的背面的第一蚀刻工艺; 通过蚀刻速率低于第一蚀刻的蚀刻速率的蚀刻方法在第一蚀刻之后蚀刻后表面的第二蚀刻工艺; 以及在第二蚀刻之后从基板的背面注入杂质以形成电流流过的第二半导体区域的工序。

6. 发明专利

JP2014067970A Surface protection member and processing method 有权
标题翻译：表面保护构件和加工方法
公开(公告)号：JP2014067970A
公开(公告)日：2014-04-17
申请号：JP2012214123
申请日：2012-09-27
申请人： Disco Abrasive Syst Ltd , 株式会社ディスコ
发明人： PRIEWASSER KARL
IPC分类号： H01L21/304
CPC分类号： H01L29/06 , H01L21/6835 , H01L21/78 , H01L2221/68318 , H01L2221/68327 , H01L2221/6834 , H01L2221/68381 , Y10S438/977
摘要： PROBLEM TO BE SOLVED: To provide a surface protection member which allows a protection member to be easily peeled from a wafer surface and no adhesive agent to be left on a device surface, to provide a processing method of the wafer using the surface protection member.SOLUTION: A processing method includes the steps of: arranging a wafer 1 on a surface protection member 10 by making a device region 3 of the wafer 1 correspond to an unevenness absorption member 14 arranged in a recess 12 of the surface protection member 10, and fixing the surface protection member 10 and the wafer 1 by arranging an adhesive agent 20 on the outside of the device region 3 (fixing step); holding the surface protection member 10 side with a holding table 21 and grinding a rear face 1b of the wafer 1 with grinding means 22 to thin the rear face down to a predetermined thickness (grinding step); and removing the surface protection member 10 from the wafer 1 (removing step). This method makes peeling easy and allows no adhesive agent to be left on the device surface by locally arranging the adhesive agent 20 on the outside of the device region 3.
摘要翻译：要解决的问题：提供一种表面保护构件，其允许保护构件容易地从晶片表面剥离并且不会留在装置表面上的粘合剂，以提供使用表面保护构件的晶片的处理方法。解决方案：一种处理方法，包括以下步骤：通过使晶片1的器件区域3对应于布置在表面保护构件10的凹部12中的凹凸吸收构件14，将晶片1布置在表面保护构件10上，以及通过在装置区域3的外侧设置粘合剂20来固定表面保护构件10和晶片1（固定步骤）; 用保持台21保持表面保护构件10一侧，并用研磨装置22研磨晶片1的后表面1b，将背面减薄至预定厚度（研磨步骤）; 并将表面保护构件10从晶片1移除（去除步骤）。该方法使得剥离容易，并且通过将粘合剂20局部地布置在器件区域3的外部，不会使器件表面上留下粘合剂。

7. 发明专利

JP2013236099A Method of fabricating semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：JP2013236099A
公开(公告)日：2013-11-21
申请号：JP2013151630
申请日：2013-07-22
申请人： Semiconductor Energy Lab Co Ltd , 株式会社半導体エネルギー研究所
发明人： YAMAZAKI SHUNPEI , OTANI HISASHI
IPC分类号： H01L21/336 , H01L27/12 , H01L21/02 , H01L21/20 , H01L21/265 , H01L21/762 , H01L29/786
CPC分类号： H01L27/1266 , H01L21/76243 , H01L21/76254 , H01L21/76256 , H01L27/1203 , H01L27/1214 , H01L29/045 , H01L29/66772 , H01L29/78603 , Y10S438/973 , Y10S438/977
摘要： PROBLEM TO BE SOLVED: To provide: an SOI substrate suitable for a TFT and a method of fabricating the same; and a semiconductor device with high reliability using the SOI substrate and a method of fabricating the same.SOLUTION: When an SOI substrate is fabricated by using a technique typified by SIMOX, ELTRAN, or Smart-Cut, a single crystal semiconductor substrate having a main surface (crystal face) of a {110} plane is used. In such an SOI substrate, adhesion between a buried insulating layer as an underlayer and a single crystal silicon layer is high, and it becomes possible to realize a semiconductor device with high reliability.
摘要翻译：要解决的问题：提供：适用于TFT的SOI衬底及其制造方法; 以及使用SOI衬底的具有高可靠性的半导体器件及其制造方法。解决方案：通过使用以SIMOX，ELTRAN或Smart-Cut为代表的技术制造SOI衬底时，具有主体的单晶半导体衬底使用{110}面的表面（晶面）。在这样的SOI衬底中，作为下层的埋入绝缘层和单晶硅层之间的粘附性高，可以实现高可靠性的半导体器件。

8. 发明专利

JP5207747B2 A method of forming a random access memory 有权
公开(公告)号：JP5207747B2
公开(公告)日：2013-06-12
申请号：JP2008013188
申请日：2008-01-23
申请人：グレンジェイリーディ
发明人：グレンジェイリーディ
IPC分类号： G11C11/401 , H01L25/065 , G11C5/02 , G11C5/04 , H01L21/336 , H01L21/768 , H01L21/8242 , H01L21/8244 , H01L21/8246 , H01L21/8247 , H01L25/07 , H01L25/18 , H01L27/06 , H01L27/10 , H01L27/105 , H01L27/108 , H01L27/11 , H01L27/115 , H01L29/788 , H01L29/792 , H01L43/08
CPC分类号： H01L27/10897 , G11C5/02 , G11C5/025 , G11C5/04 , G11C29/44 , G11C29/81 , G11C29/846 , G11C29/848 , H01L23/481 , H01L25/18 , H01L27/0688 , H01L27/105 , H01L2224/29109 , H01L2224/29111 , H01L2224/29116 , H01L2224/29118 , H01L2224/29124 , H01L2224/29144 , H01L2224/29147 , H01L2224/29155 , H01L2224/29166 , H01L2224/29169 , H01L2224/8083 , H01L2225/06541 , H01L2924/01079 , Y10S438/977 , H01L2924/00014
摘要： An on-chip reconfigurable memory is disclosed, comprising: a plurality of data lines, a plurality of gate lines, an array of memory cells, each memory cell storing a data value and comprising circuitry for coupling that data value to one of said data lines in response to the selection of one of said gate lines, a gate line selection circuit for enabling a gate line for a memory operation, said gate line selection circuit comprising programmable gates to receive address assignments for one or more of said gate lines, said address assignments for determining which of said gate lines is selected for each programmed address assignment and a controller for determining that at least one of said memory cells is defective and for altering, in at least one instance, said address assignments of said gate lines to eliminate references to that gate line that causes that defective memory cell to couple a data value to one of said data lines.

9. 发明专利

JP2013062552A Light-emitting device 审中-公开
标题翻译：发光装置
公开(公告)号：JP2013062552A
公开(公告)日：2013-04-04
申请号：JP2013001743
申请日：2013-01-09
申请人： Lg Electronics Inc , エルジーエレクトロニクスインコーポレイティド , Lg Innotek Co Ltd , エルジーイノテックカンパニーリミテッド
发明人： CHO HYUN KYONG , KIM SUN KYUNG , CHO SHUNGO
IPC分类号： H01L33/16 , H01L33/36 , H01L33/22 , H01L33/32
CPC分类号： H01L33/20 , H01L33/0079 , H01L33/22 , H01L33/405 , H01L33/42 , H01L33/44 , H01L33/48 , H01L33/60 , H01L33/62 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/48257 , H01L2224/48465 , H01L2224/73265 , H01L2933/0016 , H01L2933/0033 , H01L2933/0083 , Y10S438/977 , H01L2924/00014 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a light-emitting device used with an optical crystal structure and having optimum light extraction efficiency, which can improve light extraction efficiency while retaining electrical characteristics in introduction of a light extraction structure into the light-emitting device.SOLUTION: The light-emitting device comprises: a reflecting electrode; a semiconductor layer located on the reflecting electrode and comprising a luminous layer; and an optical crystal formed on the semiconductor layer. The distance between the centers of the reflecting electrode and the luminous layer is between (odd number)×λ/4n-α and (odd number)×λ/4n+α, where λ is the wavelength of light emitted from the luminous layer, n is the refractive index of the semiconductor layer, and α is 0.10λ/n.
摘要翻译：要解决的问题：提供一种与光学晶体结构一起使用且具有最佳光提取效率的发光装置，其可以在将光提取结构引入发光的同时保持电特性的同时提高光提取效率设备。解决方案：发光装置包括：反射电极; 位于所述反射电极上并包含发光层的半导体层; 以及形成在半导体层上的光学晶体。反射电极和发光层的中心之间的距离在（奇数）×λ/ 4n-α和（奇数）×λ/ 4n +α之间，其中λ是从发光层发射的光的波长， n为半导体层的折射率，α为0.10λ/ n。版权所有（C）2013，JPO＆INPIT

10. 发明专利

JP5011881B2 A method of manufacturing a semiconductor device 有权
公开(公告)号：JP5011881B2
公开(公告)日：2012-08-29
申请号：JP2006219477
申请日：2006-08-11
申请人：株式会社デンソー
发明人：健宮嶋 , 仁山口
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L21/823814 , H01L21/823885 , H01L29/0634 , H01L29/0649 , H01L29/0653 , H01L29/1095 , H01L29/66734 , H01L29/7803 , H01L29/7811 , Y10S438/977
摘要： A manufacturing method of a semiconductor device includes: forming multiple trenches on a semiconductor substrate; forming a second conductive type semiconductor film in each trench to provide a first column with the substrate between two trenches and a second column with the second conductive type semiconductor film in the trench, the first and second columns alternately repeated along with a predetermined direction; thinning a second side of the substrate; and increasing an impurity concentration in a thinned second side so that a first conductive type layer is provided. The impurity concentration of the first conductive type layer is higher than the first column. The first column provides a drift layer so that a vertical type first-conductive-type channel transistor is formed.

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