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1. 发明专利

JP5426069B2 Semiconductor device and a method of manufacturing the same 有权
公开(公告)号：JP5426069B2
公开(公告)日：2014-02-26
申请号：JP2006237058
申请日：2006-08-31
申请人：富士通セミコンダクター株式会社
发明人：浩由富田
IPC分类号： G11C11/4074 , G11C29/12 , H01L21/66 , H01L21/8242 , H01L27/108
CPC分类号： G11C11/4074 , G11C11/401 , G11C29/50 , G11C2029/0403 , G11C2207/2254 , H01L27/0207 , H01L27/10829

2. 发明专利

JP2011502351A How to reduce the trench capacitor leakage current of random access memory device 审中-公开
公开(公告)号：JP2011502351A
公开(公告)日：2011-01-20
申请号：JP2010530987
申请日：2007-10-31
申请人：アギアシステムズインコーポレーテッド
发明人：シング，ランビア , ユアン，シァオジュン , ロッシー，ネイス，エム．
IPC分类号： H01L21/8242 , H01L21/8234 , H01L27/06 , H01L27/108
CPC分类号： H01L27/1087 , H01L21/76224 , H01L27/10829 , H01L27/10861
摘要： A method is provided that includes forming a trench isolation structure in a dynamic random memory region (DRAM) of a substrate and patterning an etch mask over the trench structure to expose a portion of the trench structure. A portion of the exposed trench structure is removed to form a gate trench that includes a first corner formed by the substrate and a second corner formed by the trench structure. The etch mask is removed and the first corner of the gate trench is rounded to form a rounded corner. This is followed by the formation of an oxide layer over a sidewall of the gate trench, the first rounded corner, and the semiconductor substrate adjacent the gate trench. The trench is filled with a gate material.

3. 发明专利

JP4583787B2 Semiconductor device and manufacturing method including a gate line 有权
公开(公告)号：JP4583787B2
公开(公告)日：2010-11-17
申请号：JP2004083473
申请日：2004-03-22
申请人：三星電子株式会社Samsung Electronics Co.,Ltd.
发明人：珍俊朴 , 志永金
IPC分类号： H01L21/8234 , H01L21/8242 , H01L21/336 , H01L21/60 , H01L27/088 , H01L27/108 , H01L29/76 , H01L29/78
CPC分类号： H01L27/10855 , H01L21/76897 , H01L27/0207 , H01L27/10829 , H01L27/10876 , H01L27/10888 , H01L27/10891 , H01L29/66621 , H01L29/7834 , H01L2924/3011

4. 发明专利

JP4362128B2 A method of manufacturing a semiconductor device 有权
公开(公告)号：JP4362128B2
公开(公告)日：2009-11-11
申请号：JP2006157048
申请日：2006-06-06
申请人：南亞科技股▲ふん▼有限公司
发明人：培瑛李
IPC分类号： H01L21/8242 , H01L21/3205 , H01L23/52 , H01L27/108
CPC分类号： H01L27/10888 , H01L27/10823 , H01L27/10829 , H01L27/10876 , H01L27/10891 , H01L29/66621 , H01L29/7834

5. 发明专利

JP2007134470A Semiconductor device and manufacturing method thereof 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2007134470A
公开(公告)日：2007-05-31
申请号：JP2005325580
申请日：2005-11-10
申请人： Toshiba Corp , 株式会社東芝
发明人： OKAJIMA MUTSUMI
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10867 , H01L27/10829
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device and a manufacturing method thereof for controlling increase in manufacturing steps and manufacturing cost by facilitating lithography to form an element isolating region even through ultra-fine processes.
SOLUTION: A color insulating film 5 is formed to an internal wall of a trench TI where a trench capacitor is formed. Ions are guided to the part of the color insulating film 5 with ion implantation of an impurity into this trench TI from one diagonal direction. A part 5' of the color insulating film 5 to which the ions are guided is removed by etching utilizing difference in the etching rates.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种半导体器件及其制造方法，用于通过促进光刻以便通过超细工艺形成元件隔离区域来控制制造步骤和制造成本的增加。解决方案：在形成沟槽电容器的沟槽TI的内壁上形成彩色绝缘膜5。通过从一个对角线方向将杂质离子注入到该沟槽TI中，将离子引导到彩色绝缘膜5的一部分。通过利用蚀刻速率的差异进行蚀刻来去除引导离子的彩色绝缘膜5的部分5'。版权所有（C）2007，JPO＆INPIT

6. 发明专利

JP2007088458A Transistor manufacturing method and memory device manufacturing method 审中-公开
标题翻译：晶体管制造方法和存储器件制造方法
公开(公告)号：JP2007088458A
公开(公告)日：2007-04-05
申请号：JP2006245522
申请日：2006-09-11
申请人： Qimonda Ag , キモンダアクチエンゲゼルシャフト
发明人： WANG PENG-FEI , NUETZEL JOACHIM , WEIS ROLF , SCHLOSSER TILL , STRASSER MARC , LUYKEN RICHARD JOHANNES
IPC分类号： H01L21/8242 , H01L21/3205 , H01L21/768 , H01L23/52 , H01L27/108 , H01L29/78
CPC分类号： H01L27/10823 , G11C11/404 , H01L21/76897 , H01L27/0207 , H01L27/10826 , H01L27/10829 , H01L27/10867 , H01L27/10873 , H01L27/10876 , H01L27/10879 , H01L29/66795 , H01L29/66818 , H01L29/785 , H01L29/7851 , H01L29/7854
摘要： PROBLEM TO BE SOLVED: To provide a memory device manufacturing method for reducing a surface region of a DRAM access transistor. SOLUTION: The transistor manufacturing method includes a step for forming a gate electrode by defining a gate groove part in a substrate. Plate-like parts are respectively defined for each element isolation trench in a position adjacent to the gate groove part. Two respective plate-like parts sandwiching the gate groove part are connected with each other. The two respective plate-like parts are defined by an etching process for selectively etching an insulating material for the element isolation trench to a semiconductor substrate material. A gate insulator is provided at an interface part between an active region and the gate groove part, and also, at an interface part between the active region and each plate-like part. A gate electrode material is deposited and formed so as to fill the gate groove part and each plate-like part. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于减小DRAM存取晶体管的表面区域的存储器件制造方法。解决方案：晶体管制造方法包括通过在衬底中限定栅极沟槽部分来形成栅电极的步骤。在与栅极槽部分相邻的位置中，分别对每个元件隔离沟槽限定板状部分。夹着栅槽部的两个板状部件彼此连接。两个相应的板状部分通过蚀刻工艺限定，用于将用于元件隔离沟槽的绝缘材料选择性地蚀刻到半导体衬底材料。栅极绝缘体设置在有源区域和栅极沟槽部分之间的界面部分处，并且还在有源区域和每个板状部分之间的界面部分处。沉积并形成栅极电极材料以便填充栅极槽部分和每个板状部分。版权所有（C）2007，JPO＆INPIT

7. 发明专利

JPWO2004061947A1 半導体装置、ＤＲＡＭ集積回路装置およびその製造方法审中-公开
公开(公告)号：JPWO2004061947A1
公开(公告)日：2006-05-18
申请号：JP2004564530
申请日：2003-12-25
申请人：富士通株式会社
发明人：泰示江間 , 泰示江間
IPC分类号： H01L27/108 , H01L21/768 , H01L21/822 , H01L21/8242 , H01L23/522 , H01L27/04
CPC分类号： H01L27/10894 , H01L21/76801 , H01L21/76807 , H01L21/76813 , H01L21/76816 , H01L21/76838 , H01L23/5223 , H01L27/10808 , H01L27/10829 , H01L27/10852 , H01L27/10855 , H01L27/10882 , H01L27/10885 , H01L27/10888 , H01L27/10897 , H01L2924/0002 , H01L2924/00
摘要：多層配線構造を有する半導体装置は、第1の導電領域と、前記基板に対して前記第1の導電領域よりも高い位置に上面を有する第2の導電領域と、前記第1および第2の導電領域を覆う絶縁膜と、前記絶縁膜中に、前記第2の導電領域を露出するように形成された配線溝と、前記絶縁膜中に前記第1の導電領域を露出するように形成されたコンタクトホールと、前記配線溝および前記コンタクトホールを充填する配線パターンとよりなり、前記配線パターンの上面は、前記絶縁膜の上面に一致する。

8. 发明专利

JP2006049413A Semiconductor device and its manufacturing method 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2006049413A
公开(公告)日：2006-02-16
申请号：JP2004225308
申请日：2004-08-02
申请人： Fujitsu Ltd , 富士通株式会社
发明人： SUGAYA SHINJI , HASHIMOTO KOICHI , TAKAO YOSHIHIRO
IPC分类号： H01L21/8242 , H01L21/76 , H01L21/8234 , H01L27/06 , H01L27/08 , H01L27/10 , H01L27/108
CPC分类号： H01L27/1087 , H01L21/76229 , H01L27/0629 , H01L27/10829 , H01L29/66181 , H01L29/945
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device in which a logic LSI having a structure controlled in the mechanical stress of trench element separation, and a memory element of one transistor plus one capacitor type which is manufactured by using the manufacturing process of the logic LSI are loaded in a mixed state, and also to provide a method of manufacturing the device.
SOLUTION: The semiconductor device is provided with: a semiconductor substrate 10 in which trenches 16a and 16b are formed; an element separating film 32a having a liner film containing a silicon nitride film 20 formed in the trench 16a and a silicon oxide film-based insulating film; and another element separating film 32b buried in the bottom of the trench 16b. The device is also provided with an impurity diffusing area 40 formed in the upper side wall of the trench 16b as a first electrode, a capacitor dielectric film 43 composed of a silicon oxide film-based insulating film, and a capacitor having a second electrode 46.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种半导体器件，其中具有受沟槽元件分离的机械应力控制的结构的逻辑LSI，以及通过使用制造工艺制造的一个晶体管的存储元件加上一个电容器类型逻辑LSI的负载处于混合状态，并且还提供制造该器件的方法。解决方案：半导体器件设置有：形成沟槽16a和16b的半导体衬底10; 具有含有形成在沟槽16a中的氮化硅膜20的衬垫膜和氧化硅膜基绝缘膜的元件分离膜32a; 以及埋在沟槽16b底部的另一元件分离膜32b。该器件还设置有形成在作为第一电极的沟槽16b的上侧壁中的杂质扩散区域40，由氧化硅膜基绝缘膜构成的电容器电介质膜43和具有第二电极46的电容器（C）2006年，JPO＆NCIPI

9. 发明专利

JP2005197405A Semiconductor device and manufacturing method therefor 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2005197405A
公开(公告)日：2005-07-21
申请号：JP2004001075
申请日：2004-01-06
申请人： Toshiba Corp , 株式会社東芝
发明人： HIYAMA KAORU , SANUKI TOMOYA , FUJII OSAMU
IPC分类号： H01L21/822 , H01L21/8234 , H01L21/8238 , H01L21/8239 , H01L21/8242 , H01L27/04 , H01L27/06 , H01L27/08 , H01L27/088 , H01L27/092 , H01L27/105 , H01L27/108 , H01L29/786 , H01L29/92
CPC分类号： H01L21/823807 , H01L27/0629 , H01L27/105 , H01L27/1052 , H01L27/10829 , H01L27/10894 , H01L29/92
摘要： PROBLEM TO BE SOLVED: To improve carrier mobility of a CMOS device and to prevent deterioration of reliability of a memory due to leakage current when the CMOS device and a memory are formed on the same substrate.
SOLUTION: A semiconductor device comprises: the substrate having a first region and a second region adjacent to the first region, and a first silicon layer on a surface; a second silicon layer disposed on the first silicon layer of the first region; a relaxation layer which has a lattice constant larger than the second silicon layer and is prepared on the first silicon layer of the second region; and a deformed silicon layer which has the same lattice constant as the relaxation layer and is arranged on the relaxation layer.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了提高CMOS器件的载流子迁移率，并且防止当CMOS器件和存储器形成在同一衬底上时由于泄漏电流引起的存储器可靠性的劣化。解决方案：半导体器件包括：衬底，具有第一区域和与第一区域相邻的第二区域，以及表面上的第一硅层; 设置在第一区域的第一硅层上的第二硅层; 松弛层，其具有比第二硅层大的晶格常数，并且制备在第二区域的第一硅层上; 以及具有与弛豫层相同的晶格常数并且设置在弛豫层上的变形硅层。版权所有（C）2005，JPO＆NCIPI

10. 发明专利

JP2005167132A Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2005167132A
公开(公告)日：2005-06-23
申请号：JP2003407367
申请日：2003-12-05
申请人： Toshiba Corp , 株式会社東芝
发明人： HIEDA KATSUHIKO , MATSUZAWA KAZUYA , HAGISHIMA DAISUKE
IPC分类号： H01L29/423 , H01L21/336 , H01L21/8242 , H01L27/108 , H01L27/12 , H01L29/49 , H01L29/786
CPC分类号： H01L29/785 , H01L27/108 , H01L27/10814 , H01L27/10829 , H01L27/10873 , H01L27/10879 , H01L27/1211 , H01L29/42392 , H01L29/66545 , H01L29/66795 , H01L29/7854 , H01L29/78648
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device having an excellent characteristic and reliability.
SOLUTION: The semiconductor device comprises a base insulating film 102 having a recess 120; a first semiconductor section 103a including a part formed on the base insulating film and a first overlap part overlapped with the recess; a second semiconductor section 103b including a part formed on the base insulating film and a second overlap part overlapped with the recess and opposed to the first overlap part; and a third semiconductor section 103c positioned between the first and second semiconductor sections and including a part located above the recess. The semiconductor device also comprises a semiconductor structure 103 having the width of the overlap of the first overlap part equal to that of the second overlap part; a gate electrode 116 including a first electrode section for covering the upper and side surfaces of the third semiconductor section and a second electrode section formed within the recess; and a gate insulating film disposed between the semiconductor structure and the gate electrode.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供具有优异的特性和可靠性的半导体器件。解决方案：半导体器件包括具有凹部120的基底绝缘膜102; 包括形成在基底绝缘膜上的部分和与凹部重叠的第一重叠部分的第一半导体部分103a; 第二半导体部分103b，包括形成在基底绝缘膜上的部分和与凹部重叠并与第一重叠部分相对的第二重叠部分; 以及位于第一和第二半导体部分之间并且包括位于凹部上方的部分的第三半导体部分103c。半导体器件还包括具有第一重叠部分的重叠宽度等于第二重叠部分的重叠宽度的半导体结构103; 栅电极116，其包括用于覆盖第三半导体部分的上表面和第二表面的第一电极部分和形成在凹部内的第二电极部分; 以及设置在半导体结构和栅极之间的栅极绝缘膜。版权所有（C）2005，JPO＆NCIPI

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