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1. 发明专利

JP2014049508A Nonvolatile storage device 有权
标题翻译：非易失存储器件
公开(公告)号：JP2014049508A
公开(公告)日：2014-03-17
申请号：JP2012189307
申请日：2012-08-29
申请人： Toshiba Corp , 株式会社東芝
发明人： MATSUZAWA KAZUYA
IPC分类号： H01L27/105 , H01L45/00 , H01L49/00
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile storage device with a high storage density.SOLUTION: According to an embodiment, the nonvolatile storage device including a first conductive part, a second conductive part, and a storage layer is provided. The second conductive part contains metal atoms of at least one of lithium, chromium, iron, copper, indium, tellurium, calcium, sodium, silver, cobalt, gold, titanium, tungsten, erbium, platinum, aluminum, and nickel or an alloy thereof. The storage layer includes a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type. The first semiconductor layer is provided between the first conductive part and the second conductive part. The second semiconductor layer is provided between the first semiconductor layer and the second conductive part. The storage layer reversibly transitions between a first state having a low resistance and a second state having a higher resistance than the first state by at least one of a voltage applied through the first conductive part and the second conductive part and a current supplied through them.
摘要翻译：要解决的问题：提供具有高存储密度的非易失性存储装置。解决方案：根据实施例，提供包括第一导电部分，第二导电部分和存储层的非易失性存储装置。第二导电部分包含锂，铬，铁，铜，铟，碲，钙，钠，银，钴，金，钛，钨，铒，铂，铝和镍中的至少一种的金属原子或其合金。存储层包括第一导电类型的第一半导体层和第二导电类型的第二半导体层。第一半导体层设置在第一导电部和第二导电部之间。第二半导体层设置在第一半导体层和第二导电部之间。存储层通过第一导电部分和第二导电部分施加的电压和通过它们提供的电流中的至少一个，在具有低电阻的第一状态和具有比第一状态更高的电阻的第二状态之间可逆地转变。

2. 发明专利

JP2007158232A Nonvolatile semiconductor memory and method of manufacturing same 有权
标题翻译：非线性半导体存储器及其制造方法
公开(公告)号：JP2007158232A
公开(公告)日：2007-06-21
申请号：JP2005354676
申请日：2005-12-08
申请人： Toshiba Corp , 株式会社東芝
发明人： MATSUZAWA KAZUYA
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L29/42336 , G11C16/0483 , H01L27/115 , H01L27/11521
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory that can implant impurities into a source-drain region in the high density, and to provide a method of manufacturing the same.
SOLUTION: The nonvolatile semiconductor memory has a primary insulating film formed on a wall surface of a semiconductor substrate's trench, a floating gate electrode formed on the primary insulating film's surface within the trench, a source-drain region of a transistor that is formed in the semiconductor substrate and treats the semiconductor substrate adjacent to the trench as a channel region, a secondary insulating film formed on the semiconductor substrate's front surface, and a control gate electrode formed on the secondary insulating film's surface on the channel region and the floating gate electrode, wherein tunnel current is applied to the primary insulating film to take out and put in an electrical charge from and to the floating gate electrode, thus creating an in-memory state.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供可以将杂质以高密度植入源极 - 漏极区域的非易失性半导体存储器，并提供其制造方法。解决方案：非易失性半导体存储器具有形成在半导体衬底的沟槽的壁表面上的初级绝缘膜，形成在沟槽内的主绝缘膜的表面上的浮置栅极电极，晶体管的源极 - 漏极区域形成在半导体衬底中并且将与沟槽相邻的半导体衬底作为沟道区域，形成在半导体衬底的正面上的次级绝缘膜和形成在沟道区域上的次级绝缘膜表面上的控制栅电极和浮置栅极电极，其中隧道电流被施加到初级绝缘膜以取出并且从浮栅电极引入电荷，从而产生存储器内状态。版权所有（C）2007，JPO＆INPIT

3. 发明专利

JP2006093215A Nonvolatile semiconductor memory device and manufacturing method thereof 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：JP2006093215A
公开(公告)日：2006-04-06
申请号：JP2004273508
申请日：2004-09-21
申请人： Toshiba Corp , 株式会社東芝
发明人： ISHIHARA TAKAMITSU , MATSUZAWA KAZUYA
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a structure for manufacturing a fin type NAND flash memory in a self-alignment process along with its manufacturing method.
SOLUTION: By employing a strip-like SOI layer, a silicon layer region 8 is formed on a BOX oxide film 13. A tunnel insulating film 9 and an insulating film region 31 are formed respectively on the side surface and upper surface of the silicon layer region 8. A floating gate region 36 is formed to contact the tunnel insulating film 9 and the insulating film region 31. An insulating film 37 is formed to contact the floating gate region 36. A floating gate region 38 is formed to contact the insulating film 37 and the insulating film region 31. In this construction, the floating gate region 36 is formed higher than the silicon region 8.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种在自对准过程中制造鳍型NAND闪速存储器的结构及其制造方法。解决方案：通过采用带状SOI层，在BOX氧化膜13上形成硅层区8.在隧道绝缘膜9和绝缘膜区31上分别形成隧道绝缘膜9和绝缘膜区31，硅层区域8.形成浮栅区域36以与隧道绝缘膜9和绝缘膜区域31接触。形成绝缘膜37以接触浮栅区域36.形成浮栅区域38以接触绝缘膜37和绝缘膜区域31.在这种结构中，浮栅区域36形成得比硅区域8高。（C）2006，JPO＆NCIPI

4. 发明专利

JP2005310824A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2005310824A
公开(公告)日：2005-11-04
申请号：JP2004121715
申请日：2004-04-16
申请人： Toshiba Corp , 株式会社東芝
发明人： KINOSHITA ATSUHIRO , WATANABE HIROSHI , MATSUZAWA KAZUYA
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L29/7883
摘要： PROBLEM TO BE SOLVED: To improve time controllability of an electronic timer which can control influence on the operation life of an aging device of mixture of defective bits and production variations of structure parameter of the aging device.
SOLUTION: The semiconductor device is provided with a plurality of cells 31 deposited on a semiconductor substrate, each of which includes a floating gate formed on the substrate via a gate insulating film, switch elements 32 connected respectively in direct to these cells 31, and a sense circuit 34 for comparing the current flowing into the cells 31 with the predetermined reference value. The cell 31 is designed to provide the Weibull distribution as the distribution of initial current value, the initial current values of cells 31 are arranged from the lower value, the cells around 63.21% of the entire cells in the predetermined range, and the cells not selected are disconnected with the switch element 32.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提高电子计时器的时间可控性，可以控制对缺陷位混合的老化装置的使用寿命和老化装置的结构参数的生产变化的影响。解决方案：半导体器件设置有沉积在半导体衬底上的多个单元31，每个单元31包括通过栅极绝缘膜形成在衬底上的浮置栅极，分别直接连接到这些单元31的开关元件32 以及用于将流入单元31的电流与预定参考值进行比较的感测电路34。单元31被设计为提供威布尔分布作为初始电流值的分布，单元31的初始电流值从较低值排列，单元格在预定范围内的整个单元的63.21％左右，单元格不是所选择的与开关元件32断开。版权所有（C）2006，JPO＆NCIPI

5. 发明专利

JP2005242470A Circuit evaluation method, evaluation device and evaluation program 审中-公开
标题翻译：电路评估方法，评估设备和评估程序
公开(公告)号：JP2005242470A
公开(公告)日：2005-09-08
申请号：JP2004048270
申请日：2004-02-24
申请人： Toshiba Corp , 株式会社東芝
发明人： MATSUZAWA KAZUYA
IPC分类号： G06F17/50 , H01L21/82
CPC分类号： G06F17/5022
摘要： PROBLEM TO BE SOLVED: To provide a circuit evaluation method, an evaluation device and an evaluation program, wherein device analysis and circuit analysis are cooperated, allowing high-accuracy analysis of a circuit.
SOLUTION: This circuit evaluation method includes steps: for reading device information about a device included in a semiconductor integrated circuit that is an evaluated target, executing the device analysis, and acquiring a device analysis value; for reading circuit information about the semiconductor integrated circuit stored in a circuit information area, and connection node information about the semiconductor integrated circuit stored in a connection information area, producing a net list using the device analysis value in a value of power of a connection node to execute the circuit analysis, and acquiring an analysis value of the semiconductor integrated circuit; and using the analysis value of the semiconductor integrated circuit in the value of the power of the connection node to set a condition for executing the device analysis, and repeating execution of the device analysis and the circuit analysis, until a difference between the device analysis value in the connection node and the analysis value of the semiconductor integrated circuit satisfies decision conditions.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种电路评估方法，评估装置和评估程序，其中进行设备分析和电路分析，允许电路的高精度分析。该电路评估方法包括以下步骤：用于读取关于包括在作为评估对象的半导体集成电路中的设备的设备信息，执行设备分析并获取设备分析值; 用于读取存储在电路信息区域中的半导体集成电路的电路信息，以及关于存储在连接信息区域中的半导体集成电路的连接节点信息，使用连接节点的功率值中的设备分析值来生成网络列表执行电路分析，获取半导体集成电路的分析值; 并且使用连接节点的功率值的半导体集成电路的分析值来设定用于执行器件分析的条件，并重复器件分析和电路分析的执行，直到器件分析值在连接节点和半导体集成电路的分析值满足判定条件。版权所有（C）2005，JPO＆NCIPI

6. 发明专利

JP2005109233A Static discharge protective element and circuit, static discharge protective circuit designing system, and static discharge protective circuit designing method and program 审中-公开
标题翻译：静电放电保护元件和电路，静电放电保护电路设计系统和静态放电保护电路设计方法与程序
公开(公告)号：JP2005109233A
公开(公告)日：2005-04-21
申请号：JP2003342339
申请日：2003-09-30
申请人： Toshiba Corp , 株式会社東芝
发明人： MATSUZAWA KAZUYA
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8238 , H01L27/06 , H01L27/092 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a static discharge protective element wherein the operating voltage is minutely set according to the breakdown voltage and the wiring resistance of a circuit in a semiconductor integrated circuit. SOLUTION: The static discharge protective element 1a is connected to the input node Ni of an inner circuit 3 to be protected, and comprises a p-type first semiconductor region (well region) 5, a surge current carrying electrode (drain electrode) 11 forming a Schottky junction by contacting with a part of the well region 5, and connected to the input node Ni; an n + -type second semiconductor region (drain region) 15 in contact with another part of the drain electrode 11 arranged in the well region 5; and an n + -type third semiconductor region (source region) 8 arranged in the well region 5 and separated from the drain region 15; and a control electrode (gate electrode) 17 arranged on the well region 5 in between the drain region 15 and the source region 8, but insulated from the well region 5 and connected to the ground potential. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种静电放电保护元件，其中根据半导体集成电路中的电路的击穿电压和布线电阻来精细地设置工作电压。解决方案：静电放电保护元件1a连接到要保护的内部电路3的输入节点Ni，并且包括p型第一半导体区域（阱区域）5，浪涌电流承载电极（漏电极）11通过与阱区5的一部分接触而形成肖特基结，并连接到输入节点Ni; 与布置在阱区5中的漏电极11的另一部分接触的n + 型第二半导体区域（漏区）15; 和布置在阱区5中并与漏极区15分离的n + 型第三半导体区域（源极区域）8; 以及布置在漏极区域15和源极区域8之间的阱区域5上但与阱区域5绝缘并连接到接地电位的控制电极（栅电极）17。版权所有（C）2005，JPO＆NCIPI

7. 发明专利

JP2004349549A Manufacturing method of semiconductor device 有权
公开(公告)号：JP2004349549A
公开(公告)日：2004-12-09
申请号：JP2003146362
申请日：2003-05-23
申请人： Toshiba Corp , 株式会社東芝
发明人： ISHIHARA TAKAMITSU , MATSUZAWA KAZUYA
IPC分类号： H01L23/522 , H01L21/768 , H01L21/8234 , H01L21/8247 , H01L27/00 , H01L27/088 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device for suppressing an interference effect between devices. SOLUTION: The manufacturing method of the semiconductor device comprises: a first process of forming a silicon layer 18 between gate electrodes 15 on a silicon substrate 11; a second process of forming an oxide film 19 on the silicon layer 18; a third process of forming a silicon layer 20 on the gate electrode 15 and the oxide film 19; a fourth process of forming an oxide film 21 on the silicon layer 20; a fifth process of forming a nitride film 22 on the oxide film 21; a sixth process of forming a through groove 23 at the silicon layer 20; a seventh process of forming a nitride film 24 on the surface of the silicon layer 20 facing the through groove 23; an eighth process of removing the silicon layer 18; a ninth process of removing the nitride films 22 and 24; and a tenth process of connecting the part of the through groove 23 to the silicon layer 20. COPYRIGHT: (C)2005,JPO&NCIPI

8. 发明专利

JP2003298063A Field effect transistor 有权
标题翻译：场效应晶体管
公开(公告)号：JP2003298063A
公开(公告)日：2003-10-17
申请号：JP2002097049
申请日：2002-03-29
申请人： Toshiba Corp , 株式会社東芝
发明人： SUGIYAMA NAOHARU , TEZUKA TSUTOMU , TAKAGI SHINICHI , MATSUZAWA KAZUYA
IPC分类号： H01L27/08 , H01L21/8234 , H01L21/8238 , H01L27/088 , H01L27/092 , H01L29/786
CPC分类号： H01L29/785 , H01L27/1211
摘要： PROBLEM TO BE SOLVED: To provide a field effect transistor that can suppress short channel effects and can be improved in driving force.
SOLUTION: This field effect transistor is provided with a channel region 2 having a pair of facing channel surfaces, a pair of gate electrodes (3 and 4) respectively formed on the channel surfaces, and a source region 5 and a drain region 6 separately formed and positioned to hold the channel region 2 in between. The interval between the gate electrodes (3 and 4) on the source region 5 side is made longer than that between the electrodes (3 and 4) on the drain region 6 side.
COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：提供能够抑制短通道效应并且可以提高驱动力的场效应晶体管。解决方案：该场效应晶体管设置有具有一对相对的沟道表面的沟道区2，分别形成在沟道表面上的一对栅电极（3和4），以及源极区5和漏极区 6分开地形成并定位成将通道区域2保持在其间。源极区域5侧的栅电极（3和4）之间的间隔比在漏极区域6侧的电极（3和4）之间的间隔更长。版权所有（C）2004，JPO

9. 发明专利

JP2003282861A Tunnel current evaluation device, device simulation apparatus and device simulation method 有权
标题翻译：隧道电流评估装置，装置模拟装置和装置模拟方法
公开(公告)号：JP2003282861A
公开(公告)日：2003-10-03
申请号：JP2002089274
申请日：2002-03-27
申请人： Toshiba Corp , 株式会社東芝
发明人： MATSUZAWA KAZUYA
IPC分类号： G06F17/50 , H01L21/336 , H01L29/00 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To evaluate a tunnel current of a simulation structure with high accuracy. SOLUTION: A device simulation apparatus comprises an input 1, an initial value setting part 2, a bias setting part 3, a non-AC alliance computation part 4 for computing a potential, an electronic concentration and a hole concentration at each lattice point for simulation, a quantum correction potential computation part 5, a Fermi level computation part 6 for computing a Fermi level, a gate current computation part 7 for computing a gate current and a generation extinction rate of electrons and holes by a tunnel, an AC alliance computation part 8 for computing a potential at a gate electrode and AC components of the gate current, an output part 9 for outputting a simulation result, and a simulation control unit 10 for controlling the whole. When a device simulation is carried out taking into consideration and interface quantization, as an interface carrier density is computed, the Fermi level and the gate current can be computed, and even if a thickness of a gate insulating film of a MOSFET is reduced, a thickness of the gate insulating film can be computed with good accuracy. COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：以高精度评估模拟结构的隧道电流。解决方案：装置模拟装置包括输入端1，初始值设定部分2，偏置设定部分3，用于计算电位的非AC联盟计算部分4，每个格子处的电子浓度和空穴浓度用于模拟的点，量子校正电位计算部分5，用于计算费米能级的费米能级计算部分6，用于计算隧道的电流和空穴的栅极电流和发电消光速率的栅极电流计算部分7，AC 用于计算栅极电位和栅极电流的AC分量的联盟计算部分8，用于输出模拟结果的输出部分9，以及用于控制整体的模拟控制单元10。当考虑到接口量化进行器件仿真和计算接口载流子密度时，可以计算费米能级和栅极电流，即使MOSFET的栅极绝缘膜的厚度减小，可以以良好的精度计算栅极绝缘膜的厚度。版权所有（C）2004，JPO

10. 发明专利

JP2009059931A Nonvolatile semiconductor storage device 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：JP2009059931A
公开(公告)日：2009-03-19
申请号：JP2007226400
申请日：2007-08-31
申请人： Toshiba Corp , 株式会社東芝
发明人： TORIYAMA SHUICHI , MATSUZAWA KAZUYA
IPC分类号： H01L21/8247 , H01L21/76 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/0483 , H01L21/84 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/1203
摘要： PROBLEM TO BE SOLVED: To provide a NAND type nonvolatile semiconductor storage device which is improved in operation margin by providing a side electrode as an auxiliary electrode on a side surface of a channel region.
SOLUTION: The nonvolatile semiconductor storage device includes a semiconductor substrate 100 and a memory cell array which is provided to the semiconductor substrate 100 and has a plurality of series-connected memory cell transistors. Each memory cell transistor has a source region and a drain region formed on the semiconductor substrate 100, a channel region 211, a tunnel insulating film 102, a charge storage layer 104, a control insulating film 106, a control electrode 108, a side surface insulating film 110 provided on the side surface of the channel region 211, and two side electrodes 112 opposed to each other with the channel region 211 interposed therebetween. Then the side electrodes 112 are made common among the series-connected memory cell transistors.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：解决的问题：提供一种NAND型非易失性半导体存储器件，其通过在沟道区域的侧表面上提供侧电极作为辅助电极而提高了操作裕度。解决方案：非易失性半导体存储器件包括半导体衬底100和设置到半导体衬底100并具有多个串联存储单元晶体管的存储单元阵列。每个存储单元晶体管具有形成在半导体衬底100上的源区和漏区，沟道区211，隧道绝缘膜102，电荷存储层104，控制绝缘膜106，控制电极108，侧表面设置在通道区域211的侧表面上的绝缘膜110和彼此相对的两个侧电极112，其间具有沟道区域211。然后在串联连接的存储单元晶体管中使侧电极112共同。版权所有（C）2009，JPO＆INPIT

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