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1. 发明专利

JP2003297944A Semiconductor device and manufacturing method of the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2003297944A
公开(公告)日：2003-10-17
申请号：JP2002102847
申请日：2002-04-04
申请人： Toshiba Corp , Toshiba Microelectronics Corp , 東芝マイクロエレクトロニクス株式会社 , 株式会社東芝
发明人： SHIMIZU AKIRA , ARAI NORIHISA , ARAI FUMITAKA
IPC分类号： H01L21/28 , H01L21/768 , H01L21/8234 , H01L21/8247 , H01L27/088 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device having a high voltage driving system transistor, and a memory cell and a low voltage driving system transistor wherein junction breakdown strength between a source/drain electrode and a substrate does not disperse and short circuit is not generated.
SOLUTION: A first gate oxide film (5) of a high voltage driving system transistor and a second gate oxide film (7) of a memory cell transistor and a low voltage driving system transistor are formed on a silicon substrate (1). The film thickness of the first gate oxide film (5) in a region, wherein a contact plug 14 of a high voltage driving system transistor is formed, and the film thickness of the second gate oxide film (7) in a region, wherein a contact plug 15 of a memory cell transistor and a low voltage driving system transistor is formed, are made equal including the absence of films.
COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：提供具有高电压驱动系统晶体管的半导体器件，以及存储单元和低电压驱动系统晶体管，其中源/漏电极和衬底之间的结击穿强度不分散和短路电路不产生。解决方案：在硅衬底（1）上形成高电压驱动系统晶体管的第一栅极氧化膜（5）和存储单元晶体管和低电压驱动系统晶体管的第二栅氧化膜（7）。在形成高电压驱动系统晶体管的接触插塞14的区域中的第一栅极氧化膜（5）的膜厚以及第二栅极氧化膜（7）的区域的膜厚，其中，形成存储单元晶体管的接触插头15和低电压驱动系统晶体管，使其不含膜。版权所有（C）2004，JPO

2. 发明专利

JP2004297044A Semiconductor device and method of manufacturing same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2004297044A
公开(公告)日：2004-10-21
申请号：JP2004045170
申请日：2004-02-20
申请人： Toshiba Corp , Toshiba Microelectronics Corp , 東芝マイクロエレクトロニクス株式会社 , 株式会社東芝
发明人： ARAI NORIHISA , NAKANO TAKESHI , UENO HIROTAKA , SHIMIZU AKIRA
IPC分类号： H01L21/76 , H01L21/8234 , H01L21/8247 , H01L27/08 , H01L27/088 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To cut down the number of the PEP processes to enable reduction of the manufacturing cost by implementing field implantation and channel implantation successively making use of the same mask for ion implantation.
SOLUTION: Shallow trench isolations STIs 21 of a trench-embedded structure are formed in a semiconductor layer 20, and MOS element regions 22 formed of the semiconductor layer 20 surrounded by the STIs 21 are formed. A mask layer 25 having open portions 26 is formed on the semiconductor layer 20, each open portion 26 extending continuously over the entire area of each MOS element region 22 and the areas that partly cover the STIs 21 provided around the MOS element region of interest. First impurity ions are implanted onto the entire surface by way of the mask layer 25 such that the peak of the profile of the impurity ions is located in the semiconductor layer 20 directly below the bottom surface of the STI 21. Second impurity ions are implanted onto the entire surface by way of the mask layer 25 such that the peak of the profile of the impurity ions is located in the middle in the direction of the depth of the STI 21. The first and second impurity ions are activated.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了减少PEP工艺的数量，通过连续利用相同的掩模进行离子注入，实现场注入和沟道注入来降低制造成本。解决方案：在半导体层20中形成沟槽嵌入结构的浅沟槽隔离STI 21，并且形成由由STI 21包围的半导体层20形成的MOS元件区22。在半导体层20上形成具有开口部分26的掩模层25，每个开口部分26在每个MOS元件区域22的整个区域上连续地延伸，以及部分覆盖设置在感兴趣的MOS元件区域周围的STI 21的区域。第一杂质离子通过掩模层25注入到整个表面上，使得杂质离子的轮廓的峰位于STI 21的底表面正下方的半导体层20中。将第二杂质离子注入到通过掩模层25的整个表面，使得杂质离子的轮廓的峰位于STI 21的深度方向上的中间。第一和第二杂质离子被激活。版权所有（C）2005，JPO＆NCIPI

3. 发明专利

JP2003046062A Method for manufacturing semiconductor storage device 审中-公开
标题翻译：制造半导体存储器件的方法
公开(公告)号：JP2003046062A
公开(公告)日：2003-02-14
申请号：JP2001229409
申请日：2001-07-30
申请人： Toshiba Corp , Toshiba Microelectronics Corp , 東芝マイクロエレクトロニクス株式会社 , 株式会社東芝
发明人： ARAI NORIHISA , SHIRATA RIICHIRO , SHIMIZU AKIRA
IPC分类号： H01L21/8247 , H01L21/8238 , H01L27/092 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method for a semiconductor storage device where high reliability and high-performance characteristics of a memory transistor can be obtained.
SOLUTION: In this manufacturing method for a semiconductor storage device which has a cell array in which non-volatile memory transistors are arranged, and a peripheral circuit including a high-voltage system MISFET and a low-voltage system MISFET, a first gate oxide film 6 which is used for the high-voltage system MISFET is formed first on a silicon substrate 1. The first gate oxide film 6 is eliminated in the region of the cell array, and a second gate oxide film 8 turning, which serves as a tunnel insulating film of the memory transistors, is formed. A first polycrystalline silicon film 9 is deposited on the first and the second gate oxide films. In a region of the low- voltage system MISFET, the first polycrystalline silicon film and the first gate oxide film 6 are removed, and a third gate oxide film 13 of a low-voltage system MISFET is formed.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：提供一种可以获得存储晶体管的高可靠性和高性能特性的半导体存储装置的制造方法。解决方案：在具有其中布置有非易失性存储晶体管的单元阵列的半导体存储装置的制造方法以及包括高压系统MISFET和低电压系统MISFET的外围电路中，第一栅氧化膜首先在硅衬底1上形成用于高电压系统MISFET的第一栅极氧化膜6，第一栅极氧化膜6在电池阵列的区域中被去除，第二栅极氧化膜8转动，其用作隧道形成存储晶体管的绝缘膜。在第一和第二栅极氧化物膜上沉积第一多晶硅膜9。在低电压系统MISFET的区域中，除去第一多晶硅膜和第一栅极氧化膜6，形成低电压系统MISFET的第三栅极氧化膜13。

4. 发明专利

JP2005072040A Sample stage for electron beam exposure system 有权
标题翻译：电子束曝光系统的样品阶段
公开(公告)号：JP2005072040A
公开(公告)日：2005-03-17
申请号：JP2003208658
申请日：2003-08-25
申请人： Toshiba Corp , Toshiba Mach Co Ltd , 東芝機械株式会社 , 株式会社東芝
发明人： SUZUKI KIMIO , OTAKI SATOSHI , SHIMIZU AKIRA , YASUDA SATOSHI
IPC分类号： G03F7/20 , G03F1/76 , H01J37/20 , H01L21/027
摘要： PROBLEM TO BE SOLVED: To change the size of a retaining mechanism according to the size of a substrate to be treated without using any exclusive holders in the sample stage of an electron beam exposure system. SOLUTION: A mask blank 1 is retained by a retaining mechanism 10 arranged on a stage substrate 3. A first feed screw 21 and a connection shaft 23 are arranged in parallel with the X axis on the stage substrate 3, and a second feed screw 22 is arranged in parallel with the Y axis. The tip of the connection shaft 23 is connected at right angle to the rear end of the second feed screw 22 via toothed wheels. When changing the interval in the X-axis direction of the retaining mechanism 10, a drive shaft 24 is connected to the first feed screw 21 via coupling members 28 and 26, and the first feed screw 21 is driven. When changing the interval in the Y-axis direction of the retaining mechanism 10, the drive shaft 24 is connected to the second feed screw 22 via the coupling members 28, 27, and the second feed screw 22 is driven. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：根据待处理的基板的尺寸来改变保持机构的尺寸，而不使用电子束曝光系统的样品台中的任何专用的保持器。解决方案：掩模坯料1由布置在载物台基材3上的保持机构10保持。第一进料螺杆21和连接轴23与载片基材3上的X轴平行设置，第二进料螺杆进给螺杆22与Y轴平行设置。连接轴23的前端通过齿轮与第二进给螺杆22的后端成直角连接。当改变保持机构10的X轴方向的间隔时，驱动轴24经由联接构件28和26连接到第一进给螺杆21，并且第一进给螺杆21被驱动。当改变保持机构10的Y轴方向的间隔时，驱动轴24通过联接构件28,27连接到第二进给螺杆22，并且第二进给螺杆22被驱动。版权所有（C）2005，JPO＆NCIPI

5. 发明专利

JP2004319948A Non-volatile semiconductor memory 有权
公开(公告)号：JP2004319948A
公开(公告)日：2004-11-11
申请号：JP2003207566
申请日：2003-08-14
申请人： Toshiba Corp , 株式会社東芝
发明人： ARAI FUMITAKA , SHIRATA RIICHIRO , SHIMIZU AKIRA , MATSUNAGA YASUHIKO , SAKUMA MAKOTO
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , G11C16/0483 , H01L27/115 , H01L27/11524 , H01L29/7883
摘要： PROBLEM TO BE SOLVED: To reduce parasitic capacity at a periphery of a floating gate, to increase capacity between a control gate and the floating gate, to reduce writing voltage and to realize high integration and high speed. SOLUTION: The floating gate FG is formed on a semiconductor substrate 11 through a gate insulating film GI. Diffusion layers as source or drain regions are formed in the semiconductor substrates 11 positioned on both sides of the floating gate FG. First and second control gates CG driving the floating gate through an inter-gate insulating film IGI are formed on both sides of the floating gate, which correspond to the diffusion layers. COPYRIGHT: (C)2005,JPO&NCIPI

6. 发明专利

JP2004185660A Semiconductor storage device 有权
公开(公告)号：JP2004185660A
公开(公告)日：2004-07-02
申请号：JP2002347800
申请日：2002-11-29
申请人： Toshiba Corp , 株式会社東芝
发明人： SHIMIZU AKIRA , ARAI FUMITAKA , SHIRATA RIICHIRO
IPC分类号： G11C16/04 , G11C11/34 , G11C16/02 , G11C16/06 , G11C16/08 , H01L21/8247 , H01L27/10 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/08 , G11C16/0483 , H01L27/105 , H01L27/115
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor storage device which can suppress the leakage current between the transfer gate transistors and can be miniaturized as well. SOLUTION: The semiconductor storage device includes first, second and third memory cell transistors which can rewrite information electrically and addresses in row orientations are consecutive. One ends of the electric current passages of the first, second and third forwarding transistors are connected with control electrodes of the first, second, and third memory cell transistors respectively. The other ends of the electric current passages of the first, second, and third transfer transistors are impressed with a writing voltage, a path voltage, and a first voltage respectively. The path voltage is lower than the writing voltage and the first voltage is lower than the path voltage. A first control section impresses a first ON voltage to make the first transfer transistor conductive to the gate of the first forwarding transistor. A second control section impresses the second ON voltage different from the first ON voltage to the gates of the second and third transistors in order to make the second and third transfer transistor conductive. COPYRIGHT: (C)2004,JPO&NCIPI

7. 发明专利

JP2004186252A Nonvolatile semiconductor memory device and its manufacturing method 有权
标题翻译：非线性半导体存储器件及其制造方法
公开(公告)号：JP2004186252A
公开(公告)日：2004-07-02
申请号：JP2002348933
申请日：2002-11-29
申请人： Toshiba Corp , 株式会社東芝
发明人： ARAI FUMITAKA , SHIRATA RIICHIRO , YAEGASHI TOSHITAKE , SHIMIZU AKIRA , MATSUNAGA YASUHIKO , ICHIGE MASAYUKI , MEGURO TOSHITAKA
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , H01L27/115
摘要： PROBLEM TO BE SOLVED: To realize the construction of a cell made fine and the lowering of write electric potential.
SOLUTION: A device isolation insulating layer 16 has an STI structure with its upper surface being flat. A floating gate electrode 13 is disposed in a recessed part formed with protruded parts of the device isolating insulating layer 16. Two opposite side surfaces of the floating gate electrode 13 are covered with the device isolation insulating layer 16. The upper surface of the floating gate electrode 13 and the upper surface of the device isolation insulating layer 16 are substantially coincident with each other. An inter-gate insulating layer 17 is formed on the floating gate electrode 13 and the device isolation insulating layer 16. A base of the inter-gate insulating layer 17 is flat. A control gate electrode 18 is disposed on the inter-gate insulating layer 17.
COPYRIGHT: (C)2004,JPO&NCIPI
摘要翻译：要解决的问题：实现电池的制造精细和写入电位的降低。解决方案：器件隔离绝缘层16具有其上表面平坦的STI结构。浮置栅电极13设置在形成有器件隔离绝缘层16的突出部分的凹部中。浮置栅电极13的两个相对的侧表面被器件隔离绝缘层16覆盖。浮动栅极的上表面电极13和器件隔离绝缘层16的上表面基本上彼此重合。栅极间绝缘层17形成在浮栅电极13和器件隔离绝缘层16上。栅间绝缘层17的基底是平坦的。控制栅电极18设置在栅间绝缘层17上。版权所有（C）2004，JPO＆NCIPI

8. 发明专利

JP2007027776A Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：JP2007027776A
公开(公告)日：2007-02-01
申请号：JP2006239550
申请日：2006-09-04
申请人： Toshiba Corp , 株式会社東芝
发明人： ARAI FUMITAKA , SHIRATA RIICHIRO , SHIMIZU AKIRA , MATSUNAGA YASUHIKO , SAKUMA MAKOTO
IPC分类号： H01L21/8247 , G11C16/04 , H01L21/28 , H01L27/115 , H01L29/423 , H01L29/49 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To resolve the problem that it is difficult to reduce the parasitic capacity of the periphery of a floating gate and and increase capacity between a control gate and the floating gate and it is difficult to reduce write voltage and carry out high integration and speeding up. SOLUTION: In a nonvolatile semiconductor memory device, a groove is formed in a semiconductor substrate 11. A floating gate FG is formed on the bottom portion of the groove via a gate insulating film GI. A diffusion layer S/D for use as a source or drain region is formed in the semiconductor substrate 11 corresponding to both sides of the floating gate FG. First and second control gates CGs for driving the floating gate FG via the insulating film between the gates IGI are formed on both side walls of the floating gate FG positioned on both diffusion layers S/Ds. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：解决问题：为了解决难以降低浮置栅极的周边的寄生电容并且增加控制栅极和浮置栅极之间的电容的问题，并且难以降低写入电压并携带高集成度和加速。解决方案：在非易失性半导体存储器件中，在半导体衬底11中形成沟槽。浮栅FG经由栅极绝缘膜GI形成在沟槽的底部。用作源极或漏极区域的扩散层S / D形成在对应于浮置栅极FG两侧的半导体衬底11中。在位于两个扩散层S / Ds上的浮置栅极FG的两个侧壁上形成用于通过栅极IGI之间的绝缘膜驱动浮置栅极FG的第一和第二控制栅极CG。版权所有（C）2007，JPO＆INPIT

9. 发明专利

JP2004185659A Nonvolatile semiconductor storage device and its data writing method 有权
公开(公告)号：JP2004185659A
公开(公告)日：2004-07-02
申请号：JP2002347799
申请日：2002-11-29
申请人： Toshiba Corp , 株式会社東芝
发明人： ARAI FUMITAKA , SHIMIZU AKIRA
IPC分类号： G11C16/02 , G11C16/04 , G11C16/06 , G11C16/10 , G11C16/34
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/3454
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor storage device capable of highly accurately controlling a threshold value width while executing a high-speed writing operation. SOLUTION: This device is provided with a memory cell (NAND cell) including a nonvolatile memory cell transistor (MC) connected to each of a plurality of wirings (BL), a wordline (WL) for connecting the gate electrodes of cell transistors arrayed along a row direction (ROW), and a driving circuit 2 connected to each of the plurality of wirings. The driving circuit is provided with a detection circuit (21) for detecting the threshold value of the cell transistor in a verifying operation, a storage circuit (22) for storing the detected threshold value, and a potential setting circuit (23) for setting the wirings (BL) to 3 or more potentials (V1 to V3) in a writing operation subsequent to the verifying operation. COPYRIGHT: (C)2004,JPO&NCIPI

10. 发明专利

JPH0550227A BRAZING IRON TIP 失效
公开(公告)号：JPH0550227A
公开(公告)日：1993-03-02
申请号：JP18260791
申请日：1991-07-23
申请人： TOSHIBA CORP
发明人： SHIMIZU AKIRA
IPC分类号： B23K3/02 , B23K101/42 , H05K3/34
摘要： PURPOSE:To stably execute brazing of minute parts or repair of brazing by providing the function for adjusting brazing filler metal quantity utilizing a capillary phenomenon in the tip part of a soldering iron tip used for brazing. CONSTITUTION:A soldering iron tip 10 for brazing is constituted of a heating machine 11 provided to the vicinity of the tip and a soldering iron tip 12 having a metallic plating part. In the tip part of the soldering iron tip 12, one piece or plural pieces of thin grooves 13 are provided in the direction of the heating machine 11. By this groove 13, as for a brazing filler metal melted by the soldering iron tip 12, force for remaining by a capillary phenomenon is added to force for remaining in the soldering iron tip 12 by surface tension, therefore, it can be suppressed that the brazing filler metal flows out to a metallic tube to be joined from the soldering iron tip 12.

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