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1. 发明专利

JPH11274455A Solid-state image pick up device 失效
标题翻译：固态图像拾取器件
公开(公告)号：JPH11274455A
公开(公告)日：1999-10-08
申请号：JP7055898
申请日：1998-03-19
申请人： Toshiba Corp , 株式会社東芝
发明人： YAMAGUCHI TETSUYA , NOZAKI HIDETOSHI , IHARA HISANORI , INOUE IKUKO , YAMASHITA HIROSHI , NARUSE HIROSHI , IGUMA HIDEMIKI , SHIBATA HIDENORI , MAKABE AKIRA , ABE SEIGO , NOMACHI EIKO , SHIOYAMA YOSHIYUKI , HORI MIKIKO
IPC分类号： H01L27/146 , H04N5/335 , H04N5/361 , H04N5/365 , H04N5/369 , H04N5/3745
CPC分类号： H01L27/14609
摘要： PROBLEM TO BE SOLVED: To provide a solid-state image pick up device, which accurately reads out a signal charge from a photodiode even when a voltage is reduced, and also reduces generation of leak current.
SOLUTION: A solid-state image pick up device is provided with a read transistor. The react transistor has an (n) type semiconductor layer 2, which is formed on a semiconductor substrate for photoelectric conversion, a (p) type semiconductor layer 3, which is formed to shield the upper surface of the (n) type semiconductor layer 2; and an (n) type semiconductor layer 4, which is formed on the surface of the semiconductor substrate and is connected electrically with the (n) type semiconductor layer 2 for reading a signal charge from the (n) type semiconductor layer 2. The read transistor reads the signal charge from the (n) type semiconductor layer 2 through the (n) type semiconductor layer 4. The (p) type semiconductor layer 3 and the (n) type semiconductor layer 4 are formed at a prescribed interval so as not to bring the depletion layer formed by the (p) type semiconductor layer 3 into contact with the depletion layer formed by the (n) type semiconductor layer 4.
COPYRIGHT: (C)1999,JPO
摘要翻译：要解决的问题：提供一种固态图像拾取装置，其即使在电压降低时也准确地从光电二极管读出信号电荷，并且还减少了泄漏电流的产生。解决方案：固态图像拾取装置具有读取晶体管。反应晶体管具有形成在用于光电转换的半导体衬底上的（n）型半导体层2，形成为（n）型半导体层2的上表面的（p）型半导体层3 ; 和（n）型半导体层4，其形成在半导体衬底的表面上并与（n）型半导体层2电连接，用于从（n）型半导体层2读取信号电荷。晶体管通过（n）型半导体层4从（n）型半导体层2读取信号电荷。（p）型半导体层3和（n）型半导体层4以规定的间隔形成为不使由（p）型半导体层3形成的耗尽层与由（n）型半导体层4形成的耗尽层接触。

2. 发明专利

JP2013089816A Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2013089816A
公开(公告)日：2013-05-13
申请号：JP2011230008
申请日：2011-10-19
申请人： Toshiba Corp , 株式会社東芝
发明人： NOMACHI EIKO
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/522
CPC分类号： H01L23/481 , H01L21/3065 , H01L21/3213 , H01L21/76898 , H01L24/10 , H01L24/11 , H01L29/0649 , H01L2924/13091 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To achieve a highly-reliable BSV-type TSV.SOLUTION: A semiconductor device according to one embodiment has: a semiconductor substrate 11 having a front face and a rear face and on whose front face side an LSI is formed; an insulating layer 12 formed in the semiconductor substrate 11 on the front face side and having an opening; a conductive layer 13 formed on the opening on the front face side and connected with the LSI; and a via 17 connected with the conductive layer 13 via the opening from the rear face side. A size of the via 17 is larger than the size of the opening in a range from the rear face to an interface between the semiconductor substrate 11 and the insulating layer 12, and equal to the size of the opening in the opening.
摘要翻译：要解决的问题：实现高可靠性BSV型TSV。解决方案：根据一个实施例的半导体器件具有：具有前表面和后表面并且其正面侧形成LSI的半导体衬底11; 形成在前表面侧的半导体衬底11中并具有开口的绝缘层12; 形成在正面侧的开口部并与LSI连接的导电层13; 以及从后面侧经由开口与导电层13连接的通孔17。通孔17的尺寸大于从半导体衬底11和绝缘层12之间的背面到界面的范围内的开口尺寸，并且等于开口中的开口的尺寸。版权所有（C）2013，JPO＆INPIT

3. 发明专利

JP2012156167A Magnetic random access memory and method of manufacturing the same 审中-公开
标题翻译：磁性随机存取存储器及其制造方法
公开(公告)号：JP2012156167A
公开(公告)日：2012-08-16
申请号：JP2011011357
申请日：2011-01-21
申请人： Toshiba Corp , 株式会社東芝
发明人： NOMACHI EIKO
IPC分类号： H01L27/105 , H01L21/8246 , H01L29/82 , H01L43/08 , H01L43/12
CPC分类号： H01L27/228 , G11C11/161 , G11C11/1659
摘要： PROBLEM TO BE SOLVED: To provide a magnetic random access memory in which a current for magnetization inversion is sufficiently secured in a magnetoresistive effect element, and a method of manufacturing the same.SOLUTION: A magnetic random access memory according to an embodiment includes a silicon substrate. A gate electrode is embedded in a surface portion of the silicon substrate, and a gate insulating film is embedded in the silicon substrate so as to cover the gate electrode. A first diffusion layer and a second diffusion layer are provided on the surface portion of the silicon substrate so as to sandwich the gate insulating film and the gate electrode therebetween. A storage element including at least a magnetization recording layer, a non-magnetic layer, and a magnetization reference layer is provided on the second diffusion layer.
摘要翻译：解决的问题：提供一种在磁阻效应元件中充分确保用于磁化反转的电流的磁性随机存取存储器及其制造方法。解决方案：根据实施例的磁性随机存取存储器包括硅衬底。栅电极被嵌入在硅衬底的表面部分中，并且栅极绝缘膜嵌入硅衬底中以覆盖栅电极。在硅衬底的表面部分设置第一扩散层和第二扩散层，以将栅极绝缘膜和栅电极夹在其间。至少包括磁记录层，非磁性层和磁化参考层的存储元件设置在第二扩散层上。版权所有（C）2012，JPO＆INPIT

4. 发明专利

JP2009111074A Semiconductor substrate 审中-公开
标题翻译：半导体基板
公开(公告)号：JP2009111074A
公开(公告)日：2009-05-21
申请号：JP2007280564
申请日：2007-10-29
申请人： Toshiba Corp , 株式会社東芝
发明人： ITOKAWA HIROSHI , MIZUSHIMA ICHIRO , NOMACHI EIKO , TSUNASHIMA YOSHITAKA
IPC分类号： H01L21/76 , H01L21/02 , H01L21/20 , H01L27/12
CPC分类号： H01L29/045 , H01L21/02381 , H01L21/02433 , H01L21/02532 , H01L21/02609 , H01L21/02667 , H01L21/26506 , H01L21/823412 , H01L21/823481 , H01L21/84
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor substrate having a HOT structure capable of being put to original practical use by suppressing generation of a crystal defect at an interface of crystal regions of a functional substrate having mutually different crystal orientations when the semiconductor substrate having the HOT structure is manufactured using a DSB substrate.
SOLUTION: The semiconductor substrate includes: a silicon support substrate with a first crystal orientation; a silicon functional substrate which is formed directly on the silicon support substrate and which has a first crystalline region with a crystal orientation different from the first crystal orientation of the silicon support substrate and a second crystalline region with a crystal orientation different from the first crystal orientation of the silicon support substrate; and a defect creation-preventing region between the first crystalline region and the second crystalline region so as to be at least reached to a main surface of the silicon support substrate.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：为了提供具有HOT结构的半导体衬底，当半导体的半导体衬底具有相互不同的晶体取向的功能衬底的晶体区域的界面处时，抑制了晶体缺陷的产生，使用DSB基板制造具有HOT结构的基板。解决方案：半导体衬底包括：具有第一晶体取向的硅支撑衬底; 硅功能基板，其直接形成在硅支撑基板上，并且具有晶体取向不同于硅支撑基板的第一晶体取向的第一晶体区域和具有不同于第一晶体取向的晶体取向的第二晶体区域的硅支撑基板; 以及第一结晶区域和第二结晶区域之间的缺陷产生防止区域，以至少到达硅支撑基板的主表面。版权所有（C）2009，JPO＆INPIT

5. 发明专利

JP2007165550A Semiconductor device and its manufacturing method 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2007165550A
公开(公告)日：2007-06-28
申请号：JP2005359259
申请日：2005-12-13
申请人： Toshiba Corp , 株式会社東芝
发明人： NOMACHI EIKO
IPC分类号： H01L21/768 , H01L21/8234 , H01L27/088
CPC分类号： H01L29/7843
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device capable of improving transistor characteristics, and to provide its manufacturing method.
SOLUTION: The semiconductor device includes an insulating film 300 which is formed so as to fill a slit formed between side-wall insulating films 50 formed on the side faces of gate electrodes 40 adjacent to each other; a stress liner film 320 which is formed on a semiconductor substrate 10, the gate electrodes, the side-wall insulating film; and the insulating film; an interlayer insulating film 330 formed on the stress liner film; and a contact plug 350 formed so as to penetrate from the surface of the interlayer insulating film to the surface of the semiconductor substrate or the gate electrode.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供能够提高晶体管特性的半导体器件，并提供其制造方法。解决方案：半导体器件包括绝缘膜300，其形成为填充形成在彼此相邻的栅电极40的侧面上的侧壁绝缘膜50之间的狭缝; 形成在半导体衬底10上的应力衬垫膜320，栅电极，侧壁绝缘膜; 和绝缘膜; 形成在应力衬垫膜上的层间绝缘膜330; 以及形成为从层间绝缘膜的表面到半导体衬底或栅电极的表面的接触插塞350。版权所有（C）2007，JPO＆INPIT

6. 发明专利

JP2013258385A Resistance change memory and method for manufacturing the same 审中-公开
标题翻译：电阻变化记忆及其制造方法
公开(公告)号：JP2013258385A
公开(公告)日：2013-12-26
申请号：JP2012135191
申请日：2012-06-14
申请人： Toshiba Corp , 株式会社東芝
发明人： NOMACHI EIKO
IPC分类号： H01L27/105 , H01L21/8246 , H01L45/00 , H01L49/00
CPC分类号： H01L45/12 , H01L27/228 , H01L27/2436 , H01L27/2463 , H01L43/12 , H01L45/04 , H01L45/1233 , H01L45/16 , H01L45/1675
摘要： PROBLEM TO BE SOLVED: To miniaturize a memory cell and reduce manufacturing cost thereof.SOLUTION: A resistance change memory according to an embodiment includes a plurality of resistor change elements R arranged in a first direction with a first space SP1 therebetween and arranged in a second direction with a second space SP2 therebetween. A second conductive layer 14 constituting a first bit line is disposed on a side wall of a first insulation layer 13 and on a side wall of a first conductive layer 12, a width in the first direction is half or more of the first space SP1, and a width in the second direction is less than half of the second space SP2. A second insulation layer 15 is arranged on a side wall of the second conductive layer 14, and does not fill the second space SP2. A third conductive layer 16 constituting a second bit line fills the second space SP2.
摘要翻译：要解决的问题：为了使存储单元小型化并降低其制造成本。解决方案：根据实施例的电阻变化存储器包括多个电阻器改变元件R，其在第一方向上布置有第一空间SP1并且布置在第二方向上方向，其间具有第二空间SP2。构成第一位线的第二导电层14设置在第一绝缘层13的侧壁上，第一导电层12的侧壁上，第一方向上的宽度为第一空间SP1的一半以上，并且第二方向上的宽度小于第二空间SP2的一半。第二绝缘层15布置在第二导电层14的侧壁上，并且不填充第二空间SP2。构成第二位线的第三导电层16填充第二空间SP2。

7. 发明专利

JP2013140891A Manufacturing method of magnetoresistance effect element 审中-公开
标题翻译：磁阻效应元件的制造方法
公开(公告)号：JP2013140891A
公开(公告)日：2013-07-18
申请号：JP2012000671
申请日：2012-01-05
申请人： Toshiba Corp , 株式会社東芝
发明人： NOMACHI EIKO
IPC分类号： H01L21/8246 , H01L27/105 , H01L29/82 , H01L43/08 , H01L43/12
CPC分类号： H01L43/12 , H01L27/20 , H01L27/222 , H01L27/228 , H01L41/06 , H01L41/12 , H01L41/20 , H01L41/22 , H01L41/27 , H01L41/297 , H01L41/332 , H01L41/47 , H01L43/02 , H01L43/08
摘要： PROBLEM TO BE SOLVED: To reduce dimensional variations and achieve high density.SOLUTION: According to one embodiment, a manufacturing method of a magnetoresistance effect element is provided. In the manufacturing method of the magnetoresistance effect element, a first ferromagnetic layer 30, a tunnel barrier layer 31, and a second ferromagnetic layer 32 are sequentially formed on the substrate. A conductive hard mask 33 is formed on the second ferromagnetic layer 32, and the hard mask is patterned. A hard layer 34 is formed on a side surface of the hard mask. The second ferromagnetic layer, the tunnel barrier layer, and the first ferromagnetic layer are processed by ion beam etching conducted from a diagonal direction with the hard mask and the hard layer used as a mask. The hard layer has the etching rate of the ion beam etching that is smaller than that of the hard mask.
摘要翻译：要解决的问题：减小尺寸变化并实现高密度。解决方案：根据一个实施例，提供了一种磁阻效应元件的制造方法。在磁阻效应元件的制造方法中，第一铁磁层30，隧道势垒层31和第二铁磁层32依次形成在基板上。在第二铁磁层32上形成导电硬掩模33，并对硬掩模进行图案化。硬质层34形成在硬掩模的侧表面上。第二铁磁层，隧道势垒层和第一铁磁层通过用硬掩模和硬层作为掩模从对角线方向进行的离子束蚀刻进行处理。硬质层具有小于硬掩模的蚀刻速率。

8. 发明专利

JP2010212507A Method of manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：JP2010212507A
公开(公告)日：2010-09-24
申请号：JP2009058364
申请日：2009-03-11
申请人： Toshiba Corp , 株式会社東芝
发明人： NOMACHI EIKO
IPC分类号： H01L21/8238 , H01L21/28 , H01L21/76 , H01L27/092 , H01L29/423 , H01L29/49
摘要： PROBLEM TO BE SOLVED: To suppress a shape defect in a gate electrode, in a different conductivity type transistor having a different laminated structure.
SOLUTION: The method of manufacturing a semiconductor device includes the processes of: forming a gate insulating film 3 on a semiconductor substrate 1 in a first region having an MISFET of a first conductivity type and in a second region having an MISFET of a second conductivity type; forming a first metal material layer 4 on the gate insulating film in the first region; forming second gate electrodes 7a, 7b made of a second metal material layer 7 on the first metal material layer in the first region and on the gate insulating film in the second region respectively; forming first side wall insulating films 11a, 11b on side surfaces of the second gate electrodes in the first region and second region respectively; and forming a first gate electrode 4a by processing the first metal material layer in the first region using the first side wall insulating films as masks.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：在具有不同层压结构的不同导电型晶体管中抑制栅电极中的形状缺陷。解决方案：制造半导体器件的方法包括以下处理：在半导体衬底1上形成具有第一导电类型的MISFET的第一区域中的栅绝缘膜3和具有第一导电类型的MISFET的第二区域第二导电类型; 在第一区域中的栅极绝缘膜上形成第一金属材料层4; 分别在第一区域的第一金属材料层上形成由第二金属材料层7制成的第二栅极电极7a，7b，并在第二区域中形成栅极绝缘膜; 在第一区域和第二区域中分别在第二栅电极的侧表面上形成第一侧壁绝缘膜11a，11b; 以及通过使用第一侧壁绝缘膜作为掩模，在第一区域中处理第一金属材料层，形成第一栅电极4a。版权所有（C）2010，JPO＆INPIT

9. 发明专利

JP2007207816A Semiconductor device and method of manufacturing semiconductor device 审中-公开
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：JP2007207816A
公开(公告)日：2007-08-16
申请号：JP2006021998
申请日：2006-01-31
申请人： Toshiba Corp , 株式会社東芝
发明人： NISHIMURA HISASHI , HARAKAWA HIDEAKI , NOMACHI EIKO
IPC分类号： H01L29/78 , H01L21/28 , H01L21/283 , H01L21/768 , H01L23/522
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which can easily increase the thickness of a stress application film, and to provide a method of manufacturing the semiconductor device.
SOLUTION: The semiconductor device is provided with, as shown in Fig. 2H, a semiconductor substrate 101, a gate insulation film 102A, a gate electrode 102B, a gate side wall insulation film, an interlayer insulation film 112, a wiring layer, an interlayer connection part, and a stress application film. The stress application film has a first section arranged between the semiconductor substrate 101 and the interlayer insulation film 112, a second section arranged between the gate electrode 102B and the interlayer insulation film 112, a third section arranged between the gate side wall insulation film 104 and the interlayer insulation film 112, and a fourth section arranged between the inner face of a through-hole and the interlayer connection part. The stress appliction film applies stress to the semiconductor substrate.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：解决的问题：提供一种可以容易地增加应力施加膜的厚度的半导体器件，并且提供一种制造半导体器件的方法。解决方案：半导体器件如图1所示。 2H，半导体基板101，栅极绝缘膜102A，栅极电极102B，栅极侧壁绝缘膜，层间绝缘膜112，布线层，层间连接部以及应力施加膜。应力施加膜具有布置在半导体衬底101和层间绝缘膜112之间的第一部分，布置在栅电极102B和层间绝缘膜112之间的第二部分，布置在栅极侧壁绝缘膜104和层间绝缘膜112和布置在通孔的内表面和层间连接部之间的第四部分。应力应力膜对半导体衬底施加应力。版权所有（C）2007，JPO＆INPIT

10. 发明专利

JPH11274459A Solid-state image pickup device 失效
标题翻译：固态图像拾取器件
公开(公告)号：JPH11274459A
公开(公告)日：1999-10-08
申请号：JP7197598
申请日：1998-03-20
申请人： Toshiba Corp , 株式会社東芝
发明人： INOUE IKUKO , NOZAKI HIDETOSHI , IHARA HISANORI , YAMAGUCHI TETSUYA , YAMASHITA HIROSHI , MAKABE AKIRA , NOMACHI EIKO , HORI MIKIKO , NAKAMURA NOBUO
IPC分类号： H01L27/146 , H04N5/335 , H04N5/365 , H04N5/367 , H04N5/369 , H04N5/3745
摘要： PROBLEM TO BE SOLVED: To reduce white scratches, fixed pattern noise and random noise, by reducing a leak current generated on a substrate interface.
SOLUTION: A solid-state image pick up device is provided with a photoelectric conversion part 20 formed on a semiconductor substrate, an amplifying transistor 2-1-1 modulated by signal charges accumulated by photoelectric conversion of the photoelectric conversion part 20, and read transistors (21, 22) which read a signal current from the amplifying transistor 2-1-1 from the photoelectric conversion part 20. The difference between the gate voltage of the read transistor and the reverse potential of the semiconductor substrate, namely, read potential Φ, is reduced, by setting the threshold value of the read transistor at a high value, within a range wherein reading of the signal charge from the photoelectric converting part 20 can be performed.
COPYRIGHT: (C)1999,JPO
摘要翻译：要解决的问题：通过减少在基板界面上产生的泄漏电流来减少白色划痕，固定图案噪声和随机噪声。解决方案：固态摄像装置设置有形成在半导体衬底上的光电转换部分20，由光电转换部分20的光电转换累积的信号电荷调制的放大晶体管2-1-1和读出的晶体管（21,22），其从光电转换部20读取来自放大晶体管2-1-1的信号电流。读取晶体管的栅极电压与半导体衬底的反向电位之间的差即读取电位Φ 通过将读取晶体管的阈值设定为高值，在可以执行从光电转换部20读取信号电荷的范围内被减小。

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