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1. 发明专利

JP2011009526A Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2011009526A
公开(公告)日：2011-01-13
申请号：JP2009152350
申请日：2009-06-26
申请人： Toshiba Corp , 株式会社東芝
发明人： IGUMA HIDEMIKI
IPC分类号： H01L29/78 , H01L21/8238 , H01L27/092
摘要： PROBLEM TO BE SOLVED: To improve characteristics of an element as well as controllability of threshold by applying cSiGe and eSiGe to a pMOS transistor and preventing the occurrence of a damage in a gate insulation film.SOLUTION: The semiconductor device, which uses SiGe in a channel and a source-drain area of a pMOS transistor, includes: a first SiGe layer 205 that is formed on a part of an Si substrate 202 and becomes a channel of the pMOS transistor; a gate electrode 208 that is formed on the first SiGe layer 205 with a gate insulation film 206 in between; a second SiGe layer 214 that is embedded in the source-drain area of the pMOS transistor and is projected to the side of the channel at a position where the end on the side of channel is deeper than the surface of the substrate; and an Si layer 222 that is inserted between the first and second SiGe layers 205 and 214 on the surface of the substrate in a manner to separate the first and second SiGe layers 205 and 214.
摘要翻译：要解决的问题：通过将cSiGe和eSiGe应用于pMOS晶体管并防止在栅极绝缘膜中发生损伤，从而提高元件的特性以及阈值的可控性。解决方案：半导体器件在SiGe中使用沟道和源极 - 漏极区域包括：形成在Si衬底202的一部分上并成为pMOS晶体管的沟道的第一SiGe层205; 在第一SiGe层205上形成有栅极绝缘膜206的栅电极208; 第二SiGe层214，其被嵌入在pMOS晶体管的源极 - 漏极区域中并且在沟道侧的端部比衬底的表面更深的位置处被投影到沟道侧; 以及以分离第一和第二SiGe层205和214的方式插入在基板的表面上的第一和第二SiGe层205和214之间的Si层222。

2. 发明专利

JP2015056478A 半導体装置および半導体装置の製造方法审中-公开
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：JP2015056478A
公开(公告)日：2015-03-23
申请号：JP2013188290
申请日：2013-09-11
申请人：株式会社東芝 , Toshiba Corp
发明人： YOTSUMOTO SATOSHI , FUJII KOTARO , IGUMA HIDEMIKI , MINO AKIRA
IPC分类号： H01L21/8247 , H01L21/28 , H01L21/336 , H01L21/768 , H01L27/10 , H01L27/115 , H01L29/417 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11529 , H01L27/11524
摘要：【課題】異なる種類のパターンの底部の位置をほぼ同じに揃える。【解決手段】本実施形態の半導体装置は、複数のメモリセルトランジスタと、ソース側選択ゲートトランジスタと、ドレイン側選択ゲートトランジスタとを有するNANDセルユニットを複数備える。ドレイン側選択ゲートトランジスタのドレイン側選択ゲート電極間の間隔は、ソース側選択ゲートトランジスタのソース側選択ゲート電極間の間隔よりも広い。ドレイン側ライナーシリコン窒化膜のうちの半導体基板の上面上の部分の膜厚は、ソース側ライナーシリコン窒化膜のうちの半導体基板の上面上の部分の膜厚よりも薄い。【選択図】図9
摘要翻译：要解决的问题：粗略地对准不同类型的图案的底部部分的位置。解决方案：半导体器件包括多个NAND单元单元，其包含多个存储单元晶体管，源极侧选择栅极晶体管，漏极侧选择栅极晶体管。漏极侧选择栅极晶体管的漏极侧选择栅电极之间的间隔宽于源极侧选择栅极晶体管的源极侧选择栅电极之间的间隔。在漏极侧衬里氮化硅膜中的半导体衬底的上表面上的部分的膜厚比在源极侧衬里氮化硅膜中的半导体衬底的上表面的部分薄。

3. 发明专利

JP2014036203A Method of manufacturing nonvolatile storage, and nonvolatile storage 审中-公开
标题翻译：非易失存储器的制造方法和非易失存储器
公开(公告)号：JP2014036203A
公开(公告)日：2014-02-24
申请号：JP2012178331
申请日：2012-08-10
申请人： Toshiba Corp , 株式会社東芝
发明人： IGUMA HIDEMIKI , YAMAMOTO KAZUHIKO
IPC分类号： H01L27/105 , H01L45/00 , H01L49/00
CPC分类号： H01L45/1608 , H01L27/2436 , H01L27/2481 , H01L45/04 , H01L45/085 , H01L45/1226 , H01L45/146 , H01L45/147 , H01L45/1616 , H01L45/1675
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a nonvolatile storage capable of suppressing variation in memory characteristics, and to provide the nonvolatile storage.SOLUTION: A method of manufacturing a nonvolatile storage includes the steps of: making the sizes of a mask in the lamination direction and a second direction crossing a first direction relatively longer than the size of a laminate in the second direction, or making the cross-sectional size of a hole in the mask relatively shorter than the cross-sectional size of a hole in the laminate; and removing a resistance change layer formed on the bottom of a plurality of grooves or a plurality of holes. In the step for making the size of a mask in the second direction relatively longer than the size of a laminate in the second direction, or making the cross-sectional size of a hole in the mask relatively shorter than the cross-sectional size of a hole in the laminate, the mask is subjected to oxidation treatment or ion implantation, or the laminate is subjected to wet etching.
摘要翻译：要解决的问题：提供一种制造能够抑制存储特性变化的非易失性存储器的方法，并提供非易失性存储器。解决方案：一种制造非易失性存储器的方法包括以下步骤：使掩模的尺寸层叠方向和与第二方向相比长于第一方向的第二方向的第二方向，或者使掩模中的孔的横截面尺寸比第二方向上的孔的横截面尺寸短层压板; 并且去除形成在多个凹槽或多个孔的底部上的电阻变化层。在使第二方向上的掩模的尺寸比第二方向上的层叠体的尺寸相对长的步骤中，或者使掩模中的孔的横截面尺寸比a的截面尺寸短将该掩模进行氧化处理或离子注入，或对层叠体进行湿式蚀刻。

4. 发明专利

JP2013157511A Storage device 有权
标题翻译：储存设备
公开(公告)号：JP2013157511A
公开(公告)日：2013-08-15
申请号：JP2012018006
申请日：2012-01-31
申请人： Toshiba Corp , 株式会社東芝
发明人： MATSUSHITA DAISUKE , FUJII AKISUKE , NISHI YOSHIFUMI , TAKASHIMA AKIRA , ISHIKAWA TAKAYUKI , MIYAGAWA HIDENORI , HAIMOTO TAKASHI , ARAYASHIKI YUSUKE , IGUMA HIDEMIKI
IPC分类号： H01L27/105 , H01L45/00 , H01L49/00
摘要： PROBLEM TO BE SOLVED: To provide a storage device with small variation of a switching operation.SOLUTION: A storage device according to an embodiment comprises a first electrode, a second electrode, and a resistance change film connected between the first electrode and the second electrode. In the first electrode, a matrix made of a conductive material contains metal with cohesive energy lower than that of the conductive material. A concentration of the metal at a center part in a width direction of the first electrode is higher that of the metal at both ends in a width direction of the first electrode.
摘要翻译：要解决的问题：提供一种开关操作变化小的存储装置。解决方案：根据实施例的存储装置包括连接在第一电极和第二电极之间的第一电极，第二电极和电阻变化膜。在第一电极中，由导电材料制成的基体含有内聚能低于导电材料的金属。在第一电极的宽度方向上的中心部分处的金属的浓度高于第一电极的宽度方向两端的金属的浓度。

5. 发明专利

JP2013201405A Nonvolatile memory device 审中-公开
标题翻译：非易失性存储器件
公开(公告)号：JP2013201405A
公开(公告)日：2013-10-03
申请号：JP2012070408
申请日：2012-03-26
申请人： Toshiba Corp , 株式会社東芝
发明人： IGUMA HIDEMIKI
IPC分类号： H01L27/105 , H01L45/00 , H01L49/00
CPC分类号： H01L27/2481 , G11C13/0011 , G11C2213/71 , G11C2213/77 , H01L45/085 , H01L45/1266 , H01L45/145 , H01L45/1675
摘要： PROBLEM TO BE SOLVED: To provide a highly reliable nonvolatile memory device.SOLUTION: The nonvolatile memory device of an embodiment includes: a first wiring layer; a second wiring layer intersecting the first wiring layer; and a first memory layer provided at a position where the first wiring layer and the second wiring layer intersect each other. The first memory layer is in contact with the first wiring layer, and the first wiring layer is capable of supplying metal ions to the first memory layer.
摘要翻译：要解决的问题：提供高度可靠的非易失性存储装置。实施例的非易失性存储装置包括：第一布线层; 与第一布线层相交的第二布线层; 以及设置在第一布线层和第二布线层相交的位置的第一存储层。第一存储层与第一布线层接触，第一布线层能够向第一存储层提供金属离子。

6. 发明专利

JP2013197523A Memory device 有权
标题翻译：内存设备
公开(公告)号：JP2013197523A
公开(公告)日：2013-09-30
申请号：JP2012066109
申请日：2012-03-22
申请人： Toshiba Corp , 株式会社東芝
发明人： MATSUSHITA DAISUKE , FUJII AKISUKE , NISHI YOSHIFUMI , TAKASHIMA AKIRA , ISHIKAWA TAKAYUKI , MIYAGAWA HIDENORI , HAIMOTO TAKASHI , ARAYASHIKI YUSUKE , IGUMA HIDEMIKI
IPC分类号： H01L27/105 , H01L45/00 , H01L49/00
摘要： PROBLEM TO BE SOLVED: To provide a memory device with excellent retention property for a state.SOLUTION: A memory device according to an embodiment comprises: a first electrode; a second electrode; a variable resistance film between the first electrode and the second electrode and contacting with both of them. The first electrode includes metal in matrix containing a conductive material, in which the metal has lower cohesive energy than that of the conductive material. The metal in the first electrode has greater density at an end part in the width direction than at a center part in the width direction.
摘要翻译：要解决的问题：提供一种具有优异的状态保持性的存储器件。解决方案：根据实施例的存储器件包括：第一电极; 第二电极; 第一电极和第二电极之间的可变电阻膜并与它们两者接触。第一电极包括含有导电材料的基体中的金属，其中金属具有比导电材料低的内聚能。第一电极中的金属在宽度方向上的端部处的宽度方向上的宽度方向上的中心部分处的密度更大。

7. 发明专利

JPH11274455A Solid-state image pick up device 失效
标题翻译：固态图像拾取器件
公开(公告)号：JPH11274455A
公开(公告)日：1999-10-08
申请号：JP7055898
申请日：1998-03-19
申请人： Toshiba Corp , 株式会社東芝
发明人： YAMAGUCHI TETSUYA , NOZAKI HIDETOSHI , IHARA HISANORI , INOUE IKUKO , YAMASHITA HIROSHI , NARUSE HIROSHI , IGUMA HIDEMIKI , SHIBATA HIDENORI , MAKABE AKIRA , ABE SEIGO , NOMACHI EIKO , SHIOYAMA YOSHIYUKI , HORI MIKIKO
IPC分类号： H01L27/146 , H04N5/335 , H04N5/361 , H04N5/365 , H04N5/369 , H04N5/3745
CPC分类号： H01L27/14609
摘要： PROBLEM TO BE SOLVED: To provide a solid-state image pick up device, which accurately reads out a signal charge from a photodiode even when a voltage is reduced, and also reduces generation of leak current.
SOLUTION: A solid-state image pick up device is provided with a read transistor. The react transistor has an (n) type semiconductor layer 2, which is formed on a semiconductor substrate for photoelectric conversion, a (p) type semiconductor layer 3, which is formed to shield the upper surface of the (n) type semiconductor layer 2; and an (n) type semiconductor layer 4, which is formed on the surface of the semiconductor substrate and is connected electrically with the (n) type semiconductor layer 2 for reading a signal charge from the (n) type semiconductor layer 2. The read transistor reads the signal charge from the (n) type semiconductor layer 2 through the (n) type semiconductor layer 4. The (p) type semiconductor layer 3 and the (n) type semiconductor layer 4 are formed at a prescribed interval so as not to bring the depletion layer formed by the (p) type semiconductor layer 3 into contact with the depletion layer formed by the (n) type semiconductor layer 4.
COPYRIGHT: (C)1999,JPO
摘要翻译：要解决的问题：提供一种固态图像拾取装置，其即使在电压降低时也准确地从光电二极管读出信号电荷，并且还减少了泄漏电流的产生。解决方案：固态图像拾取装置具有读取晶体管。反应晶体管具有形成在用于光电转换的半导体衬底上的（n）型半导体层2，形成为（n）型半导体层2的上表面的（p）型半导体层3 ; 和（n）型半导体层4，其形成在半导体衬底的表面上并与（n）型半导体层2电连接，用于从（n）型半导体层2读取信号电荷。晶体管通过（n）型半导体层4从（n）型半导体层2读取信号电荷。（p）型半导体层3和（n）型半导体层4以规定的间隔形成为不使由（p）型半导体层3形成的耗尽层与由（n）型半导体层4形成的耗尽层接触。

8. 发明专利

JP2009277849A Semiconductor device and manufacturing method thereof 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2009277849A
公开(公告)日：2009-11-26
申请号：JP2008127024
申请日：2008-05-14
申请人： Toshiba Corp , 株式会社東芝
发明人： IGUMA HIDEMIKI
IPC分类号： H01L29/78 , H01L21/314 , H01L21/768 , H01L21/8238 , H01L23/522 , H01L27/092 , H01L29/786
CPC分类号： H01L21/823412 , H01L21/76832 , H01L21/76837 , H01L21/823807 , H01L29/7843 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To avoid a void generated in a CESL film or an interlayer insulating film on the CESL film even when a thick CESL film is used, and to achieve a high driving current and high reliability. SOLUTION: A semiconductor apparatus has a MOSFET in which a gate electrode 13 is formed on a semiconductor substrate 10 via a gate insulating film 12, and a source/drain region 18 is formed on a substrate surface on both sides of the gate electrode 13. The semiconductor apparatus has: a sidewall insulating film 17 formed on a side part of a gate length direction of the gate; an alloy layer 19 formed on the source/drain region 18; a taper adjusting insulating film 21 provided at the side part of the sidewall insulating film 17 and which has a taper angle to the substrate surface in a cross section of the gate length direction smaller than that of the sidewall insulating film 17; a stress-causing insulating film 22 for giving distortion to a channel, which is formed so as to cover the gate, the sidewall insulating film 17, and the taper adjusting insulating film 21; and an interlayer insulating film 25 formed on the stress-causing insulating film 22. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了避免CESL膜上的CESL膜或层间绝缘膜中产生的空穴，即使使用厚CESL膜，并且实现高驱动电流和高可靠性。解决方案：半导体器件具有MOSFET，其中通过栅极绝缘膜12在半导体衬底10上形成栅电极13，并且在栅极两侧的衬底表面上形成源/漏区18 电极13.半导体装置具有：形成在栅极的栅极长度方向的侧部的侧壁绝缘膜17; 形成在源极/漏极区域18上的合金层19; 设置在侧壁绝缘膜17的侧部并且在栅极长度方向的截面小于侧壁绝缘膜17的截面中与基板表面成锥角的锥形调节绝缘膜21; 用于对形成为覆盖栅极的沟道，侧壁绝缘膜17和锥形调节绝缘膜21施加变形的应力导致绝缘膜22; 以及形成在应力导致绝缘膜22上的层间绝缘膜25.权利要求：（C）2010，JPO＆INPIT

9. 发明专利

JP2008205378A Semiconductor device and its production process 有权
标题翻译：半导体器件及其生产工艺
公开(公告)号：JP2008205378A
公开(公告)日：2008-09-04
申请号：JP2007042394
申请日：2007-02-22
申请人： Toshiba Corp , 株式会社東芝
发明人： IGUMA HIDEMIKI
IPC分类号： H01L21/8244 , H01L21/28 , H01L21/336 , H01L21/768 , H01L21/8234 , H01L27/088 , H01L27/11 , H01L29/78 , H01L29/786
CPC分类号： H01L27/1104 , H01L27/11 , H01L29/6656 , H01L29/66636 , H01L29/7833 , H01L29/7834
摘要： PROBLEM TO BE SOLVED: To restrain junction leakage caused by a shared contact coming into contact with an extension, and to achieve contact without increasing an area and raising a resistance.
SOLUTION: A semiconductor device having a shared contact has a gate electrode 104 formed via a gate insulating film 103 on a semiconductor substrate 101, side wall insulating films 105, 106 formed in both side surfaces of the gate electrode 104 and a semiconductor layer 119 doped with impurities which is formed in a portion wherefrom the semiconductor substrate 101 and the gate insulating film 103 are removed by removing at least one of surface parts adjacent to both sides of the gate electrode 104 of the substrate 101 until it attains below the gate electrode 104 over a lower part of the side wall insulating films 105, 106 and removing the gate insulating film 103 exposed in the removed part.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了抑制由与扩展部接触的共用接触引起的结漏，并且在不增加面积和提高电阻的情况下实现接触。解决方案：具有共享接触的半导体器件具有通过半导体衬底101上的栅极绝缘膜103形成的栅电极104，形成在栅电极104的两个侧表面中的侧壁绝缘膜105,106和半导体通过除去与衬底101的栅电极104的两侧相邻的表面部分中的至少一个的表面部分，形成在半导体衬底101和栅极绝缘膜103的部分中形成的杂质的层119直到达到低于栅电极104在侧壁绝缘膜105,106的下部，并且去除暴露在去除部分中的栅极绝缘膜103。版权所有（C）2008，JPO＆INPIT

10. 发明专利

JP2008091536A Semiconductor apparatus, and manufacturing method thereof 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：JP2008091536A
公开(公告)日：2008-04-17
申请号：JP2006269333
申请日：2006-09-29
申请人： Toshiba Corp , 株式会社東芝
发明人： IGUMA HIDEMIKI
IPC分类号： H01L21/8238 , H01L21/768 , H01L23/522 , H01L27/092
CPC分类号： H01L21/823412 , H01L21/823468 , H01L21/823475 , H01L21/823481 , H01L29/6653 , H01L29/6656 , H01L29/78 , H01L29/7843 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor apparatus and a manufacturing method thereof capable of giving a sufficient stress to a channel part of a transistor. SOLUTION: This semiconductor apparatus comprises a first semiconductor device with carriers as electrons and a second semiconductor device with carriers as holes which are formed on a semiconductor substrate (101), and a first insulating film (108) having a tensile stress to the first semiconductor device and a second insulating film (111) having a compressive stress to the second semiconductor device which are on the source/drain regions and the gate electrodes of the first and the second semiconductor devices. At least parts of sidewall spacers of the gate electrodes of the first and the second semiconductor devices are removed, and at least one of the first and the second insulating films does not block between the gate electrodes of the first and the second semiconductor devices. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够向晶体管的沟道部分产生足够的应力的半导体装置及其制造方法。解决方案：该半导体装置包括具有载流子作为电子的第一半导体器件和形成在半导体衬底（101）上的作为空穴的载体的第二半导体器件，以及第一绝缘膜（108），其具有拉伸应力第一半导体器件和在第一和第二半导体器件的源极/漏极区域和栅电极上具有对第二半导体器件的压缩应力的第二绝缘膜（111）。除去第一和第二半导体器件的栅电极的侧壁间隔物的至少一部分，并且第一绝缘膜和第二绝缘膜中的至少一个不会阻挡在第一和第二半导体器件的栅电极之间。版权所有（C）2008，JPO＆INPIT

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