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1. 发明专利

JP2013172083A Manufacturing method of semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：JP2013172083A
公开(公告)日：2013-09-02
申请号：JP2012036377
申请日：2012-02-22
申请人： Toshiba Corp , 株式会社東芝
发明人： KITAMURA MASAYUKI , SAKATA ATSUKO , WADA MAKOTO , YAMAZAKI YUICHI , KATAGIRI MASAYUKI , KAJITA AKIHIRO , SAKAI TADASHI , SAKUMA HISASHI , MIZUSHIMA ICHIRO
IPC分类号： H01L21/3205 , C23C16/26 , H01L21/28 , H01L21/285 , H01L21/768 , H01L23/532
CPC分类号： H01L21/02373 , H01L21/76846 , H01L21/76855 , H01L21/76858 , H01L21/76861 , H01L21/76876 , H01L23/53276 , H01L2221/1089 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device including a high quality graphene having a lower resistivity than the conventional and fewer crystal defects as much as possible.SOLUTION: The manufacturing method of a semiconductor device comprises a step of forming a promoter layer having a face-centered cubic structure above the surface of a semiconductor substrate. The promoter layer is formed so that the (111) plane of the face-centered cubic structure is oriented in parallel with the surface of a semiconductor substrate. A catalyst layer having a face-centered cubic structure is formed on the promoter layer. The catalyst layer is formed so that the (111) plane of the face-centered cubic structure is oriented in parallel with the surface of a semiconductor substrate. A portion of the promoter layer in contact with the catalyst layer has a face-centered cubic structure. The catalyst layer is subjected to oxidation treatment and then subjected to reduction treatment thus planarizing the exposed surface of the catalyst layer. Finally, a graphene layer is formed on the catalyst layer.
摘要翻译：要解决的问题：提供一种半导体器件的制造方法，该半导体器件包括尽可能多的具有比常规的更低的电阻率和更少的晶体缺陷的高质量石墨烯。解决方案：半导体器件的制造方法包括以下步骤：启动子层，其在半导体衬底的表面上方具有面心立方结构。形成促进剂层使得面心立方结构的（111）面与半导体衬底的表面平行取向。在促进剂层上形成具有面心立方结构的催化剂层。形成催化剂层，使得面心立方结构的（111）面与半导体衬底的表面平行取向。与催化剂层接触的助催化剂层的一部分具有面心立方结构。对催化剂层进行氧化处理，然后进行还原处理，从而使催化剂层的暴露表面平坦化。最后，在催化剂层上形成石墨烯层。

2. 发明专利

JP2005228882A Semiconductor device and its manufacturing method 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2005228882A
公开(公告)日：2005-08-25
申请号：JP2004035403
申请日：2004-02-12
申请人： Toshiba Corp , 株式会社東芝
发明人： KAJITA AKIHIRO
IPC分类号： H01L21/768 , H01L21/00 , H01L21/82 , H01L21/822 , H01L21/8242 , H01L23/525 , H01L27/04 , H01L27/10 , H01L27/108 , H01L31/062
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which varies the resistance of a fuse element without melting a fuse wiring even by irradiation of laser beams and has the fuse element of which functions are controlled, and to provide its manufacturing method. SOLUTION: The semiconductor device comprises a semiconductor substrate, a first wiring layer formed on the semiconductor substrate, a second wiring layer formed at the upper part of the first wiring layer, a plug serving as at least a fuse element for connecting the first wiring layer with the second wiring layer, and an opening provided in a part of an insulating film formed on the second wiring layer corresponding to the plug. Further, the semiconductor device can include an opening gap formed in the plug by irradiation of laser beams on the opening. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：解决的问题：提供一种半导体器件，其即使通过激光束的照射也不熔化保险丝布线来改变熔丝元件的电阻，并且具有控制功能的熔丝元件，并提供其制造方法。解决方案：半导体器件包括半导体衬底，形成在半导体衬底上的第一布线层，形成在第一布线层的上部的第二布线层，用作至少保险丝元件的插头，用于将具有第二布线层的第一布线层和设置在形成在对应于插头的第二布线层上的绝缘膜的一部分中的开口。此外，半导体器件可以包括通过在开口处照射激光束而形成在插头中的开口间隙。版权所有（C）2005，JPO＆NCIPI

3. 发明专利

JPH08316233A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH08316233A
公开(公告)日：1996-11-29
申请号：JP17805395
申请日：1995-06-21
申请人： TOSHIBA CORP
发明人： HASUNUMA MASAHIKO , ITOU SACHIYO , SHIMAMURA KEIZO , KANEKO HISAFUMI , HAYASAKA NOBUO , TSUTSUMI JUNSEI , KAJITA AKIHIRO , WADA JUNICHI , OKANO HARUO
IPC分类号： H01L21/28 , H01L21/203 , H01L21/31 , H01L21/3205 , H01L21/768 , H01L23/52
摘要： PURPOSE: To form a buried interconnection which is dense and whose reliability is high by a method wherein a heating treatment is executed in such a way that a groove or a contact hole is filled by the reflow of a conductive film, the conductive film in parts other than an electrode-interconnection formation region is then polished and removed and an electrode is formed. CONSTITUTION: When an electrode interconnection is formed on a semiconductor substrate, a conductive film 8 which is composed mainly of Cu, Ag or the like is formed on a semiconductor substrate face 9 in which a groove 6 and a contact hole are formed in advance in a region in which the electrode interconnection is to be formed, a heat treatment is executed while an oxidizing gas is being supplied, and the groove 6 and the contact hole are filled by the reflow of the conductive film 8. Then, the conductive film 8 other than that is polished and removed, and the electrode interconnection is formed. In addition, in a heating treatment, a reducing gas is supplied in addition to an oxidizing gas, and the conductive film 8 is made to flow or reflow by using a local oxidation- reduction reaction so as to be buried.

4. 发明专利

JPH08288242A MANUFACTURE OF SEMICONDUCTOR DEVICE AND CHEMICAL VAPOR DEPOSITION APPARATUS 失效
公开(公告)号：JPH08288242A
公开(公告)日：1996-11-01
申请号：JP2407396
申请日：1996-02-09
申请人： TOSHIBA CORP
发明人： KAJITA AKIHIRO , KANEKO HISAFUMI
IPC分类号： C23C16/02 , C23C16/18 , C23C16/44 , C23C16/448 , C23C16/455 , H01L21/285 , H01L21/3205 , H01L21/768 , H01L23/52 , H01L21/205
摘要： PURPOSE: To deposit a Cu thin film having a very high purity and good adhesion to a base layer, using the CVD method by feeding a raw material gas composed of a Cu-containing organic metal compd. and oxidizing gas, stopping feeding the oxidizing gas with leaving the raw material gas being fed to form a thin film contg. Cu as a main component. CONSTITUTION: On a Si wafer 11 a Si oxide film 12 and TiN thin film 13 are formed and exposed to the atmospheric air to form a natural oxide film. This substrate is set in a reaction chamber, a Cu source gas composed of Cu hexafluoroacetylacetone trimethylvinylsilane is fed to the substrate and at the same time an O2 gas is fed from a separate piping system from that of the synthesis gas to do the low pressure heat CVD. For about 30sec. the source gas and O2 gas are fed at the same time to form a Cu film 15, the O2 gas is stopped from feeding, the heat CVD is continued by the source gas only for about 90sec. to form a Cu film 16. Thus, a high-purity and low-resistance Cu thin film superior in adhesion to a base layer can be formed.

5. 发明专利

JPH06267954A FORMING METHOD OF METALLIC THIN FILM 失效
公开(公告)号：JPH06267954A
公开(公告)日：1994-09-22
申请号：JP5401193
申请日：1993-03-15
申请人： TOSHIBA CORP
发明人： KAJITA AKIHIRO , KANEKO HISAFUMI , WADA JUNICHI , OKUDE SHINICHIRO , TOYODA HIROSHI
IPC分类号： C23C16/04 , H01L21/285 , H01L21/3205 , H01L23/52
摘要： PURPOSE:To enable a metallic thin film pertinent to the formation of fine wiring, etc., to be easily formed by a method wherein insulator layers in different material qualities are formed after specific pattern on a base substance layer comprising an insulator so that single crystalline metallic layers may be selectively formed on the base substance layer with no insulating layer formed thereon. CONSTITUTION:After the formation of an amorphous Sin. film 2a on an Si wafer 1 surface, an amorphous SiN film 3 and another amorphous SiO2 film 2b are successively deposition-formed. Next, the deposition-formed amorphous SiO2 film 2b is photoetched away to shapedly provide aperture parts 4 for exposing parts of the amorphous SiN 3. Later, Al thin films 5a are selectively deposition-grown on the exposed amorphous SiN film 3 (in the aperture parts 4) by CVD process. During this CVD growing process, the Al thin films 5a are not to be deposited on the amorphous SiO2 film 2b but to be selectively buried in the aperture parts 4 only wherein the amorphous SiN films 3 is exposed.

6. 发明专利

JP2012080006A Graphene wiring and method for manufacturing the same 有权
标题翻译：石墨线及其制造方法
公开(公告)号：JP2012080006A
公开(公告)日：2012-04-19
申请号：JP2010225777
申请日：2010-10-05
申请人： Toshiba Corp , 株式会社東芝
发明人： SAITO TATSURO , WADA MAKOTO , KAJITA AKIHIRO , SAKATA ATSUKO
IPC分类号： H01L23/52 , C01B31/02 , H01L21/28 , H01L21/285 , H01L21/3205
CPC分类号： H01L21/76885 , H01L21/76834 , H01L21/76849 , H01L21/76876 , H01L21/76877 , H01L21/76879 , H01L21/76883 , H01L23/53276 , H01L2221/1094 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To improve electrical characteristics in a wiring structure.SOLUTION: A method for manufacturing graphene wiring comprises the steps of: forming a wiring groove 30 in an insulating film 13; forming a catalyst film 14 on the entire surface in the wiring groove; and forming, on the catalyst layer in the wiring groove, a graphene layer 16 composed of a plurality of graphene sheets 16a-16e laminated in a direction perpendicular to the bottom of the wiring groove.
摘要翻译：要解决的问题：提高布线结构中的电气特性。解决方案：一种用于制造石墨烯布线的方法包括以下步骤：在绝缘膜13中形成布线槽30; 在布线槽的整个表面上形成催化剂膜14; 并且在布线槽的催化剂层上形成由在与布线槽的底部垂直的方向上层叠的多个石墨烯片16a-16e构成的石墨烯层16。版权所有（C）2012，JPO＆INPIT

7. 发明专利

JP2010056227A Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2010056227A
公开(公告)日：2010-03-11
申请号：JP2008218353
申请日：2008-08-27
申请人： Toshiba Corp , 株式会社東芝
发明人： NAWATA HIDEFUMI , KAJITA AKIHIRO , TSUCHIYA TAKANORI , SUGIMAE KIKUKO
IPC分类号： H01L21/768 , H01L21/28 , H01L21/3205 , H01L21/8247 , H01L23/522 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L23/53295 , H01L21/76802 , H01L21/76816 , H01L21/76877 , H01L21/76883 , H01L23/5226 , H01L23/53238 , H01L23/53266 , H01L27/105 , H01L27/11526 , H01L27/11573 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device in which an increase in resistance of wiring is suppressed, and to provide a method of manufacturing the same. SOLUTION: The semiconductor device includes: an impurity diffusion layer 11a of a memory cell portion 6 and an impurity diffusion layer 11b of a peripheral circuit portion 7, the impurity diffusion layers being provided on a surface of a semiconductor substrate 10 and having upper surfaces forming substantially the same plane; insulating films 12 and 14 formed covering the upper surfaces of the impurity diffusion layers 11a and 11b and having nearly constant film thicknesses; a metal plug 13a formed in the insulating films 12 and 14 and connected to the impurity diffusion layer 11a; a metal plug 13b formed in the insulating film 12, formed shorter than the metal plug 13a, and connected to the impurity diffusion layer 11b; metal wiring 15a connected to an upper end portion of the metal plug 13a and having an upper surface buried so as to be flush with the insulating film 14; and metal wiring 15b connected to an upper end portion of the metal plug 13b and having an upper surface buried so as to be flush with the insulating film 14. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供抑制布线电阻增加的半导体器件，并提供其制造方法。解决方案：半导体器件包括：存储单元部分6的杂质扩散层11a和外围电路部分7的杂质扩散层11b，杂质扩散层设置在半导体衬底10的表面上并具有上表面形成基本相同的平面; 形成为覆盖杂质扩散层11a，11b的上表面并具有几乎恒定的膜厚的绝缘膜12和14; 形成在绝缘膜12和14中并连接到杂质扩散层11a的金属插塞13a; 形成在绝缘膜12中的金属插塞13b，形成为比金属插塞13a短，并且与杂质扩散层11b连接; 与金属插塞13a的上端部连接并具有与绝缘膜14齐平的上表面的金属配线15a; 以及与金属插塞13b的上端部连接并具有与绝缘膜14齐平的上表面的金属布线15b。（C）2010，JPO＆INPIT

8. 发明专利

JP2009283569A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2009283569A
公开(公告)日：2009-12-03
申请号：JP2008132289
申请日：2008-05-20
申请人： Toshiba Corp , 株式会社東芝
发明人： WADA MAKOTO , KAJITA AKIHIRO , AZUMA KAZUYUKI
IPC分类号： H01L21/768 , H01L21/8247 , H01L23/522 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L23/522 , H01L21/76816 , H01L21/76849 , H01L21/76852 , H01L21/76885 , H01L21/76895 , H01L23/5226 , H01L27/10885 , H01L27/10888 , H01L27/11517 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device improving resolution of lithography and optical contrast and reducing a chip area in a memory element region part. SOLUTION: The semiconductor device includes a plurality of bit lines 10 which are repetitively arranged in a memory element region at the same line width and same pitch, a plurality of shunt lines 30 which are formed in the same layer as the plurality of bit lines 10 in parallel in the memory element region and are disposed at the same line width and same pitch as the plurality of bit lines 10 and an upper layer contact plug 34 disposed to be connected from an upper layer side of the plurality of shunt lines 30 over the plurality of shunt lines 30. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种提高光刻分辨率和光学对比度并减少存储元件区域部分中的芯片面积的半导体器件。解决方案：半导体器件包括多个位线10，它们以相同的线宽和相同的间距重复地布置在存储元件区域中，多个分流线30形成在与多个位线10在存储元件区域中并联并且以与多个位线10相同的线宽度和相同的间距设置，并且上层接触插塞34设置成从多个分流线的上层侧连接 30多个分流线30。版权所有（C）2010，JPO＆INPIT

9. 发明专利

JP2009130291A Method of manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：JP2009130291A
公开(公告)日：2009-06-11
申请号：JP2007306533
申请日：2007-11-27
申请人： Toshiba Corp , 株式会社東芝
发明人： WADA MAKOTO , AZUMA KAZUYUKI , KAJITA AKIHIRO
IPC分类号： H01L21/027 , G03F7/20 , G03F7/40 , H01L21/3065 , H01L21/3205
摘要： PROBLEM TO BE SOLVED: To form a micropattern without using a high-resolution exposure system.
SOLUTION: In the formation of a micropattern for forming an interconnecting line, a bridging film 6 having a size of (1/2)d is formed on both side faces of a resist film 5 having a size of 2d to form a line pattern having a size of 3d that is composed of the resist film 5 and the bridging film 6 and a space pattern having a minimum size of d. A first opening having the minimum size of d is formed on a second hard mask 4, using the resist film 5 and the bridging film 6 as a mask. The first opening is filled with a backfill material 7. On the second hard mask 4 and the backfill material 7, a bridging film 9 having the size of (1/2)d is formed on both side faces of a resist film 8 having the size of 2d that is shifted by the size 2d relative to the pattern of the resist film 5 to form a line pattern having the size of 3d that is composed of the resist film 8 and the bridging film 9 and a space pattern having the minimum size of d. A second opening having the minimum size of d is formed on the second hard mask 4, using the resist film 8 and the bridging film 9 as a mask.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：在不使用高分辨率曝光系统的情况下形成微图案。解决方案：在形成互连线的微图案的形成中，在尺寸为2d的抗蚀剂膜5的两个侧面上形成具有（1/2）d尺寸的桥接膜6，以形成具有由抗蚀剂膜5和桥接膜6组成的尺寸3d的线图案和具有最小尺寸d的空间图案。使用抗蚀剂膜5和桥接膜6作为掩模，在第二硬掩模4上形成具有最小尺寸d的第一开口。第一开口填充有回填材料7.在第二硬掩模4和回填材料7上，具有尺寸为（1/2）d的桥接膜9形成在具有（1/2）d的抗蚀剂膜8的两个侧面上，尺寸2d相对于抗蚀剂膜5的图案移动尺寸2d以形成由抗蚀剂膜8和桥接膜9组成的尺寸为3d的线图案和具有最小尺寸的空间图案的d。使用抗蚀剂膜8和桥接膜9作为掩模，在第二硬掩模4上形成具有最小尺寸d的第二开口。版权所有（C）2009，JPO＆INPIT

10. 发明专利

JP2005142262A Semiconductor device and manufacturing method therefor 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2005142262A
公开(公告)日：2005-06-02
申请号：JP2003375432
申请日：2003-11-05
申请人： Toshiba Corp , 株式会社東芝
发明人： KAJITA AKIHIRO
IPC分类号： H01L23/522 , H01L21/4763 , H01L21/768 , H01L23/00 , H01L23/52 , H01L23/532 , H01L23/58
CPC分类号： H01L23/585 , H01L23/53238 , H01L23/53295 , H01L23/562 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor chip having a structure in which the cracking and film peeling of an interlayer insulating film in a dicing process are not generated in an element forming region, and to provide a manufacturing method for the chip.
SOLUTION: The semiconductor chip 100 has a semiconductor substrate 10 and a semiconductor element formed on the surface of the substrate 10. The chip 100 further has laminated films being composed of a plurality of the interlayer insulating films 12 to 52 deposited on the substrate 10 so as to coat the element, and containing a hollow trench 70 formed in the vertical direction to the surface of the substrate 10 to at least a part of the outer edge of the substrate 10.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种半导体芯片，其具有在元件形成区域中不产生切割工艺中的层间绝缘膜的裂纹和膜剥离的结构，并且提供用于芯片的制造方法。解决方案：半导体芯片100具有形成在基板10的表面上的半导体基板10和半导体元件。芯片100还具有由多个层叠绝缘膜12〜52构成的层叠膜，基板10，以便涂覆元件，并且包含在基板10的表面的垂直方向上形成的中空沟槽70至基板10的外边缘的至少一部分。版权所有（C）2005 ，JPO＆NCIPI

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