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1. 发明专利

JPH08148549A ELECTROSTATIC CHUCK DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH08148549A
公开(公告)日：1996-06-07
申请号：JP31133594
申请日：1994-11-22
申请人： TOMOEGAWA PAPER CO LTD , TOSHIBA CORP
发明人： MATSUNAGA TADAO , MATSUSHITA TAKAYA , HATTORI KEI
IPC分类号： B23Q3/15 , H01L21/683 , H01L21/68
摘要： PURPOSE: To provide an electrostatic chuck device which improves heat conductivity, increases a suction area, improves suction force and eliminates unevenness of a wafer mounting surface. CONSTITUTION: An electrostatic chuck device is formed by laminating an adhesive layer 2, an electrode layer 3 formed of a metal deposition film or a plating film and an electric insulation layer 4 with a surface whereon a suction object is installed one by one on a metallic substrate 1. The electrostatic chuck device is manufactured by a process for forming an electrode layer comprised of a metal deposition film or a plating film in one surface of a heat resistance film, a process for providing a photoresist layer to a surface of an electrode layer, performing pattern exposure, developing it and carrying out etching treatment, a process for providing a semi-hardened adhesive layer to a surface of an etched electrode layer, a process for punching a formed laminate sheet to a form of a metallic substrate and a process for laminating a metallic substrate and a laminate sheet through the adhesive layer and hardening it.

2. 发明专利

JP2005116801A Method for manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：JP2005116801A
公开(公告)日：2005-04-28
申请号：JP2003349540
申请日：2003-10-08
申请人： Toshiba Corp , 株式会社東芝
发明人： OMURA MITSUHIRO , KANEKO HISAFUMI , MATSUSHITA TAKAYA , KATANO MAKIKO , ITO AKIKO
IPC分类号： H01L21/00 , H01L21/26 , H01L21/302 , H01L21/306 , H01L21/3065 , H01L21/311 , H01L21/324 , H01L21/44 , H01L21/461 , H01L21/4763 , H01L21/768
CPC分类号： H01L21/76838 , H01L21/02046 , H01L21/31116
摘要： PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device with corrosion of its copper layer suppressed, even when a semiconductor wafer with its semiconductor substrate having a copper layer covered by an insulating film is subjected to dry etching in a fluorocarbon gas for partially removing the insulating film for the exposure of the copper layer surface, and the semiconductor wafer is then exposed to the atmosphere before a surface treatment.
SOLUTION: The insulating film (14) is partially removed by dry etching in a fluorocarbon gas for the exposure of the copper layer (13), and then the copper layer (13) is subjected to a nitrogen plasma treatment.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了提供一种抑制其铜层腐蚀的半导体器件的制造方法，即使将具有被绝缘膜覆盖的铜层的半导体衬底的半导体晶片在用于部分去除用于暴露铜层表面的绝缘膜的碳氟化合物气体，然后在表面处理之前将半导体晶片暴露于大气中。解决方案：通过在用于曝光铜层（13）的碳氟化合物气体中的干法蚀刻部分去除绝缘膜（14），然后对铜层（13）进行氮等离子体处理。版权所有（C）2005，JPO＆NCIPI

3. 发明专利

JPH05343693A 失效
公开(公告)号：JPH05343693A
公开(公告)日：1993-12-24
申请号：JP14521692
申请日：1992-06-05
申请人： TOSHIBA CORP
发明人： HIURA YOHEI , YAMADA SEIJI , MATSUSHITA TAKAYA
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PURPOSE:To make it possible to protect the boundary part between a source part and a channel part under gates by the sidewalls of cells in the case of removal of a field oxide film at the time of formation of the source part in the manufacture of a tunnel current erase type EPROM, to lessen an irregularity in the thickness of a gate oxide film and to inhibit an irregularity in the erase characteristics of the cells. CONSTITUTION:In a tunnel current erase type EPROM, floating gates 114 and control gates 115 are formed on a P-type silicon wafer 101 consisting a memory cell main part and a source region 112 and drain regios 113 are formed in the wafer 101. When such the EPROM is manufactured, an etching condition to generate a polymer is used at the time of a selective etching for removing a field oxide film in a SAS technique and the boundary parts between the source part and the gates are made to protect by making this polymer adhere on the sidewalls of two-layer gates. Thereby, a generation of a step in the surface of the silicon substrate is prevented at the boundary between the source part and a channel part under the gates and an irregularity in the erase characteristics of cells is inhibited.

4. 发明专利

JPH08213372A ETCHING METHOD 失效
公开(公告)号：JPH08213372A
公开(公告)日：1996-08-20
申请号：JP4353295
申请日：1995-02-07
申请人： TOKYO ELECTRON LTD , TOSHIBA CORP
发明人： INASAWA KOICHIRO , OKAMOTO SUSUMU , HAYASHI HISATAKA , MATSUSHITA TAKAYA
IPC分类号： H05H1/46 , C23F4/00 , C30B33/12 , H01L21/302 , H01L21/3065 , H01L21/311
摘要： PURPOSE: To improve selectivity of a shoulder part, by shortening discharge continuance time in the case of etching, and increasing existence ratio of active seed ions whose selection ratio is high. CONSTITUTION: In an etching method which performs plasma etching treatment to an object W to be treated while introducing etching gas in a treatment chamber 16, the etching gas is composed of mixed gas containing at least C4 F8 , and CO, and the etching gas stays in the treatment chamber for a time long enough that, e.g. the selection ratio of an etching layer and its substratum layer at a shoulder part becomes larger than or equal to 10. Thereby, the discharge continuance time is shortened, the progress of dissociation of the etching gas is accelerated, and the existence ratio of active seed ions whose selectivity is high can be incresed.

5. 发明专利

JPH05166762A ETCHING 失效
公开(公告)号：JPH05166762A
公开(公告)日：1993-07-02
申请号：JP33107791
申请日：1991-12-16
申请人： TOKYO ELECTRON LTD , TOSHIBA CORP
发明人： TAWARA YOSHIFUMI , OGASAWARA MASAHIRO , MATSUSHITA TAKAYA
IPC分类号： C23F4/00 , H01L21/302 , H01L21/3065
摘要： PURPOSE:To etch a thin film with an improved selection ratio without damage to its base silicon. CONSTITUTION:A process chamber 2 is maintained at a predetermined vacuum by an exhaust mechanism 15. In the chamber, a semiconductor wafer 5 to be etched is exposed to gases supplied through many holes in an upper electrode 3 from an Ar source 7, a CHF3 source 8, a CF4 source 9, and CO source 10a and 10b.

6. 发明专利

JP2011129737A Method of manufacturing semiconductor storage device, and semiconductor storage device 审中-公开
标题翻译：制造半导体存储器件的方法和半导体存储器件
公开(公告)号：JP2011129737A
公开(公告)日：2011-06-30
申请号：JP2009287323
申请日：2009-12-18
申请人： Toshiba Corp , 株式会社東芝
发明人： YAHASHI KATSUNORI , KUNIYA TAKUJI , MATSUSHITA TAKAYA , TANIGUCHI SHUICHI , KAWAI BURANDO
IPC分类号： H01L27/10 , H01L45/00 , H01L49/00
CPC分类号： H01L27/0688 , H01L27/2409 , H01L27/2418 , H01L27/2481 , H01L45/085 , H01L45/1233 , H01L45/147 , H01L45/1675
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor storage device configured such that loss of an etching mask is small and residues which may cause a short circuit between adjacent memory cells are not left, and to provide the semiconductor storage device.
SOLUTION: A columnar memory cell is formed by: forming a first groove extending in a first direction and forming first wiring 103 after forming a first wiring layer and a memory cell layer 104A on a semiconductor substrate 101; forming a thin film 161 on a sidewall of the first groove; burying an interlayer dielectric 105 in the groove to form a laminate; forming a second wiring layer on the laminate; forming a second groove 186 extending in a second direction and forming second wiring 106; removing the thin film 161 exposed from a bottom part of the second groove 186; and removing the memory cell layer 104A exposed from the bottom part of the second groove 186 up to an upper part of the first wiring layer. The thin film 161 is faster in etching rate than the interlayer dielectric 105 and removed before the part of an adjacent memory cell layer 104A.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种制造半导体存储装置的方法，其被配置为使得蚀刻掩模的损耗小，并且可能导致相邻存储单元之间的短路的残留物不被留下，并且提供半导体存储设备。解决方案：柱形存储单元通过以下方式形成：在半导体衬底101上形成第一布线层和存储单元层104A之后，形成沿第一方向延伸的第一沟槽和形成第一布线103; 在第一槽的侧壁上形成薄膜161; 将沟槽中的层间电介质105埋入以形成层压体; 在层压板上形成第二布线层; 形成沿第二方向延伸并形成第二布线106的第二槽186; 移除从第二槽186的底部露出的薄膜161; 并且从第二槽186的底部露出的存储单元层104A去除到第一布线层的上部。薄膜161的蚀刻速度比层间电介质105更快，并且在相邻的存储单元层104A的部分之前去除。版权所有（C）2011，JPO＆INPIT

7. 发明专利

JP2001284329A SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 失效
公开(公告)号：JP2001284329A
公开(公告)日：2001-10-12
申请号：JP2000099760
申请日：2000-03-31
申请人： TOSHIBA CORP
发明人： SETA SHOJI , MATSUSHITA TAKAYA
IPC分类号： H01L21/027 , H01L21/28 , H01L21/302 , H01L21/3065 , H01L21/308 , H01L21/311 , H01L21/3213 , H01L21/76 , H01L21/768 , H01L23/528 , H01L29/417
摘要： PROBLEM TO BE SOLVED: To provide the manufacturing method of a semiconductor device, which can form work shapes different in the respective parts of a chip with satisfactory controllability, can sufficiently perform work with satisfactory controllability, even if a film where bases partially differ exists in the chip and can form a precise pattern, and to provide the semiconductor device obtained by the method. SOLUTION: The mask of resist 18 of the film, including carbon, is worked after a hard mask (15) is worked. Thus, a prescribed part sets the hard masks, in a state where they are incorporated in resist, another part of the prescribed part forms a part where the resist mask exists and the other part forms a part where the hard mask exists. Thus, the work shape different in the respective parts of the chip can be formed with satisfactory controllability, and work can be performed with sufficient controllability, even if the film where the bases partially differ exists in the chip.

8. 发明专利

JPH05308062A 失效
公开(公告)号：JPH05308062A
公开(公告)日：1993-11-19
申请号：JP7138092
申请日：1992-03-27
申请人： TOSHIBA CORP
发明人： OIWA NORIHISA , HAYASHI HISATAKA , HORIOKA KEIJI , OKANO HARUO , MATSUSHITA TAKAYA , HASEGAWA ISAHIRO , TAKEUCHI AKIRA
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/311
摘要： PURPOSE:To prevent etching speed from depending on a pattern size and increase etching selection ratio by forming a mask pattern with an opening with a specific range of opening diameter on a silicon oxide film and then introducing carbon fluoride gas and hydrogen gas in a mixing ratio of within a specific range. CONSTITUTION:A silicon oxide film 32 is formed on a substrate 30 and a mask pattern with an opening whose opening diameter is at least equal to or more than 0.1mum and is equal to or less than 1mum is formed on the silicon oxide film 32. The substrate 30 is housed in a reaction container 11 and then a mixed gas containing carbon fluoride gas and hydrogen gas is introduced into the reaction container 11 so that the mixing ratio of hydrogen gas to the total of carbon fluoride gas and hydrogen gas ranges from 50 to 80%. The mixed gas is turned into plasma and the silicon oxide film 32 is etched along a mask pattern, thus forming an opening with an aspect ratio which is equal to or more than 1 on the silicon oxide film 32 below the opening of the mask pattern.

9. 发明专利

JP2011142248A Method and device for cleaning substrate 有权
标题翻译：清洗基板的方法和装置
公开(公告)号：JP2011142248A
公开(公告)日：2011-07-21
申请号：JP2010002720
申请日：2010-01-08
申请人： Tokyo Electron Ltd , Toshiba Corp , 東京エレクトロン株式会社 , 株式会社東芝
发明人： TAWARA SHIGERU , YAMASHITA FUMIKO , NISHIMURA EIICHI , OIWA NORIHISA , MATSUSHITA TAKAYA , TOMITA HIROSHI
IPC分类号： H01L21/304 , H01L21/027 , H01L21/3065
CPC分类号： H01L21/67028 , H01L21/02057
摘要： PROBLEM TO BE SOLVED: To provide a method and device for cleaning a substrate which remove a by-product and residual fluorine without damaging a pattern including an exposed portion of a silicon layer when forming the pattern by plasma etching.
SOLUTION: In the method for cleaning the substrate, the surface of a substrate is cleaned after a pattern is formed on the substrate by plasma etching. The method includes a by-product removing step of exposing the substrate to an HF-gas atmosphere to remove the by-product, and a residual-fluorine removing step of plasmanizing cleaning gas containing hydrogen gas and gas of a compound containing carbon and hydrogen as constituent elements, and causing the plasma cleaning gas to act on the substrate to remove residual fluorine on the substrate.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于清洁基板的方法和装置，其在通过等离子体蚀刻形成图案时，不会损坏包括硅层的暴露部分的图案，而不会损坏副产物和残余氟。解决方案：在清洁基板的方法中，在通过等离子体蚀刻在基板上形成图案之后，清洁基板的表面。该方法包括将基板暴露于HF气体气氛以除去副产物的副产物除去步骤，以及将含有氢气的清洗气体和含有碳和氢的化合物的气体等离子化的残余氟除去步骤作为构成元件，并且使等离子体清洁气体作用在基板上以除去基板上的残余氟。版权所有（C）2011，JPO＆INPIT

10. 发明专利

JP2008060264A Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2008060264A
公开(公告)日：2008-03-13
申请号：JP2006234241
申请日：2006-08-30
申请人： Toshiba Corp , 株式会社東芝
发明人： AKIYAMA KAZUTAKA , MATSUSHITA TAKAYA
IPC分类号： H01L21/82 , H01L21/3065 , H01L21/3205 , H01L21/768 , H01L23/52 , H01L23/522
CPC分类号： H01L23/5258 , H01L21/76816 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which can increase a relief rate based on a redundant circuit and can reduce a possibility of a failure in the semiconductor device at the same time, and also to provide a method of manufacturing the semiconductor device. SOLUTION: The semiconductor device comprises a metal wiring pattern 109 and a fuse wiring pattern 111 formed in an insulating film 106 on a substrate 101, a first insulating film 202 under a PAD wiring formed above the insulating film 106, a second insulating film 203 under the PAD wiring formed on the first insulating film 202 under the PAD wiring, PAD wiring 402 formed in a region above the metal wiring pattern 109 for the first and second insulating films 202 and 203 under the PAD wiring, and an opening 701 formed so that part of the first insulating film 202 under the PAD wiring in the first and second insulating films 202 and 203 under the PAD wiring remains in a region above the fuse wiring pattern 111. The second insulating film 203 under the PAD wiring contains an element different from an element contained in the first insulating film 202 under the PAD wiring. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：解决的问题：提供一种半导体器件，其可以基于冗余电路增加释放速率，并且可以同时降低半导体器件的故障的可能性，并且还提供一种制造半导体器件。解决方案：半导体器件包括金属布线图案109和形成在基板101上的绝缘膜106中的熔丝布线图案111，在绝缘膜106上形成的PAD布线下的第一绝缘膜202，第二绝缘层在PAD布线下方的第一绝缘膜202上形成的PAD布线下方的膜203，在PAD布线下面的第一绝缘膜202和第二绝缘膜203的金属布线图案109上方的区域上形成的PAD布线402，以及开口701 形成为使得在PAD布线下面的第一和第二绝缘膜202和203中的PAD布线下面的第一绝缘膜202的一部分保留在熔丝布线图案111上方的区域中.PAD布线下方的第二绝缘膜203包含元件不同于PAD布线下面的第一绝缘膜202中包含的元件。版权所有（C）2008，JPO＆INPIT

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