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1. 发明专利

JPS6151944A Package for semiconductor ic device 失效
标题翻译：半导体IC器件封装
公开(公告)号：JPS6151944A
公开(公告)日：1986-03-14
申请号：JP17473784
申请日：1984-08-22
申请人： Nec Corp , Nippon Telegr & Teleph Corp
发明人： ASHIDA SHIGEAKI , NODA YUJI , OBARA MAMORU , KIKUCHI HIROYUKI
IPC分类号： H01L23/02 , H01L21/60 , H01L23/66
CPC分类号： H01L23/66 , H01L2224/48 , H01L2224/48091 , H01L2224/48237 , H01L2224/49 , H01L2224/49171 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/3011 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： PURPOSE:To reduce the impendance of the electrical connection means by a method wherein the mount surface is provided with a continuous projection which surrounds a chip, and the chip is bonded to each of package lead extensions provided on the mount surface outside the projection. CONSTITUTION:Bonding pads 6 and 4 of the same potential on the chip 1 are connected to the package lead extensions 19 and 20 with bonding wires 13 and 16, respectively. The projection 18 surrounding the chip 1 is provided on the surface where each electrode of the mount part 2 is present, and set to such as suitable level that solder does not flow out of the projection at the mount part and does not block bonding work. Besides, the electrical bonding between package leads 21 and 22 and between 23 and 24 is made dense by providing package lead extensions 19 and 20 made of metallic film. This reduces the DC and high- frequency impedance between the bonding pad 4 or 6 and the mount part 2.
摘要翻译：目的：通过一种方法来减小电连接装置的阻抗，其中安装表面设置有围绕芯片的连续突起，并且芯片被接合到设置在突出部外部的安装表面上的每个封装引线延伸部。构成：芯片1上具有相同电位的接合焊盘6和4分别用接合线13和16连接到封装引线延伸部19和20。围绕芯片1的突起18设置在安装部2的每个电极存在的表面上，并且被设置为使得焊料不会从安装部分处的突起流出并且不阻挡接合作业的适当水平。此外，通过提供由金属膜制成的封装引线延伸部19和20，封装引线21和22以及23和24之间的电接合变得致密。这降低了接合焊盘4或6与安装部件2之间的直流和高频阻抗。

2. 发明专利

JPS5746537A Programmable counter 失效
标题翻译：可编程计数器
公开(公告)号：JPS5746537A
公开(公告)日：1982-03-17
申请号：JP12276180
申请日：1980-09-04
申请人： Nec Corp , Nippon Telegr & Teleph Corp
发明人： KATOU GIICHI , KIKUCHI HIROYUKI , IWATA ATSUSHI
IPC分类号： H03K23/66
CPC分类号： H03K23/665
摘要： PURPOSE:To shorten the time for the count execution start of a programmable counter, by providing a gate circuit having a delay circuit of four-gate components in the preceding stage of a D type FF. CONSTITUTION:When an LOAD terminal is set to L and a program data input terminal Pi is set to H, the output of an NAND gate 24 becomes H; and since an NAND gate 26 is H, a transmission gate TG28 is turned on, and a D type FF34 is set to H. Next, the LOAD terminal is set to H; and if a CEP or CET terminal is L, the output of the NAND gate 26 becomes L, and a TG31 is turned on, and the D type FF34, is held in the preceding state. When CEP and CET terminals become H together, the D type FF34 is inverted each time a clock terminal CP becomes H, and thus, count advances. Consequently, the propagation delay time to the count start is shortened to the time of four-gate components of NAND gates 25 and 26, an inverter 27, and the TG28.
摘要翻译：目的：为了缩短可编程计数器的计数执行开始的时间，通过提供具有D型FF的前级的四门分量的延迟电路的门电路。构成：当LOAD端子设置为L并且程序数据输入端子Pi设置为H时，与非门24的输出变为H; 并且由于与非门26是H，所以传输门TG28导通，D型FF34被设置为H.接下来，LOAD端被设置为H; 如果CEP或CET端子为L，则与非门26的输出变为L，TG31导通，D型FF34保持在前一状态。当CEP和CET端子变为H时，每当时钟端CP变为H时，D型FF34都反相，因此计数提前。因此，计数开始的传播延迟时间缩短为与非门25和26，逆变器27和TG28的四门组件的时间。

3. 发明专利

JP2005348232A Switch apparatus 有权
标题翻译：开关装置
公开(公告)号：JP2005348232A
公开(公告)日：2005-12-15
申请号：JP2004167307
申请日：2004-06-04
申请人： Nippon Telegr & Teleph Corp , Ntt Electornics Corp , エヌティティエレクトロニクス株式会社 , 日本電信電話株式会社
发明人： KAMITSUNA HIDEKI , MURAGUCHI MASAHIRO , KIKUCHI HIROYUKI
IPC分类号： H01P1/15
摘要： PROBLEM TO BE SOLVED: To provide a switch configuration having scalability to a multi-input/output switch and other multiple uses by solving problems that conventional 2×2 switches can not use a signal having DC offset, circuit scale is large since switch circuits are included at both input and output sides and positions of input/output terminals are inconvenient for extension to multiple uses. SOLUTION: A plurality of 2×2 switches are configured adjacently to each other on a rectangular substrate, a single-pole double-throw switch comprising the 2×2 switches is comprised of two series FETs, input/output terminals are disposed on sides adjacent to each other at positions of 90° on the substrate, and input/output terminals are also disposed on two sides different from said sides even for another switch. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了通过解决传统的2×2开关不能使用具有DC偏移的信号的问题来提供对多输入/输出开关具有可扩展性的开关配置和其他多种用途，因此电路规模大开关电路包括在输入和输出侧，输入/输出端子的位置不便于扩展到多种用途。
解决方案：在矩形基板上多个2×2开关相互配置，包括2×2开关的单极双掷开关由两个串联FET组成，输入/输出端子被布置在基板上的90°的位置上彼此相邻的侧面，即使对于另一个开关，输入/输出端子也设置在与所述侧面不同的两侧。版权所有（C）2006，JPO＆NCIPI

4. 发明专利

JPS57123717A Switched capacitor circuit 失效
标题翻译：开关电容器电路
公开(公告)号：JPS57123717A
公开(公告)日：1982-08-02
申请号：JP792781
申请日：1981-01-23
申请人： Hitachi Ltd , Nippon Telegr & Teleph Corp
发明人： SUZUKI TOSHIROU , KIKUCHI HIROYUKI
IPC分类号： G06G7/186 , H03H19/00
CPC分类号： H03H19/004
摘要： PURPOSE:To reduce the influence, noise and crosstalk of a stary capacitor, by providing switches, which close during discharge, between both electrodes of a capacitor, and one of both the electrodes and the ground. CONSTITUTION:Between a capacitor (C)7 to be charged and discharged and the input terminal 1 of a switched capacitor circuit 4, and the C7 and the output terminal 2 of the circuit 4, switches SW8 and SW9 which close during charge are provided, and between both electrodes of the C7, and the output-terminal electrode of the C7 and the ground, SWs 12 and 13 which close during discharge are provided. Each SW is composed of an MOS transistor; the SWs 8 and 9 close by a pulse phi1 and at this time, the SWs 12 and 13 open; the SWs 12 and 13 close by a pulse phi2 and at this time, the SWs 8 and 9 open. With the SWs 12 and 13 closed, the C7 is discharged through the SW12, and stray capacitors Cs and Cs' are discharged through the SWs 12 and 13. Since the discharge of the C7 depends upon only the SW12, the required area of the MOS transistor is reduced, and since the discharge of the Cs and Cs' depends upon only the SW13, it is composed of the MOS transistor of small size, thereby reducing the noise, crosstalk, etc., of the capacitors.
摘要翻译：目的：通过在电容器的两个电极和电极和地面中的一个之间提供在放电期间闭合的开关来减小暂停电容器的影响，噪声和串扰。构成：在被充电和放电的电容器（C）7与开关电容器电路4的输入端子1之间以及电路4的C7和输出端子2之间，设置在充电期间闭合的开关SW8和SW9，并且在C7的两个电极和C7的输出端电极和接地之间提供在放电期间闭合的SW 12和13。每个SW由MOS晶体管组成; SW8和9由脉冲phi1关闭，此时SW 12和13打开; SW 12和13由脉冲phi2关闭，此时SW 8和9打开。在SW 12和13关闭的情况下，C7通过SW12放电，并且杂散电容器Cs和Cs'通过SW 12和13放电。由于C7的放电仅取决于SW12，所以MOS的所需面积晶体管被减小，并且由于Cs和Cs'的放电仅取决于SW13，所以它由小尺寸的MOS晶体管组成，从而降低了电容器的噪声，串扰等。

5. 发明专利

JPS6165622A Analog switch 失效
标题翻译：模拟开关
公开(公告)号：JPS6165622A
公开(公告)日：1986-04-04
申请号：JP18656984
申请日：1984-09-07
申请人： Nippon Telegr & Teleph Corp
发明人： KIKUCHI HIROYUKI , KAWARADA KUNIYASU
IPC分类号： H03K17/16 , H03K17/60
CPC分类号： H03K17/16 , H03K17/603
摘要： PURPOSE:To decrease leakage to an output side by constituting the titled switch as longitudinal stack differential 2-stage, controlling signal on/off of the differential stage of upper stage and using the lower stage differential stage to convert linearly an input signal thereby avoiding direct leakage of the input signal via a parasitic capacitance. CONSTITUTION:When VC>VR2, almost no current flows to a transistor (TR)Q22, an output Vout becomes a nearly constant value, and the switch is turned off. On the other hand, when VC
摘要翻译：目的：通过将标称开关构成纵向堆栈差分2级，控制上级差分级的信号开/关，并使用下级差分级线性输入信号，从而避免直接通过寄生电容泄漏输入信号。构成：当VC> VR2时，几乎没有电流流向晶体管（TR）Q22，输出Vout变为几乎恒定的值，开关断开。另一方面，当VC

6. 发明专利

JPS58205330A Signal detecting circuit 失效
标题翻译：信号检测电路
公开(公告)号：JPS58205330A
公开(公告)日：1983-11-30
申请号：JP8805882
申请日：1982-05-26
申请人： Nippon Telegr & Teleph Corp
发明人： KANEKO TAKAO , KIKUCHI HIROYUKI
IPC分类号： G01R23/02 , H03K12/00 , H04Q1/45
CPC分类号： H03K12/00
摘要： PURPOSE:To attain a detecting operation not affected by noise and DC offset voltage without using a control signal generating circuit, by comparing a peak- to-peak voltage of a signal with a threshold voltage at each period of an AC input signal. CONSTITUTION:An AC input signal VIN including DC offset voltage is given to peak holding circuits 5A, 5B, its output (b) is inputted to a selecting circuit 6, any one of the outputs (b) is selected and given to a comparator 2. A selection switching signal to the selecting circuit 6 and the type of the threshold voltage given to the comparator 2 are controlled by a control circuit 3 based on the output of the comparator, and an output (c) of the comparator 2 is obtained as an AC signal detecting waveform. Thus, the peak holding operation is done at each half period and the comparing operation is done at the same time, then the detection is not affected by noise and SC offset voltage.
摘要翻译：目的：通过在交流输入信号的每个周期将信号的峰 - 峰电压与阈值电压进行比较，来获得不受噪声和直流偏移电压影响的检测操作，而不使用控制信号发生电路。构成：向峰值保持电路5A，5B给出包括DC偏移电压的AC输入信号VIN，其输出（b）被输入到选择电路6，输出（b）中的任何一个被选择并给予比较器2 选择电路6的选择切换信号和给予比较器2的阈值电压的种类由控制电路3根据比较器的输出进行控制，比较器2的输出（c）为 AC信号检测波形。因此，峰值保持操作在每个半周期进行，并且比较操作同时进行，则检测不受噪声和SC偏移电压的影响。

7. 发明专利

JPS5761325A Voltage-controlled variable oscillating circuit 失效
标题翻译：电压控制可变振荡电路
公开(公告)号：JPS5761325A
公开(公告)日：1982-04-13
申请号：JP13711080
申请日：1980-09-30
申请人： Nippon Telegr & Teleph Corp
发明人： KIKUCHI HIROYUKI
IPC分类号： H03K3/02 , H03K3/354
CPC分类号： H03K3/354
摘要： PURPOSE:To increase the width of a variable oscillation frequency range greatly by connecting a p channel and an n channel MISFET in series between a power line and earth. CONSTITUTION:Between a power line 4 and earth, a p channel MISFETM4 and an N channel MISFETM5 are connected in series. The connection middle point between the FEts 4 and 5 is connected to the connection middle point A between an MISFETM2 and a resistance 5. Then, a p channel MISFETM7 is connected in series between the power line 4 and earth as well as a p channel MISFETM6. Further, an n channel MISFETM8 and an MISFETM9 are connected in series between the power line and earth. Consequently, control is so exercised by a control voltage V that only when the voltage of the FETM4 is less than a voltage VA, the FETM4 operates. The FETM5, on the other hand, is also controlled by the control voltage V to operate only when its voltage is less than a voltage VB.
摘要翻译：目的：通过在电源线和地线之间串联连接p沟道和n沟道MISFET来大大增加可变振荡频率范围的宽度。构成：在电源线4和地之间，串联连接p沟道MISFETM4和N沟道MISFETM5。第4和5号之间的连接中点连接到MISFETM2和电阻5之间的连接中间点A.然后，p沟道MISFETM7串联连接在电力线4和地之间以及p沟道MISFETM6。此外，n沟道MISFETM8和MISFETM9串联连接在电源线和地之间。因此，只有当FETM4的电压小于电压VA时，控制电压V才能进行控制，FETM4工作。另一方面，FETM5也由控制电压V控制，仅在其电压小于电压VB时才起作用。

8. 发明专利

JPS57123729A Reference-voltage supplying circuit 失效
标题翻译：参考电压供电电路
公开(公告)号：JPS57123729A
公开(公告)日：1982-08-02
申请号：JP792681
申请日：1981-01-23
申请人： Hitachi Ltd , Nippon Telegr & Teleph Corp
发明人： YAMAKIDO KAZUO , KIKUCHI HIROYUKI
IPC分类号： H03M1/12 , G06G7/25 , H03M1/00
CPC分类号： H03M1/00
摘要： PURPOSE:To eliminate the need for a control terminal by selecting a reference voltage on the basis of the level of the reference voltage supplied from an external terminal. CONSTITUTION:An external reference voltage VEXT supplied to an external reference voltage input terminal 1 is discriminated on the basis of an input threshold voltage value VTH determined by an inverter circuit 21 to output lines 3 and 4 binary signals which have mutually complementary logical levels and switch analog switches 6 and 7 complementarily. When the external reference voltage vEXT is lower than the threshold voltage value VTH, a voltage having a value VINT is applied from an internal reference voltage source 5 to an output terminal 8. When not, the analog switch 6 is closed, so the external reference voltage source 5 to an output terminal 8. When not, the analog switch 6 is closed, so the external reference voltage is developed at the output terminal 8.
摘要翻译：目的：通过根据从外部端子提供的参考电压的电平选择参考电压来消除对控制端子的需要。构成：基于由逆变器电路21确定的输入阈值电压值VTH来输出提供给外部参考电压输入端子1的外部参考电压VEXT，以输出线路3和4具有互补逻辑电平和开关的二进制信号模拟开关6和7互补。当外部参考电压vEXT低于阈值电压值VTH时，从内部参考电压源5向输出端子8施加值为VINT的电压。否则，模拟开关6闭合，因此外部参考电压电压源5连接到输出端子8.否则，模拟开关6闭合，因此在输出端子8处产生外部基准电压。

9. 发明专利

JPS5912683A Receiver of multifrequency signal 失效
标题翻译：多频信号接收机
公开(公告)号：JPS5912683A
公开(公告)日：1984-01-23
申请号：JP12192782
申请日：1982-07-13
申请人： Nippon Telegr & Teleph Corp
发明人： KANEKO TAKAO , KIKUCHI HIROYUKI
IPC分类号： H04Q1/457 , H04Q1/453
CPC分类号： H04Q1/453
摘要： PURPOSE:To attain the economy at circuit integration, by multiplexing a band pass filter and a detecting circuit and operating them in time series to each channel of a multifrequency signal for decreasing the occupied area and power consumption of the filter and the detecting circuit. CONSTITUTION:The multifrequency signal divided into groups at band stop filters 1, 2 is inputted to limiter circuits 3, 4, where the signal level is detected and a rectangular wave having a period equal to a signal is outputted. Thus, an input signal of multiplex band pass filters 21, 22 is a rectangular wave having a equal period to one frequency among each four frequencies of low and high groups. The multiplex band pass filters 21, 22 have equal gain and Q, the center frequency is controlled for the filters from the channel 1 to the channel 4 split into four kinds of frequencies respectively for high and low groups by providing four sets of timing with a clock and is operated in time series. Thus, the occupied area and power consumption of the filters 21, 22 and the detecting circuits 23, 24 are decreased, and the economy is attained because the scale of circuit is small in case of circuit integration.
摘要翻译：目的：为了实现电路集成的经济性，通过对带通滤波器和检测电路进行复用，并对多频信号的每个通道进行时间序列的操作，以减少滤波器和检测电路的占用面积和功耗。构成：在频带停止滤波器1,2分组的多频信号被输入到检测信号电平的限制电路3,4，并输出周期等于信号的矩形波。因此，多路复用带通滤波器21,22的输入信号是在低和高组的每四个频率中具有相等周期到一个频率的矩形波。多路复用带通滤波器21,22具有相等的增益和Q，通过提供四组定时，通过提供四组定时，将滤波器的中心频率从频道1到频道4分别分为四种频率，分别用于高和低组时钟和时间序列。因此，滤波器21,22和检测电路23,24的占用面积和功率消耗减小，并且由于在电路集成的情况下电路规模小，因此获得经济性。

10. 发明专利

JP2002176418A FRAME SYNCHRONIZATION CIRCUIT 失效
公开(公告)号：JP2002176418A
公开(公告)日：2002-06-21
申请号：JP2000371864
申请日：2000-12-06
申请人： NEC CORP
发明人： KIKUCHI HIROYUKI
IPC分类号： H04J3/06 , H04L7/08
摘要： PROBLEM TO BE SOLVED: To provide a frame synchronization circuit that has a circuit configuration with a smaller scale at a lower cost than those of a conventional frame synchronization circuit by decreasing number of circuits required for a high- speed operation more than that of the conventional frame synchronization circuit and can avoid mis-synchronization of frames due to a pseudo frame pattern. SOLUTION: The frame synchronization circuit is configured to establish frame synchronization by adjusting latch timing, generates the latch timing according to a clock signal with a frequency (1/N), adjusts the phase of the clock signal with the frequency (1/N) to adjust the latch timing when detecting out of synchronism of the frame, and invalidates the adjustment of the latch timing when not detecting the out of synchronism of the frame.

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