专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JPS57123474A Integral network 失效
标题翻译：综合网络
公开(公告)号：JPS57123474A
公开(公告)日：1982-07-31
申请号：JP792481
申请日：1981-01-23
申请人： Hitachi Ltd , Nippon Telegr & Teleph Corp
发明人： SUZUKI TOSHIROU , IWATA ATSUSHI
IPC分类号： H03H19/00 , G06G7/186
CPC分类号： G06G7/186
摘要： PURPOSE:To obtain a switched capacitor type integral network having the reduced occurrnce of the folded noise, by having a complementary action of the switched capacitors of the same constitution. CONSTITUTION:The input signal is applied to an input terminal 1 and then to the 1st and 2nd switched capacitor circuits 4-1 and 4-2 which have the same constitution and perform a complementary action. For each switch 6, a switch 6-4 is on with switches 6-3 and 6-4 turned off when a switch 6-1 is on, and a switch 6-4 is off with switches 6-3 and 6-4 turned off when the switch 6-1 is off respectively. In other words, the switches 6 are controlled to perform a complementary action so that one of the circuits 4-1 and 4-2 has a discharging action when the other is carrying out a charging action.
摘要翻译：目的：通过具有相同结构的开关电容器的互补作用，获得具有减少的折叠噪声发生的开关电容器型整体网络。构成：将输入信号施加到具有相同结构并执行补充动作的输入端子1，然后施加到第1和第2开关电容器电路4-1和4-2。对于每个开关6，当开关6-1接通时，开关6-4接通，开关6-3和6-4断开，开关6-4和6-4断开，开关6-4断开当开关6-1分别断开时关闭。换句话说，控制开关6执行互补动作，使得当另一个进行充电动作时，电路4-1和4-2中的一个具有放电动作。

2. 发明专利

JPS57123717A Switched capacitor circuit 失效
标题翻译：开关电容器电路
公开(公告)号：JPS57123717A
公开(公告)日：1982-08-02
申请号：JP792781
申请日：1981-01-23
申请人： Hitachi Ltd , Nippon Telegr & Teleph Corp
发明人： SUZUKI TOSHIROU , KIKUCHI HIROYUKI
IPC分类号： G06G7/186 , H03H19/00
CPC分类号： H03H19/004
摘要： PURPOSE:To reduce the influence, noise and crosstalk of a stary capacitor, by providing switches, which close during discharge, between both electrodes of a capacitor, and one of both the electrodes and the ground. CONSTITUTION:Between a capacitor (C)7 to be charged and discharged and the input terminal 1 of a switched capacitor circuit 4, and the C7 and the output terminal 2 of the circuit 4, switches SW8 and SW9 which close during charge are provided, and between both electrodes of the C7, and the output-terminal electrode of the C7 and the ground, SWs 12 and 13 which close during discharge are provided. Each SW is composed of an MOS transistor; the SWs 8 and 9 close by a pulse phi1 and at this time, the SWs 12 and 13 open; the SWs 12 and 13 close by a pulse phi2 and at this time, the SWs 8 and 9 open. With the SWs 12 and 13 closed, the C7 is discharged through the SW12, and stray capacitors Cs and Cs' are discharged through the SWs 12 and 13. Since the discharge of the C7 depends upon only the SW12, the required area of the MOS transistor is reduced, and since the discharge of the Cs and Cs' depends upon only the SW13, it is composed of the MOS transistor of small size, thereby reducing the noise, crosstalk, etc., of the capacitors.
摘要翻译：目的：通过在电容器的两个电极和电极和地面中的一个之间提供在放电期间闭合的开关来减小暂停电容器的影响，噪声和串扰。构成：在被充电和放电的电容器（C）7与开关电容器电路4的输入端子1之间以及电路4的C7和输出端子2之间，设置在充电期间闭合的开关SW8和SW9，并且在C7的两个电极和C7的输出端电极和接地之间提供在放电期间闭合的SW 12和13。每个SW由MOS晶体管组成; SW8和9由脉冲phi1关闭，此时SW 12和13打开; SW 12和13由脉冲phi2关闭，此时SW 8和9打开。在SW 12和13关闭的情况下，C7通过SW12放电，并且杂散电容器Cs和Cs'通过SW 12和13放电。由于C7的放电仅取决于SW12，所以MOS的所需面积晶体管被减小，并且由于Cs和Cs'的放电仅取决于SW13，所以它由小尺寸的MOS晶体管组成，从而降低了电容器的噪声，串扰等。

3. 发明专利

JPS59161132A Variable equalizer 失效
标题翻译：可变均衡器
公开(公告)号：JPS59161132A
公开(公告)日：1984-09-11
申请号：JP3545583
申请日：1983-03-04
申请人： Fujitsu Ltd , Hitachi Ltd , Nec Corp , Nippon Telegr & Teleph Corp , Oki Electric Ind Co Ltd
发明人： TAKADA AKIHIKO , TSUDA TOSHITAKA , KIMURA TADAKATSU , SASAGAWA MASAAKI , SUZUKI TOSHIROU , KURAISHI YOSHIAKI , GUNJI KATSUHIKO
IPC分类号： H04B3/04 , H03H11/02 , H03H11/04 , H04B3/14
CPC分类号： H04B3/145
摘要： PURPOSE:To set optionally a variable width of impedance so that no variation is generated, by dividing a value of an impedance element into plural pieces, and executing the switcing control of a switch so that an output of a variable gain controlling circuit is subjected to prescribed equalizing control. CONSTITUTION:In order to control the gain of equalizing circuits FEG, SEQ, reference voltage V and an equalizing output OUT are compared by a peak value detecting circuit PD, its magnitude is decided, and the continuity of its result is detected by a pulse controlling circuit PC. Subsequently, a pulse from the circuit PC is counted by a counting circuit CNT, and a counting value corresponding to the gain required for the circuit FEQ, SEQ is obtained. An output of this circuit CNT is converted to a logic for switching switches SW11-SW1n and SW21-SW2n provided on the circuits FEQ, SEQ, by a gain controlling circuit LG, and setting of the gain corresponding to the output of the circuit CNT is executed.
摘要翻译：目的：通过将阻抗元件的值除以多个部分，并且执行开关的切换控制，使可变增益控制电路的输出经受规定均衡控制。构成：为了控制均衡电路FEG，SEQ，参考电压V和均衡输出OUT的增益，通过峰值检测电路PD进行比较，确定其幅度，并通过脉冲控制来检测其结果的连续性电路PC。随后，通过计数电路CNT对来自电路PC的脉冲进行计数，并且获得与电路FEQ，SEQ所需的增益相对应的计数值。该电路CNT的输出通过增益控制电路LG转换为设置在电路FEQ，SEQ上的开关SW11-SW1n和SW21-SW2n的逻辑，并且与电路CNT的输出相对应的增益的设定为执行。

4. 发明专利

JPS5737937A Automatic hybrid circuit 失效
标题翻译：自动混合电路
公开(公告)号：JPS5737937A
公开(公告)日：1982-03-02
申请号：JP11168980
申请日：1980-08-15
申请人： Hitachi Ltd , Nippon Telegr & Teleph Corp
发明人： AMADA EIICHI , SUZUKI TOSHIROU , SHIRASU HIROTOSHI , KUWABARA HIROSHI , MORIKAWA YUUICHI , SATOU HIROHIKO
IPC分类号： H04B3/03 , H04B3/20 , H04B3/23
CPC分类号： H04B3/03 , H04B3/23
摘要： PURPOSE: To obtain a circuit which can automatically be applied to various impedances at two line side, by selecting a filter so that the output voltage is equal to the leakage voltage to the 4-line output side among a plurality of filter groups connected to the 4-line input side.
CONSTITUTION: An input signal of a 4-line type input side 202 is applied to a 2-line side 210 via an amplifier 216, terminal impedance 209, and coupling point 214. A signal at the 2-line side is outputted to a 4-line type output side 201 via the coupling point 214, sample hold SH circuit 207, and subtractors 203, 204. A plurality of filters 211-1∼211-N with different transmission performance are connected to the 4-line type input via an SH circuit 208 and the output is connected to the negative side of the subtractors 203, 204 via switches 212-1∼212-N and 213-1∼213-N respectively, and the output of the subtractors is inputted to a discrimination circuit 205. The leakage voltage from the 4-line type input to output side stored at the circuit 207 kand the filter output voltage are subtracted at two subtractors, and a filter having minimum subtraction value is discriminated by switching the switches at the circuit 205, allowing to select the filter.
COPYRIGHT: (C)1982,JPO&Japio
摘要翻译：目的：为了获得可以自动应用于两个线路侧的各种阻抗的电路，通过选择滤波器，使得输出电压等于连接到多个滤波器组的多个滤波器组中的4线输出侧的泄漏电压 4行输入端。构成：4线型输入侧202的输入信号经由放大器216，端子阻抗209和耦合点214被施加到2线侧210. 2线侧的信号被输出到4线型经由耦合点214，采样保持SH电路207和减法器203,204的线路型输出侧201.具有不同传输性能的多个滤波器211-1-211-N经由 SH电路208，并且输出分别经由开关212-1-212-N和213-1-213-N连接到减法器203,204的负侧，并且减法器的输出被输入到鉴别电路205 从存储在电路207处的4线型输入到输出侧的漏电压和滤波器输出电压在两个减法器中减去，并且通过在电路205上切换开关来鉴别具有最小减法值的滤波器，允许选择过滤器。

5. 发明专利

JPS60223257A VARIABLE EQUALIZER 失效
公开(公告)号：JPS60223257A
公开(公告)日：1985-11-07
申请号：JP4830785
申请日：1985-03-13
申请人： HITACHI LTD
发明人： YUMOTO OSAMU , SUZUKI TOSHIROU , TAKATORI HIROSHI , TAKASAKI YOSHITAKA
IPC分类号： H03H11/04 , H04B3/14 , H04L25/00 , H04L25/03
摘要： PURPOSE:To increase equalizing range without deteriorating the equalizing accuracy by converting the output of an equalizer into digital signals and using high-order and low-order bits of the digital signal to control an equalizer having a large variable step width and an equalizer of a smaller variable step width, respectively. CONSTITUTION:Unit variable equalizers 3 and 4 are connected in series. For a part of the output of an equalizer 4, an output signal is converted into the DC value by a level detecting circuit 5. This DC value is compared with a reference signal 6 by a comparaor 7, and the result of this comparison is applied to an up- down counter 8. An high-order bit signal aU of the counter 8 is used to control an equalizer of a large variable step width. While a low-order bit signal aL is used to control an equalizer of a small varible step width, respectively.

6. 发明专利

JPS57192118A HIGH PASS FILTER 失效
公开(公告)号：JPS57192118A
公开(公告)日：1982-11-26
申请号：JP7650181
申请日：1981-05-22
申请人： HITACHI LTD
发明人： SUZUKI TOSHIROU
IPC分类号： H03H19/00
摘要： PURPOSE:To reduce the volume of an LSI chip, by constituting the circuit that no holding capacitor is required in a switched capacitor circuit. CONSTITUTION:One end of a switched capacticor circuit 10 is connected to an input terminal 1 of a filter 1 and another end is connected to switches 7-1 and 7-2 which alternately switch a switched capacitor circuit 20 and ground with a prescribed period. The circuit 20 consists of a switched capacitor 4 which makes charging with a switch 7-2 turned on and a switch 7-3 turned on and makes discharge with a switch 7-4 turned on and a switch 7-3 turned off when the switch 7-1 turns on and the switch 7-2 turns off, a capacitor 5 and an operational amplifier 8. Further, the circuit is constituted so that a product V2(C3+C2) between an output terminal voltage V2 and the sum of capacitors 4 and 5 can be a function of a product between a capacitance value C1 of a capacitor 3 and a potential difference of an input voltage V1 for one period.

7. 发明专利

JPS5390853A PULSE AMPLITUDE MODULATOR 失效
公开(公告)号：JPS5390853A
公开(公告)日：1978-08-10
申请号：JP491977
申请日：1977-01-21
申请人： HITACHI LTD
发明人： SUZUKI TOSHIROU , TSUKAMOTO NOBUO
IPC分类号： H04J3/00 , H03K7/02
摘要： PURPOSE:To improve the crosstalk and the noise characteristics as well as to realize a smallsize circuit and an easy IC formation, by increasing the signal source impedance in accordance with increment of the frequency with use of the active element.

8. 发明专利

JPS5387157A NONNLINEAR AAD CONVERTER 失效
公开(公告)号：JPS5387157A
公开(公告)日：1978-08-01
申请号：JP148677
申请日：1977-01-12
申请人： HITACHI LTD
发明人： SUZUKI TOSHIROU
IPC分类号： H03M1/58
摘要： PURPOSE:To obtain the non-linear AD converter in which the circuit operating at a low clock rate can be simplified and miniaturized by combining a voltage frequency converter and simple logic circuit.

9. 发明专利

JPS60200654A DECODING CIRCUIT 失效
公开(公告)号：JPS60200654A
公开(公告)日：1985-10-11
申请号：JP5606984
申请日：1984-03-26
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： TAKATORI HIROSHI , SUZUKI TOSHIROU , YOSHIDA KOUICHI
IPC分类号： H04L25/08 , H04L25/03
摘要： PURPOSE:To realize a maximum likelihood decoder (MLD) by a small hardware quantity even in case of a system in which an inter-code interference is large, and also to obtain a decoding circuit whose error is smaller than the case when a decision feedback type decoder (DFD) is used singly, by forming as one body the MLD and the DFD. CONSTITUTION:Two miximum likelihood sequences are stored in a shift register sequency 5 and 6, but an inter-code interference corresponding to these two sequences is calculated by a counter to which an impulse response is set, and a multiplying train 9 and 9' and outputted from DFDs A, B, respectively. They are fed back to adders of 7-1, 2 and an interference quantity corresponding to each data sequence is eliminated. Also, in case of decoding of MLD-DFD, the fourth bit to which a noise is superposed is mistaken as ''1'', and the subsequent fifth bit is decoded as ''-1'', but the erroneous propagation is ended by this bit and after the sixth bit, decoding is executed correctly. That is to say, an error of 7 bit in case of DFD is decreased to 2 bit in case of MLD-DFD. This circuit uses two decoders known up to the present, namely, both MLD and DFD, by which it is possible to solve simultaneously the individual problem points such as the hardware quantity becomes huge when the inter-code interference exists, in case each is used single, in case of MLD, and an error is propagated by plural bits in case of DFD.

10. 发明专利

JPS60200604A VARIABLE GAIN AMPLIFIER CIRCUIT 失效
公开(公告)号：JPS60200604A
公开(公告)日：1985-10-11
申请号：JP5602384
申请日：1984-03-26
申请人： HITACHI LTD
发明人： MATSUBARA OSAMU , TAKATORI HIROSHI , SUZUKI TOSHIROU
IPC分类号： H03G3/12 , H03G3/10 , H03K5/02
摘要： PURPOSE:To prevent various operation failures caused by a switching operation, especially, a deterioration of an S/N, etc. by masking a signal input to an amplifier at the time of switching of a switch use MOSFET for selecting a resistance value of a resistance string. CONSTITUTION:Mask operating MOSFETs T21-T22 are driven by a mask signal MASK generated by a delaying circuit DLY and an NOR logic L1, and the CMOS switches T21-T22 are set to an off-state while a new data is outputted to resistance array changeover switch use MOSFETs T1-T19, and held in a state before an input of a wide band amplifier AMP. Thereafter, when the mask signal MASK falls, transfer MOSFETs T21-T22 become an on-state, and an input signal divided into a desired value is applied to the wide band amplifier AMP. In case when the circuit is susceptible to a feed-through, etc., the CMOS switches T21, T22 become an off-state, and it can be made a circuit which is strong against a noise.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式