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1. 发明专利

JP2004193628A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2004193628A
公开(公告)日：2004-07-08
申请号：JP2004060690
申请日：2004-03-04
申请人： Hitachi Ulsi Systems Co Ltd , Renesas Technology Corp , 株式会社ルネサステクノロジ , 株式会社日立超エル・エス・アイ・システムズ
发明人： MASUDA MASACHIKA , WADA TAMAKI , SUGIYAMA MICHIAKI , TONO TOMOKO , NISHIDA TAKAFUMI , ONO HIROSHI
IPC分类号： H01L25/18 , H01L25/065 , H01L25/07
CPC分类号： H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2225/06562 , H01L2924/01021 , H01L2924/00014
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which is thinned by laminating two semiconductor chips and sealing them together in resin. SOLUTION: The semiconductor chips (4), (5) are bonded and fixed with the back sides of the chips which face each other so as to allow the other long side (4A2) of the semiconductor chip (4) and one long side (5A1) of the semiconductor chip (5) to be directed to the side of a lead (10B), and a support lead (8) is bonded and fixed to the circuit formation surface (4A) of the semiconductor chip (4) or the circuit formation surface (5A) of the semiconductor chip (5). COPYRIGHT: (C)2004,JPO&NCIPI
摘要翻译：要解决的问题：提供通过层压两个半导体芯片并将它们密封在一起的树脂来减薄的半导体器件。解决方案：半导体芯片（4），（5）与彼此面对的芯片的背面接合固定，以便允许半导体芯片（4）的另一个长边（4A2）和一个半导体芯片（5）的长边（5A1）被引导到引线（10B）的一侧，并且支撑引线（8）被接合并固定到半导体芯片（4）的电路形成表面（4A））或半导体芯片（5）的电路形成面（5A）。版权所有（C）2004，JPO＆NCIPI

2. 发明专利

JP2004158896A Semiconductor device 有权
公开(公告)号：JP2004158896A
公开(公告)日：2004-06-03
申请号：JP2004060689
申请日：2004-03-04
申请人： Hitachi Ulsi Systems Co Ltd , Renesas Technology Corp , 株式会社ルネサステクノロジ , 株式会社日立超エル・エス・アイ・システムズ
发明人： MASUDA MASACHIKA , WADA TAMAKI , SUGIYAMA MICHIAKI , TONO TOMOKO , NISHIDA TAKAFUMI , ONO HIROSHI
IPC分类号： H01L25/18 , H01L25/065 , H01L25/07
CPC分类号： H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2225/06562 , H01L2924/01021 , H01L2924/00014
摘要： PROBLEM TO BE SOLVED: To provide a technology which can thin down a semiconductor device which laminates two semiconductor chips, and seals these two semiconductor chips with a resin sealant. SOLUTION: The respective chips of semiconductor chips 4, 5 are bonded each other for fixing while the respective backsides are made to face each other, such that another long side 4A2 of the semiconductor chip 4 and one long side 5A1 of the semiconductor chip 5 face reed 10B side. A support lead 8 are bonded to the circuit surface 4A of the semiconductor chip 4 or the circuit surface 5A of the semiconductor chip 5. COPYRIGHT: (C)2004,JPO

3. 发明专利

JP2004328010A Semiconductor device 审中-公开
公开(公告)号：JP2004328010A
公开(公告)日：2004-11-18
申请号：JP2004205614
申请日：2004-07-13
申请人： Hitachi Ltd , Hitachi Ulsi Systems Co Ltd , 株式会社日立製作所 , 株式会社日立超エル・エス・アイ・システムズ
发明人： SAKUMA KAZUKI , KAWAMURA MASAYASU , TAKAHASHI YASUSHI , MASUDA MASACHIKA , WADA TAMAKI , SUGIYAMA MICHIAKI , NISHIZAWA HIROTAKA , KANNO TOSHIO
IPC分类号： H01L25/18 , H01L23/50 , H01L25/065 , H01L25/07
CPC分类号： H01L2224/48091 , H01L2224/4826 , H01L2924/00014
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which is capable of thinning a resin-sealed semiconductor device by laminating two semiconductor chips, and also improving electrical properties by reducing stray capacitance arising between the semiconductor chips. SOLUTION: A TSOP semiconductor device 1 is formed by laminating the semiconductor chips 2 and 3 with both rear faces facing each other. Outer leads for clock enable into which a clock enable signal and a chip select signal are input individually are mounted on the semiconductor chips 2 and 3, respectively. When gaining an access to one of the semiconductor chips, the other semiconductor chip can be set in a low power consumption mode by setting the clock enable signal and the chip select signal to an inactive state. COPYRIGHT: (C)2005,JPO&NCIPI

4. 发明专利

JP2005236335A Manufacturing method of semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：JP2005236335A
公开(公告)日：2005-09-02
申请号：JP2005146966
申请日：2005-05-19
申请人： Hitachi Ltd , Hitachi Ulsi Systems Co Ltd , 株式会社日立製作所 , 株式会社日立超エル・エス・アイ・システムズ
发明人： MASUDA MASACHIKA , WADA TAMAKI , SUGIYAMA MICHIAKI , NISHIZAWA HIROTAKA , KANNO TOSHIO , TAKAHASHI YASUSHI , KAWAMURA MASAYASU
IPC分类号： H01L25/18 , H01L23/50 , H01L25/065 , H01L25/07
CPC分类号： H01L2224/45144 , H01L2224/48091 , H01L2224/4826 , H01L2924/01055 , H01L2924/00014
摘要： PROBLEM TO BE SOLVED: To provide a method for reducing a thickness and for improving electronic properties of a semiconductor device in which two semiconductor chips are laminated, which are sealed with one resin seal. SOLUTION: The semiconductor device includes: a resin seal; two semiconductor chips which are positioned within the resin seal, and on which front face of their front and rear faces external terminals are formed; and a lead extending over the inner side and outer side of the resin seal, wherein the lead is branched into two leads at least inside the resin seal, one of the branched leads is fixed to the front face of one of the semiconductor chips and electrically connected to the external terminal of the front face, the other of the branched leads is fixed to the front face of the other of the semiconductor chips and electrically connected to the external terminal of the front face, wherein each of the two semiconductor chips is laminated with their rear faces facing each other. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种减小厚度并改善半导体器件的电子性能的方法，其中两个半导体芯片被层叠，半导体器件被一个树脂密封件密封。解决方案：半导体器件包括：树脂密封; 位于树脂密封件内的两个半导体芯片，其前后表面形成有外部端子; 以及在所述树脂密封件的内侧和外侧延伸的引线，其中所述引线至少在所述树脂密封件的内部分支成两个引线，所述分支引线中的一个固定到所述半导体芯片之一的前表面，并且电连接到前表面的外部端子，另一个分支导线固定到另一个半导体芯片的前表面并电连接到前表面的外部端子，其中两个半导体芯片中的每一个层压其后表面相互面对。版权所有（C）2005，JPO＆NCIPI

5. 发明专利

JP2010086550A Semiconductor card device 审中-公开
标题翻译：半导体卡设备
公开(公告)号：JP2010086550A
公开(公告)日：2010-04-15
申请号：JP2009287383
申请日：2009-12-18
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： NISHIZAWA HIROTAKA , HIGUCHI AKIRA , OSAWA KENJI , OSAKO JUNICHIRO , WADA TAMAKI , SUGIYAMA MICHIAKI
IPC分类号： G06K19/077
CPC分类号： H01L24/97 , H01L2224/32145 , H01L2224/48227 , H01L2224/73265 , H01L2224/97 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To make the socket of a semiconductor card device thinner. SOLUTION: When the entire semiconductor card device is sealed to a package with external connection terminals exposed, at least two level difference portions to be engaged with the socket are formed in a thickness direction of the package. The package is formed with integral molding or in a MAP (mold array package) form, and the level difference portions are also integrally formed with integral molding. The socket engages with the level difference portions, each having a thickness thinner than that of the package, and it is therefore facilitated to limit the thickness of the socket to the minimum. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：使半导体卡装置的插座更薄。解决方案：当整个半导体卡装置被密封到具有暴露的外部连接端子的封装时，在封装的厚度方向上形成至少两个与插座接合的高低差部分。封装形成为一体成型或MAP（模具阵列封装）形式，并且电平差部分也整体成型为一体成型。插座与水平差部分接合，每个部分的厚度均小于封装的厚度，因此有助于将插座的厚度限制到最小。版权所有（C）2010，JPO＆INPIT

6. 发明专利

JP2008084263A Memory card and its manufacturing method 审中-公开
标题翻译：记忆卡及其制造方法
公开(公告)号：JP2008084263A
公开(公告)日：2008-04-10
申请号：JP2006266453
申请日：2006-09-29
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： KURATOMI BUNJI , SHIMIZU FUKUMI , SUGIYAMA MICHIAKI , FUJISHIMA ATSUSHI , WADA TAMAKI
IPC分类号： G06K19/077 , B42D15/10
CPC分类号： H01L23/3121 , H01L21/566 , H01L24/45 , H01L24/48 , H01L24/49 , H01L25/0657 , H01L25/18 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/49175 , H01L2225/0651 , H01L2225/06562 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H05K1/117 , H05K3/0052 , H05K3/284 , H05K2201/09145 , H05K2201/10159 , H05K2203/1316 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To increase capacity of a memory card for a portable communication terminal device. SOLUTION: The memory card 1 is composed of a wiring substrate 2 mainly made of glass epoxy resin, a plurality of semiconductor chips (3C, 3F) mounted on the main surface, and a mold resin 4 that encapsulates the wiring substrate 2 and the semiconductor chips (3C, 3F). The mold resin 4 is made of a thermosetting epoxy resin containing quartz filler. The back face of the wiring substrate 2 is not covered with the mold resin 4, but is exposed on the backside of the memory card 1. A plurality of external connection terminals 7, electrically connected to the semiconductor chips (3C, 3F), are formed on the back face of the wiring substrate 2. When the memory card 1 is mounted in the card slot of a cellular phone, a connector terminal built in the card slot and the external connection terminals 7 are brought into contact to exchange a signal and to supply power source between the memory card 1 and the cellular phone. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提高用于便携式通信终端设备的存储卡的容量。解决方案：存储卡1由主要由玻璃环氧树脂制成的布线基板2，安装在主表面上的多个半导体芯片（3C，3F）和封装布线基板2的模制树脂4 和半导体芯片（3C，3F）。模制树脂4由含有石英填料的热固性环氧树脂制成。布线基板2的背面没有被模制树脂4覆盖，而是暴露在存储卡1的背面。电连接到半导体芯片（3C，3F）的多个外部连接端子7是形成在布线基板2的背面上。当存储卡1安装在蜂窝电话的卡槽中时，内置在卡槽中的连接器端子和外部连接端子7接触以交换信号，并且以在存储卡1和蜂窝电话之间提供电源。版权所有（C）2008，JPO＆INPIT

7. 发明专利

JP2007041629A Memory card and semiconductor device 审中-公开
标题翻译：存储卡和半导体器件
公开(公告)号：JP2007041629A
公开(公告)日：2007-02-15
申请号：JP2003374237
申请日：2003-11-04
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： NISHIZAWA HIROTAKA , HIGUCHI AKIRA , OSAWA KENJI , OSAKO JUNICHIRO , WADA TAMAKI , SUGIYAMA MICHIAKI
IPC分类号： G06K17/00 , B42D15/10 , G06K19/00 , G06K19/077 , G11C7/00
CPC分类号： G06K19/07732 , G06K19/005 , G06K19/077 , G06K19/07749
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device having an antenna connection function for contactless interface by minimizing modification on a terminal alignment and a terminal shape of a memory card incompatible with the contactless interface. SOLUTION: Two antenna connection terminals (C6A:LA, C6B:LB) included in the memory card are made to be split terminals separately disposed, by dividing into two areas each having a maximum size of one potential supply terminal. Because the maximum size of each of the two antenna terminals is the size of the potential supply terminal, with the provision of the two antenna connection terminals by sparing a terminal area having the size of the one potential supply terminal to the memory card being incompatible with the contactless interface, the memory card compatible with the contactless interface can be formed. Thus, it becomes possible to form a terminal area of the memory card compatible with the contactless interface without deviating from the terminal area of the memory card incompatible with the contactless interface. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：通过使与非接触式接口不兼容的存储卡的端子排列和端子形状的修改最小化来提供具有用于非接触式接口的天线连接功能的半导体器件。
解决方案：存储卡中包含的两个天线连接端子（C6A：LA，C6B：LB）分别设置为分开设置的分离端子，分为两个区域，每个区域最大尺寸为一个电位端子。由于两个天线端子中的每一个的最大尺寸是电位供应端子的尺寸，所以通过将具有一个电位供应端子的尺寸的端子区域与存储卡不相兼容来提供两个天线连接端子可以形成与非接触式接口兼容的非接触式接口。因此，可以在不偏离与非接触式接口不兼容的存储卡的终端区域的情况下形成与非接触式接口兼容的存储卡的终端区域。版权所有（C）2007，JPO＆INPIT

8. 发明专利

JP2010147225A Semiconductor device and its manufacturing method 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2010147225A
公开(公告)日：2010-07-01
申请号：JP2008322274
申请日：2008-12-18
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： SUGIYAMA MICHIAKI , OTA YUSUKE , MIWA TAKASHI , KIKUCHI TAKU
IPC分类号： H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L24/73 , H01L24/97 , H01L2224/16225 , H01L2224/32145 , H01L2224/48227 , H01L2224/73253 , H01L2224/73265 , H01L2224/97 , H01L2225/06558 , H01L2924/15311 , H01L2224/32225 , H01L2924/00012 , H01L2224/85 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device preventing wire bonding failure when the upper side of laminated semiconductor chips is inclined, and preventing package cracking when a gap is generated between the lower surface of the upper side semiconductor chip and a resin surface. SOLUTION: In a SIP 11, a microcomputer chip 1 is flip-chip-connected on a wiring board 2, and a memory chip 7 larger than the microcomputer chip 1 in the outside dimension is laminated on the microcomputer chip 1, In the SIP, a dam 2f is formed around the microcomputer chip 1 on the wiring board 2, a first sealing body 4 is arranged between the microcomputer chip 1 and the dam 2f, a protruding part 7d of the memory chip 7 is supported by the first sealing body 4, and mounted on the microcomputer chip 1 via a DAF6 having a bonding layer, and an irregularity formed on the surface of the first sealing body 4 is absorbed by the bonding layer of the DAF6, so that the memory chip 7 on the upper side is prevented from being arranged with an incline to the microcomputer chip 1 on the lower side, and the reliability of the SIP 11 is improved. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种半导体器件，当层叠半导体芯片的上侧倾斜时防止引线接合故障，并且在上侧半导体芯片的下表面和树脂之间产生间隙时防止封装开裂表面。解决方案：在SIP11中，微机芯片1在布线板2上倒装芯片连接，并且在外部尺寸上将比微型计算机芯片1大的存储芯片7层叠在微计算机芯片1上 SIP，在配线基板2的微计算机芯片1的周围形成有堤坝2f，在微型计算机芯片1和堤坝2f之间配置有第一密封体4，存储芯片7的突出部7d被第一密封体4，并且通过具有接合层的DAF6安装在微计算机芯片1上，并且形成在第一密封体4的表面上的凹凸被DAF6的接合层吸收，使得存储芯片7 防止上侧向下侧的微型计算机芯片1倾斜地配置，提高了SIP11的可靠性。版权所有（C）2010，JPO＆INPIT

9. 发明专利

JP2009188328A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2009188328A
公开(公告)日：2009-08-20
申请号：JP2008029141
申请日：2008-02-08
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： SHINOHARA MINORU , SUGIYAMA MICHIAKI , NISHI TAKAOMI , KOYAMA MASAAKI
IPC分类号： H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L2224/45144 , H01L2224/48091 , H01L2224/48463 , H01L2224/49107 , H01L2224/73265 , H01L2924/10253 , H01L2924/13091 , H01L2924/00014 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To miniaturize a semiconductor device such as a memory card formed by laminating a memory chip and a controller chip on a wiring substrate. SOLUTION: In the memory card 1A, relocation wiring 6 is formed on the surface of the memory chip M2, pads are disposed at its both ends is electrically connected to the wiring substrate 2 and elements (the memory chips M1, M2, the controller chip 3 and a chip capacitor 4) on the wiring substrate 2 by the relocation wiring 6 and Au wires connected to the pads. Thus the wiring substrate 2 is connected to the elements on the wiring substrate 2 by the short Au wires 11, 14. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：通过在布线基板上层叠存储芯片和控制器芯片而形成的存储卡等半导体装置的小型化。解决方案：在存储卡1A中，在存储芯片M2的表面上形成有重定位布线6，其两端的焊盘与布线基板2和元件（存储芯片M1，M2，控制器芯片3和片状电容器4）通过重定位布线6和连接到焊盘的Au布线布置在布线基板2上。因此，布线基板2通过短Au线11,14连接到布线基板2上的元件。（C）2009，JPO＆INPIT

10. 发明专利

JP2007243227A Method of manufacturing semiconductor apparatus 有权
标题翻译：制造半导体器件的方法
公开(公告)号：JP2007243227A
公开(公告)日：2007-09-20
申请号：JP2007165827
申请日：2007-06-25
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： KAWADA YOICHI , KOIZUMI KOJI , SUGIYAMA MICHIAKI
IPC分类号： H01L25/18 , H01L23/50 , H01L25/065 , H01L25/07
CPC分类号： H01L2224/32245 , H01L2224/45144 , H01L2224/4826 , H01L2224/73215 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To prevent the displacement of a dam bar caused by the injection pressure of resin at mold-forming in manufacturing of semiconductor apparatus which seals two semiconductor chips to a single package with resin using two lead frames.
SOLUTION: A short dummy lead 7 which is present at a direction of the width of a dam bar 6 is formed at the side of the dam bar 6 of a second lead frame LF2. The dummy lead 7 is formed only at the central part of a space region of a lead 1, and is not formed at both ends of the space region (in the neighborhood of the lead 1). This leads to that the dam bar 6 has a larger width by the length of the dummy lead 7 at the central part of the space region of the lead 1 and also has a smaller width at the both ends of the space region (in the neighborhood of the lead 1).
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了防止在使用两个引线框使用树脂将两个半导体芯片密封到单个封装的半导体器件的制造中在模具成型时树脂的注射压力引起的位移。解决方案：在第二引线框架LF2的阻挡杆6的侧面形成有在阻挡杆6的宽度方向上存在的短虚拟引线7。虚拟引线7仅形成在引线1的空间区域的中心部分，并且不形成在空间区域（引线1附近）的两端。这导致阻挡杆6在引线1的空间区域的中心部分处具有较大的虚拟引线7的长度的宽度，并且在空间区域的两端具有较小的宽度的领导1）。版权所有（C）2007，JPO＆INPIT

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