专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JP2010147225A Semiconductor device and its manufacturing method 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2010147225A
公开(公告)日：2010-07-01
申请号：JP2008322274
申请日：2008-12-18
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： SUGIYAMA MICHIAKI , OTA YUSUKE , MIWA TAKASHI , KIKUCHI TAKU
IPC分类号： H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L24/73 , H01L24/97 , H01L2224/16225 , H01L2224/32145 , H01L2224/48227 , H01L2224/73253 , H01L2224/73265 , H01L2224/97 , H01L2225/06558 , H01L2924/15311 , H01L2224/32225 , H01L2924/00012 , H01L2224/85 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device preventing wire bonding failure when the upper side of laminated semiconductor chips is inclined, and preventing package cracking when a gap is generated between the lower surface of the upper side semiconductor chip and a resin surface. SOLUTION: In a SIP 11, a microcomputer chip 1 is flip-chip-connected on a wiring board 2, and a memory chip 7 larger than the microcomputer chip 1 in the outside dimension is laminated on the microcomputer chip 1, In the SIP, a dam 2f is formed around the microcomputer chip 1 on the wiring board 2, a first sealing body 4 is arranged between the microcomputer chip 1 and the dam 2f, a protruding part 7d of the memory chip 7 is supported by the first sealing body 4, and mounted on the microcomputer chip 1 via a DAF6 having a bonding layer, and an irregularity formed on the surface of the first sealing body 4 is absorbed by the bonding layer of the DAF6, so that the memory chip 7 on the upper side is prevented from being arranged with an incline to the microcomputer chip 1 on the lower side, and the reliability of the SIP 11 is improved. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种半导体器件，当层叠半导体芯片的上侧倾斜时防止引线接合故障，并且在上侧半导体芯片的下表面和树脂之间产生间隙时防止封装开裂表面。解决方案：在SIP11中，微机芯片1在布线板2上倒装芯片连接，并且在外部尺寸上将比微型计算机芯片1大的存储芯片7层叠在微计算机芯片1上 SIP，在配线基板2的微计算机芯片1的周围形成有堤坝2f，在微型计算机芯片1和堤坝2f之间配置有第一密封体4，存储芯片7的突出部7d被第一密封体4，并且通过具有接合层的DAF6安装在微计算机芯片1上，并且形成在第一密封体4的表面上的凹凸被DAF6的接合层吸收，使得存储芯片7 防止上侧向下侧的微型计算机芯片1倾斜地配置，提高了SIP11的可靠性。版权所有（C）2010，JPO＆INPIT

2. 发明专利

JP2005159139A Manufacturing method for semiconductor device 审中-公开
标题翻译：半导体器件的制造方法
公开(公告)号：JP2005159139A
公开(公告)日：2005-06-16
申请号：JP2003397539
申请日：2003-11-27
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： KAWAKAMI MASARU , KIKUCHI TAKU , KIMOTO RYOSUKE , KAWAKUBO HIROSHI
IPC分类号： H01L23/12 , H01L21/304 , H01L21/60
CPC分类号： H01L24/97 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/14 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To improve the manufacturing yield of a semiconductor device wherein semiconductor chips are mounted on a wiring board. SOLUTION: After a semiconductor wafer is subjected to a wafer process, it is subjected to re-wiring. Then, after the back side grinding is carried out, dicing is effected to obtain chips, and semiconductor chips 2 having terminals 23 and having no bump electrode are formed. After solder paste 51 is printed on the terminals 43 of the wiring board 41; the semiconductor chips 2 and solder balls 61 are mounted on the wiring board 41, reflow treatment is carried out to connect the terminals 43 of the wiring board 41 to the terminals 23 of the semiconductor chips 2 via the solder paste 51, and the terminals 44 of the wiring board 41 are connected to the solder balls 61. Then, after the underfill resin is formed between the semiconductor chips 2 and the wiring board 41, the wiring board 41 is cut and separated into respective semiconductor devices. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了提高其中半导体芯片安装在布线板上的半导体器件的制造成品率。解决方案：在对半导体晶片进行晶片处理之后，对其进行重新布线。然后，在进行背面研磨之后，进行切割以获得芯片，并且形成具有端子23并且没有凸起电极的半导体芯片2。焊膏51印刷在布线基板41的端子43上之后，半导体芯片2和焊球61安装在布线板41上，进行回流处理，以通过焊膏51将布线基板41的端子43与半导体芯片2的端子23连接，端子44 接线板41与焊球61连接。然后，在半导体芯片2和布线基板41之间形成底部填充树脂之后，将配线基板41切断并分离成各自的半导体装置。版权所有（C）2005，JPO＆NCIPI

3. 发明专利

JP2005012037A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2005012037A
公开(公告)日：2005-01-13
申请号：JP2003175792
申请日：2003-06-20
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： IMURA CHIKAKO , KIKUCHI TAKU , MIWA TAKASHI , SHIBAMOTO MASAKUNI
IPC分类号： H01L23/12 , H01L21/60
CPC分类号： H01L2224/16225 , H01L2924/15174 , H01L2924/15311
摘要： PROBLEM TO BE SOLVED: To enable high density packaging and to improve the electrical characteristic of a semiconductor device. SOLUTION: The semiconductor device is composed of a multilayer wiring board provided with a plurality of lands 23d, a semiconductor chip flip-chip-connected with the lands 23d arranged aligned like a lattice on the surface layer of the multilayer wiring board, a plurality of gold bumps arranged between the multilayer wiring board and the semiconductor chip, a plurality of solder balls provided on the multilayer wiring board, and a sealing part arranged in the periphery of the gold bumps and formed by underfill sealing. The plurality of lands 23d for flip-chip connection on the multilayer wiring board have a plularity of kinds of land diameters and are provided with a plurality of kinds of pitches, thereby increasing the number of effective pins to enable the high density packaging and to improve the electrical characteristic of a BGA. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了实现高密度封装和改善半导体器件的电气特性。解决方案：半导体器件由多层布线板构成，多层布线板设置有多个焊盘23d，半导体芯片与在多层布线板的表面层上排列成阵列的焊盘23d倒装芯片连接，布置在多层布线板和半导体芯片之间的多个金凸块，设置在多层布线板上的多个焊球，以及设置在金凸块的周围并通过底部填充密封形成的密封部。在多层布线基板上进行倒装芯片连接的多个焊盘23d具有一定数量的焊盘直径，并且具有多种间距，从而增加了有效引脚的数量，以实现高密度封装并提高 BGA的电气特性。版权所有（C）2005，JPO＆NCIPI

4. 发明专利

JP2010093106A Semiconductor device and method for manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2010093106A
公开(公告)日：2010-04-22
申请号：JP2008262647
申请日：2008-10-09
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： AKIBA TOSHIHIKO , NAITO TAKAHIRO , KINOSHITA YOSHIHIRO , KIKUCHI TAKU , KISHIKAWA NORIO
IPC分类号： H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L24/97 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48479 , H01L2224/73204 , H01L2224/73265 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01024 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/07802 , H01L2924/181 , H01L2224/48471 , H01L2224/81 , H01L2224/85 , H01L2924/00 , H01L2224/4554
摘要： PROBLEM TO BE SOLVED: To promote reduction in the size and thickness of a system in package (SiP) configured by laminating a plurality of semiconductor chips on a wiring board. SOLUTION: Bonding pads 13 of a logic chip 2 which is flip-flop mounted on a main surface of a wiring board 1 by a face-down method and lands 5a of the wiring board 1 are connected to barrier metal layers 14 and solder layers 15 which are formed on the bonding pads 13 through stud bumps 16s formed on respective lands 5a. Bonding pads 20 on a memory chip 3 mounted on the upper part of the logic chip 2 by a face-up method are connected to the lands 5a on the wiring board 1 through barrier metal layers 21 and Au wires 22 formed on respective bonding pads 20. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：解决的问题：为了促进通过在布线板上层叠多个半导体芯片而构成的封装体系（SiP）的尺寸和厚度的降低。解决方案：通过面朝下方法安装在布线板1的主表面上的触发器的逻辑芯片2的接合焊盘13和布线板1的焊盘5a连接到阻挡金属层14和焊料层15，其形成在接合焊盘13上，通过形成在相应的焊盘5a上的柱形突起16形成。通过面朝上方法安装在逻辑芯片2的上部的存储芯片3上的接合焊盘20通过形成在各个接合焊盘20上的阻挡金属层21和Au线22连接到布线板1上的焊盘5a 。版权所有（C）2010，JPO＆INPIT

5. 发明专利

JP2008078367A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2008078367A
公开(公告)日：2008-04-03
申请号：JP2006255548
申请日：2006-09-21
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： KIKUCHI TAKU , KANEMOTO KOICHI , MIYAZAKI CHUICHI , SHIOTSUKI TOSHIHIRO
IPC分类号： H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L24/83 , H01L23/3128 , H01L23/49575 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/78 , H01L24/85 , H01L24/97 , H01L25/0657 , H01L2224/05554 , H01L2224/274 , H01L2224/29111 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48175 , H01L2224/48227 , H01L2224/48247 , H01L2224/48465 , H01L2224/48599 , H01L2224/49113 , H01L2224/4912 , H01L2224/49171 , H01L2224/49174 , H01L2224/49175 , H01L2224/73265 , H01L2224/78301 , H01L2224/83191 , H01L2224/8385 , H01L2224/85181 , H01L2224/92 , H01L2224/97 , H01L2225/0651 , H01L2225/06562 , H01L2924/0001 , H01L2924/01005 , H01L2924/01006 , H01L2924/01012 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01038 , H01L2924/01047 , H01L2924/0105 , H01L2924/01051 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/0133 , H01L2924/0134 , H01L2924/014 , H01L2924/0665 , H01L2924/07802 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/15738 , H01L2924/15747 , H01L2924/1576 , H01L2924/181 , H01L2924/30105 , H01L2924/3511 , H01L2924/00014 , H01L2224/85 , H01L2224/83 , H01L2224/92247 , H01L2924/00 , H01L2924/3512 , H01L2924/00012 , H01L2924/01028 , H01L2224/29099
摘要： PROBLEM TO BE SOLVED: To improve reliability of a semiconductor device which has a constitution for housing a plurality of semiconductor chips of different planar sizes in the same sealing body in a stack through an adherent insulating film. SOLUTION: In a semiconductor device 1A having a constitution for housing a plurality of semiconductor chips 2M1, 2M2, 2C of different planar sizes in the same sealing body 4 in a stack through DAFs 5a to 5c, the DAF5c in a rear of an uppermost semiconductor chip 2C wherein a control circuit is formed is made thicker than each of DAF5a, 5b in a rear of lower semiconductor chips 2M1, 2M2 wherein a memory circuit is formed. Thereby, it is possible to reduce defect that a bonding wire connecting the uppermost semiconductor chip 2C and a wiring substrate 3 comes into contact with a major surface corner part of the lower semiconductor chip 2M2. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了提高半导体器件的可靠性，该半导体器件具有通过粘附绝缘膜在堆叠中的相同密封体中容纳不同平面尺寸的多个半导体芯片的结构。解决方案：在具有通过DAF 5a至5c在堆叠中的同一密封体4中容纳不同平面尺寸的多个半导体芯片2M1,2M2,2C的结构的半导体器件1A中，DAF5c位于其中形成有控制电路的最上面的半导体芯片2C被制成比形成有存储电路的下半导体芯片2M1,2M2的后面的DAF5a，5b中的每一个更厚。因此，可以减少连接最上半导体芯片2C和布线基板3的接合线与下半导体芯片2M2的主表面角部接触的缺陷。版权所有（C）2008，JPO＆INPIT

6. 发明专利

JP2004363289A Manufacturing method for semiconductor device 审中-公开
公开(公告)号：JP2004363289A
公开(公告)日：2004-12-24
申请号：JP2003159305
申请日：2003-06-04
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： KAWAKAMI MASARU , KIKUCHI TAKU , NISHIDA TAKAFUMI , KOYAMA HIROSHI
IPC分类号： H01L23/12 , G05B19/4155 , H01L25/10 , H01L25/11 , H01L25/18
CPC分类号： G05B19/4155 , G05B2219/34343 , G05B2219/42189 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/92125 , H01L2924/15151 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To improve the quality of a semiconductor device. SOLUTION: A semiconductor chip 1 is connected to the surface 3a of a package board 3 having a through-hole 3c via flip chip bonding. A sealing resin 12 is injected from the back surface 3b side of the package board 3 via the through-hole 3c to supply the sealing resin 12 between the semiconductor chip 1 and the package board 3. Then a plurality of solder balls are formed on the outside periphery of the semiconductor chip 1 on the package board 3 to build a first package structure. Another first package structure is superimposed on the surface 3a of the package board 3 of the above first package structure to build a laminated package. Since the sealing resin 12 is injected from the back surface 3b side of the package board 3 via the through-hole 3c in a sealing process, the sealing resin 12 is prevented from sticking to a land at the outside of the chip 1 of the board 3, which improves the quality of the laminated package. COPYRIGHT: (C)2005,JPO&NCIPI

7. 发明专利

JP2008251786A Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2008251786A
公开(公告)日：2008-10-16
申请号：JP2007090558
申请日：2007-03-30
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： KANEMOTO KOICHI , KIKUCHI TAKU , SUZUKI KAZUNARI , SHIOTSUKI TOSHIHIRO
IPC分类号： H01L21/52 , H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2924/15311 , H01L2924/00014
摘要： PROBLEM TO BE SOLVED: To provide a technique for increasing a reliability in a semiconductor device.
SOLUTION: A semiconductor device comprises a semiconductor chip (first semiconductor chip) 3 having a main surface (first main surface) 3a and a main surface (second main surface) 3b located at a position opposed to the main surface 3a, a lead frame (carrier substrate) for carrying the semiconductor chip 3, a resin film (first film layer) 7 tightly mounted onto the main surface 3b of the semiconductor chip 3, and an adhesive (first adhesive layer) 8 for tightly mounting the semiconductor chip 3 onto the lead frame. The Young's modulus of the adhesive 8 is set to be smaller than the Young's modulus of the resin film 7.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于提高半导体器件的可靠性的技术。解决方案：半导体器件包括具有主表面（第一主表面）3a和位于与主表面3a相对的位置的主表面（第二主表面）3b的半导体芯片（第一半导体芯片）3，用于承载半导体芯片3的引线框架（载体基板），紧密地安装在半导体芯片3的主表面3b上的树脂膜（第一膜层）7和用于紧密地安装半导体芯片的粘合剂 3到引线框架上。粘合剂8的杨氏模量被设定为小于树脂膜7的杨氏模量。版权所有：（C）2009，JPO＆INPIT

8. 发明专利

JP2005039020A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2005039020A
公开(公告)日：2005-02-10
申请号：JP2003199467
申请日：2003-07-18
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： KAWAKAMI MASARU , KIKUCHI TAKU , KAWAKUBO HIROSHI , KIMOTO RYOSUKE , IMURA CHIKAKO , SHIBAMOTO MASAKUNI
IPC分类号： H01L25/18 , H01L25/10 , H01L25/11
CPC分类号： H01L2224/73204 , H01L2924/01019 , H01L2924/15311
摘要： PROBLEM TO BE SOLVED: To mount a semiconductor device of a structure in which wiring boards are laminated, in a high density. SOLUTION: The semiconductor device includes a multilayer substrate 43, a first step chip 47 electrically connected to the multilayer substrate 43, other package substrate 33 laminated in three steps on the multilayer substrate 43 and connected to the wiring board of a lower stage via a solder ball 37, second step chip 48, third step chip 49 and fourth step chip 50 electrically connected to and mounted on the other package substrate 33 laminated in three steps, and a plurality of solder balls 35 provided on the multilayer substrate 43 of the lowermost layer. The multilayer substrate 43 of the lowermost layer for mounting logic chips can incorporate the wiring layer not used for detouring to the solder ball 35 by increasing the wiring layer more than the package substrate 33 for mounting memory chip. The laminated package 46 can be mounted in higher density by using the wiring of the wiring layer to mount other semiconductor element, passive component, etc. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：以高密度安装层叠有布线板的结构的半导体器件。解决方案：半导体器件包括多层基板43，与多层基板43电连接的第一台阶芯片47，在多层基板43上三层叠的其他封装基板33，并与下层的布线基板连接电连接并安装在三个层叠的另一个封装基板33上的焊锡球37，第二台阶芯片48，第三阶梯芯片49和第四台阶芯片50以及设置在多层基板43上的多个焊球35 最下层。用于安装逻辑芯片的最下层的多层基板43可以通过比用于安装存储芯片的封装基板33增加布线层，而将不用于迂回的布线层结合到焊球35。可以通过使用布线层的布线来安装其它半导体元件，无源元件等，以更高的密度来安装层叠封装。（C）2005，JPO＆NCIPI

9. 发明专利

JP2007227537A Non-volatile storage device 有权
标题翻译：非易失存储器件
公开(公告)号：JP2007227537A
公开(公告)日：2007-09-06
申请号：JP2006045463
申请日：2006-02-22
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： HANAWA KAZUKO , KIKUCHI TAKU , KANEMOTO KOICHI , SUGIYAMA MICHIAKI , IMURA CHIKAKO
IPC分类号： H01L25/18 , H01L21/8247 , H01L25/065 , H01L25/07 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L25/18 , G11C5/06 , H01L24/45 , H01L24/73 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48145 , H01L2224/48147 , H01L2224/48227 , H01L2224/49171 , H01L2224/73265 , H01L2225/06506 , H01L2225/0651 , H01L2225/06555 , H01L2225/06562 , H01L2225/06586 , H01L2924/01014 , H01L2924/01037 , H01L2924/01079 , H01L2924/10253 , H01L2924/15311 , H01L2924/181 , H01L2924/30107 , H01L2924/3011 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a non-volatile storage device having realization of reduction in size and mass-productivity while acquiring reliability and signal transmitting performance. SOLUTION: The non-volatile memory chip having a first side where a pad is not formed and a second side where a pad is formed is mounted on a mounting substrate. A control chip for controlling the non-volatile memory chip is mounted on the same non-volatile memory chip. The control chip has a first pad line corresponding to the pad of the non-volatile memory chip. This first pad line is provided in proximity to the first side of the non-volatile memory chip. The first pad line of the control chip is connected to a first electrode line formed on the mounting substrate via a first wire group. The pad of the non-volatile memory chip and a second electrode line formed on the mounting substrate are connected via a second wire group. The first electrode line and the second electrode lie are connected via a wiring formed on the mounting substrate. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种在获取可靠性和信号传输性能的同时实现尺寸和批量生产率的实现的非易失性存储装置。解决方案：具有不形成焊盘的第一侧的非易失性存储器芯片和形成焊盘的第二侧安装在安装基板上。用于控制非易失性存储器芯片的控制芯片安装在相同的非易失性存储器芯片上。控制芯片具有对应于非易失性存储芯片的焊盘的第一焊盘线。该第一焊盘线设置在非易失性存储芯片的第一侧附近。控制芯片的第一焊盘线经由第一线组连接到形成在安装基板上的第一电极线。非易失性存储芯片的焊盘和形成在安装基板上的第二电极线经由第二线组连接。第一电极线和第二电极通过形成在安装基板上的布线连接。版权所有（C）2007，JPO＆INPIT

10. 发明专利

JP2007027287A Semiconductor device and its manufacturing process 审中-公开
标题翻译：半导体器件及其制造工艺
公开(公告)号：JP2007027287A
公开(公告)日：2007-02-01
申请号：JP2005205027
申请日：2005-07-14
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： KIKUCHI TAKU , KANEMOTO KOICHI , SUGIYAMA MICHIAKI , KAWAKUBO HIROSHI
IPC分类号： H01L23/12 , G06K19/077 , H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H05K1/111 , H01L21/4853 , H01L23/49816 , H01L23/5386 , H01L24/45 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L25/50 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/48465 , H01L2224/73265 , H01L2225/06562 , H01L2225/06568 , H01L2225/06586 , H01L2924/00014 , H01L2924/01057 , H01L2924/01079 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H05K3/3452 , H05K3/3484 , H05K2201/09381 , H05K2201/09418 , H05K2201/0989 , H05K2201/099 , H05K2201/10734 , H05K2203/043 , Y02P70/611 , H01L2924/00 , H01L2924/00012 , H01L2224/05599
摘要： PROBLEM TO BE SOLVED: To provide a technology for enhancing packaging performance of a semiconductor device. SOLUTION: A package substrate 3 having a plurality of lands 3d of NSMD structure, and a take-out wiring 3i and dummy wiring 3j connected with the plurality of lands 3d, respectively, and arranged at positions of 180° symmetry is prepared. Since solder is printed on the plurality of lands 3d by printing method after a package is assembled, variation in height of solder coat can be reduced between lands and thereby packaging performance of LGA (semiconductor device) 7 is enhanced. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于提高半导体器件的封装性能的技术。解决方案：制备具有多个NSMD结构的焊盘3d的封装基板3和分别布置在180度对称位置上的与多个焊盘3d连接的引出布线3i和虚设布线3j以及虚设布线3j 。由于在组装封装之后通过印刷方法将焊料印刷在多个焊盘3d上，因此可以在焊盘之间降低焊料涂层的高度变化，从而提高LGA（半导体器件）7的封装性能。版权所有（C）2007，JPO＆INPIT

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式