专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JP2006178701A Memory card 审中-公开
标题翻译：存储卡
公开(公告)号：JP2006178701A
公开(公告)日：2006-07-06
申请号：JP2004370512
申请日：2004-12-22
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： SHINOHARA MINORU , YAMADA YUICHIRO , WADA TAMAKI
IPC分类号： G06K19/077
摘要： PROBLEM TO BE SOLVED: To improve the reliability of a memory card by sharply reducing defective connection between a printed board and a connector due to ejection of the memory card from a slot. SOLUTION: In a memory card 1 to be used for a playing machine such as Pachinko, fixing projection parts 2b, 3b are respectively formed on the inner surface of one long side of each of caps 2, 3 consisting of acrylic resin in the vicinity of the outer peripheral part of the long side. On both the side faces of a connector 6 joined to the printed board 4, engaging grooves 6 1 are formed in the longitudinal direction. In the case of forming a case of the memory card 1 by superposing the caps 2, 3 on each other, the engaging grooves 6 1 of the connector 6 are respectively engaged with the fixing projection parts 2b, 3b of the caps 2, 3 to fix the connector 6. Consequently the connector 6 joined to the printed board 4 is fixed and application of stress to a joint part between the printed board 4 and the connector 6 at the time of inserting/ejecting the memory card 1 can be prevented. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：通过大大减少由于存储卡从插槽中的弹出而导致的印刷电路板和连接器之间的连接不良，从而提高存储卡的可靠性。解决方案：在用于诸如弹球的游戏机的存储卡1中，固定突起部分2b，3b分别形成在由丙烯酸树脂构成的每个盖子2,3的一个长边的内表面上长边的外周部附近。在连接到印刷电路板4的连接器6的两个侧面上，沿着纵向方向形成有接合槽6＆lt; SB＆gt; 1＆lt; / SB＆gt;。在通过将盖2,3彼此重叠形成存储卡1的情况下，连接器6的接合槽6 1 分别与固定突起部2b，3b接合因此，连接到印刷电路板4的连接器6在插入/弹出存储器时被固定并施加到印刷电路板4和连接器6之间的接合部分卡1可以防止。版权所有（C）2006，JPO＆NCIPI

2. 发明专利

JP2009212486A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2009212486A
公开(公告)日：2009-09-17
申请号：JP2008198535
申请日：2008-07-31
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： SHINOHARA MINORU , SUGIYAMA MICHIAKI , ARAKI MAKOTO
IPC分类号： H01L25/065 , G06K19/077 , H01L21/60 , H01L23/52 , H01L25/07 , H01L25/18 , H01L27/00
CPC分类号： G06F1/185 , G11C5/02 , G11C5/063 , H01L23/5388 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/97 , H01L25/0657 , H01L25/18 , H01L2224/05553 , H01L2224/05554 , H01L2224/45144 , H01L2224/48091 , H01L2224/48137 , H01L2224/48145 , H01L2224/48225 , H01L2224/48227 , H01L2224/49171 , H01L2224/49175 , H01L2224/97 , H01L2225/06506 , H01L2225/0651 , H01L2225/06527 , H01L2225/06562 , H01L2225/06572 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01023 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/1815 , H01L2924/19041 , H01L2924/30105 , H01L2924/00014 , H01L2224/85 , H01L2924/00 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To improve the degree of freedom in wirings for connecting memory chips and a control chip in a semiconductor device having a package structure in which the memory chips and the control chip are stacked on a wiring board. SOLUTION: The memory card 1A includes: a wiring board 2; four memory chips M1 to M4 stacked on a main surface of the wiring board; and a controller chip 3 and an interposer 4, both mounted on a surface of the memory chip M4 of the uppermost layer. Each of the memory chips M1 to M4 is stacked on the surface of the wiring board 2 so that its long side is directed in the same direction as the long side of the wiring board 2. The memory chip M1 of the lowermost layer is mounted on the wiring board 2 in a dislocated manner by a predetermined distance in the direction toward the front end portion of the memory card 1A so that it does not overlap the pads 9 of the wiring board 2. The three memory chips M2 to M4 stacked on the memory chip M1 are disposed so that their short sides on the side in which the pads 6 are formed are located at the front end portion of the memory card 1A. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：为了提高具有封装结构的半导体器件中的存储器芯片和控制芯片连接的自由度，其中存储器芯片和控制芯片堆叠在布线板上。存储卡1A包括：布线板2; 堆叠在布线板的主表面上的四个存储芯片M1至M4; 以及安装在最上层的存储芯片M4的表面上的控制器芯片3和插入件4。每个存储芯片M1至M4堆叠在布线板2的表面上，使得其长边指向与布线板2的长边相同的方向。最下层的存储芯片M1安装在布线板2以与存储卡1A的前端部分相反的方向偏移预定距离，使得其不与布线板2的焊盘9重叠。堆叠在存储卡1A上的三个存储芯片M2至M4 存储芯片M1被布置成使得它们在形成焊盘6的一侧上的短边位于存储卡1A的前端部分。版权所有（C）2009，JPO＆INPIT

3. 发明专利

JP2008301329A Wireless communication system, sim card, mobile communication terminal, and data guarantee method 审中-公开
标题翻译：无线通信系统，SIM卡，移动通信终端和数据保护方法
公开(公告)号：JP2008301329A
公开(公告)日：2008-12-11
申请号：JP2007146648
申请日：2007-06-01
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： NISHIZAWA HIROTAKA , KOIKE HIDEO , IWASAKI HIRONORI , OSAKO JUNICHIRO , SHINOHARA MINORU , WADA TAMAKI
IPC分类号： G06F12/00 , H04M3/00 , H04W8/20 , H04W12/06
CPC分类号： H04W8/20 , H04L63/0853 , H04W12/06
摘要： PROBLEM TO BE SOLVED: To prevent a loss of the stored data due to physical breakage of a secure memory card such as a SIM card. SOLUTION: A host part 8 executes card authentication of a memory card 9. When the authentication is OK, update data of the memory card 9 is transmitted by security communication so as to execute data update. Then, the host part 8 outputs a request for mirror update of card data to a base-station server 5. When access is allowed, the card data is transmitted to the base-station server 5 via the host part 8 so as to execute mirror update of the card data. When the mirror update of the card data is finished, the base-station server 5 sends a finish confirmation replay to the host part 8 and data backup processing is finished. In this way, data of the memory card 9 is subjected to mirror update by the base-station server 5 so as to prevent a loss of the stored data. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：为了防止由于诸如SIM卡的安全存储卡的物理破坏而导致的存储数据的丢失。主机部8执行存储卡9的卡认证。当认证为OK时，通过安全通信发送存储卡9的更新数据，以执行数据更新。然后，主机部8向基站服务器5输出卡数据的镜像更新请求。当允许访问时，经由主机部8将卡数据发送到基站服务器5，以执行镜像更新卡片数据。当卡数据的镜像更新结束时，基站服务器5向主机部8发送完成确认重放，数据备份处理结束。以这种方式，存储卡9的数据由基站服务器5进行镜像更新，以防止存储数据的丢失。版权所有（C）2009，JPO＆INPIT

4. 发明专利

JP2008300588A Electronic apparatus, and manufacturing method thereof 审中-公开
标题翻译：电子设备及其制造方法
公开(公告)号：JP2008300588A
公开(公告)日：2008-12-11
申请号：JP2007144492
申请日：2007-05-31
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： SHINOHARA MINORU , SONOBE TAKAO , IWASAKI HIRONORI
IPC分类号： H01L23/29 , H01L23/28 , H01L23/31 , H01L25/00
CPC分类号： H01L2224/48091 , H01L2224/48247 , H01L2924/00014
摘要： PROBLEM TO BE SOLVED: To improve reliability in an electronic apparatus in which semiconductor devices are mounted. SOLUTION: By the formation of a first portion 7e in which a substrate 7g is exposed and a second portion 7h protruding toward a first sealing body 2e from the substrate 7g in a region facing opposedly the first sealing body 2e of a TSOP2 in the main plane 7a of a wiring substrate 7, when in solder connecting the TSOP2, the first sealing body 2e can be supported by the second portion 7h of the wiring substrate 7, a sufficient clearance can be formed between the first sealing body 2e and the first portion 7e of the wiring substrate 7. Thereby, a resin for sealing can be filled up between the first sealing body 2e of the TSOP2 when sealing memory module 3 with resin and the wiring substrate 7 making it possible to prevent the deformation of the first sealing body 2e and the wiring substrate 7. As the result, the improvement of reliability of a memory module 3 can be attained. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：为了提高安装半导体器件的电子设备的可靠性。解决方案：通过形成基板7g露出的第一部分7e和从基板7g朝向第一密封体2e突出的第二部分7h，该区域与TSOP2的第一密封体2e相对地布线基板7的主面7a，当连接TSOP2的焊料时，第一密封体2e可以被布线基板7的第二部分7h支撑，在第一密封体2e和第二密封体2e之间可以形成足够的间隙因此，当密封存储器模块3与树脂时，可以在TSOP2的第一密封体2e和布线基板7之间填充用于密封的树脂，从而可以防止第一部分7e的变形密封体2e和布线基板7.结果，可以实现存储模块3的可靠性的提高。版权所有（C）2009，JPO＆INPIT

5. 发明专利

JP2007287820A Electronic device, and manufacturing method therefor 有权
标题翻译：电子设备及其制造方法
公开(公告)号：JP2007287820A
公开(公告)日：2007-11-01
申请号：JP2006111661
申请日：2006-04-14
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： SHINOHARA MINORU , KOMATSU SATORU
IPC分类号： H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L24/97 , H01L21/565 , H01L24/73 , H01L25/0652 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48145 , H01L2224/48227 , H01L2224/73265 , H01L2224/97 , H01L2225/06562 , H01L2924/01005 , H01L2924/01006 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2224/83 , H01L2224/85 , H01L2924/00 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide a novel semiconductor module which is compact and high reliable. SOLUTION: The semiconductor module 1 is provided with a hollow part 4 formed by a frame 10, first and second wiring boards 20 and 40, a first semiconductor device 30 which is mounted to the first wiring board 20 and is placed in the hollow part 4, a second semiconductor device 50 which is mounted to the second wiring board 40 and is placed in the hollow part 4, and a resin packaging body 5 to package the frame 10 and the first wiring board 20. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种紧凑且高可靠性的新型半导体模块。解决方案：半导体模块1设置有由框架10，第一和第二布线板20和40形成的中空部分4，安装到第一布线板20并被放置在第一布线板20中的第一半导体器件30。中空部分4，安装到第二布线板40并放置在中空部分4中的第二半导体装置50以及用于封装框架10和第一布线板20的树脂封装体5.版权：（C）2008，JPO＆INPIT

6. 发明专利

JP2010147090A Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2010147090A
公开(公告)日：2010-07-01
申请号：JP2008319938
申请日：2008-12-16
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： SHINOHARA MINORU , INOUE TOMIFUMI , TSUKUI SEIICHIRO
IPC分类号： H01L25/10 , H01L25/11 , H01L25/18
CPC分类号： H01L23/49816 , H01L21/561 , H01L23/3128 , H01L23/5385 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/97 , H01L25/0655 , H01L25/105 , H01L25/18 , H01L2224/05554 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48095 , H01L2224/48227 , H01L2224/48228 , H01L2224/48465 , H01L2224/49171 , H01L2224/73265 , H01L2224/97 , H01L2225/1023 , H01L2225/1058 , H01L2225/1076 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/10161 , H01L2924/10162 , H01L2924/15173 , H01L2924/15183 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/1815 , H01L2924/19041 , H01L2924/19105 , H01L2924/30105 , H01L2924/3511 , H01L2224/85 , H01L2924/00 , H01L2924/00012 , H01L2224/05599
摘要： PROBLEM TO BE SOLVED: To improve reliability in a semiconductor device. SOLUTION: A POP-type semiconductor device is comprised of an upper-side second semiconductor package laminated on a lower-side first semiconductor package 7. Two or more main surface side lands 2e of a first wiring substrate 2 on the first semiconductor package 7 are arranged such that they are given out on both sides of a chip mounting region situated at the central part of the main surface 2a as a border, thereby the through mold method can be adopted. Hereby, a first sealing object 4 formed on the main surface 2a of the first wiring substrate 2 on the lower-side first semiconductor package 7 is formed from the central part of one second side 2n of the first wiring substrate 2 toward the central part of the other second side 2n, thereby strength in relation to curvature of the lower-side first wiring substrate 2 can be enhanced, and the reliability of the POP-type semiconductor device is improved. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提高半导体器件的可靠性。解决方案：POP型半导体器件由层叠在下侧第一半导体封装7上的上侧第二半导体封装构成。第一半导体层上的第一布线基板2的两个以上的主面侧焊盘2e 封装7被布置成使得它们在位于主表面2a的中心部分的芯片安装区域的两侧作为边界被放出，从而可以采用贯通模制方法。因此，形成在下侧第一半导体封装7上的第一布线基板2的主表面2a上的第一密封件4由第一布线基板2的一个第二边2n的中心部朝向第一布线基板2的中央部分另一方的第二面2n能够提高与下侧的第一布线基板2的弯曲强度，提高了POP型半导体装置的可靠性。版权所有（C）2010，JPO＆INPIT

7. 发明专利

JP2009188328A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2009188328A
公开(公告)日：2009-08-20
申请号：JP2008029141
申请日：2008-02-08
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： SHINOHARA MINORU , SUGIYAMA MICHIAKI , NISHI TAKAOMI , KOYAMA MASAAKI
IPC分类号： H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L2224/45144 , H01L2224/48091 , H01L2224/48463 , H01L2224/49107 , H01L2224/73265 , H01L2924/10253 , H01L2924/13091 , H01L2924/00014 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To miniaturize a semiconductor device such as a memory card formed by laminating a memory chip and a controller chip on a wiring substrate. SOLUTION: In the memory card 1A, relocation wiring 6 is formed on the surface of the memory chip M2, pads are disposed at its both ends is electrically connected to the wiring substrate 2 and elements (the memory chips M1, M2, the controller chip 3 and a chip capacitor 4) on the wiring substrate 2 by the relocation wiring 6 and Au wires connected to the pads. Thus the wiring substrate 2 is connected to the elements on the wiring substrate 2 by the short Au wires 11, 14. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：通过在布线基板上层叠存储芯片和控制器芯片而形成的存储卡等半导体装置的小型化。解决方案：在存储卡1A中，在存储芯片M2的表面上形成有重定位布线6，其两端的焊盘与布线基板2和元件（存储芯片M1，M2，控制器芯片3和片状电容器4）通过重定位布线6和连接到焊盘的Au布线布置在布线基板2上。因此，布线基板2通过短Au线11,14连接到布线基板2上的元件。（C）2009，JPO＆INPIT

8. 发明专利

JP2009147134A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2009147134A
公开(公告)日：2009-07-02
申请号：JP2007323293
申请日：2007-12-14
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： SHINOHARA MINORU
IPC分类号： H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L23/49575 , H01L23/525 , H01L24/05 , H01L24/06 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/18 , H01L2224/04042 , H01L2224/05553 , H01L2224/05554 , H01L2224/05556 , H01L2224/05599 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/45015 , H01L2224/45144 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/48247 , H01L2224/48465 , H01L2224/48599 , H01L2224/4903 , H01L2224/49051 , H01L2224/49107 , H01L2224/49175 , H01L2224/73265 , H01L2224/85399 , H01L2225/06562 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/1306 , H01L2924/13091 , H01L2924/181 , H01L2924/1815 , H01L2924/3025 , H01L2924/00 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To achieve miniaturization and thinning of a semiconductor device onto which semiconductor chips are laminated. SOLUTION: In a laminated primary memory chip and secondary memory chip 2, a primary pad of the primary memory chip on the lower stage hidden under the upper secondary memory chip 2 is pulled out through re-wiring, thus making it possible to wire-connect the primary pad pushed out and exposed from the upper-stage secondary memory chip 2 and a secondary pad 2d of the upper-stage secondary memory chip 2. Further, a microcomputer chip 3 and a tertiary pad 2e formed on a re-wire 2f are connected by wire 4 on the uppermost-stage secondary memory chip 2, thereby enabling wire-connection of multiple laminated memory chips to be realized with no intervention of spacers. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：为了实现其上层叠半导体芯片的半导体器件的小型化和薄化。解决方案：在层叠的一次存储芯片和二次存储芯片2中，通过重新布线将通过上层次存储芯片2隐藏在下层的主存储芯片的主焊盘拉出，从而使得可以将从上级副存储芯片2推出并暴露的主焊盘电线连接到上级副存储芯片2的辅助焊盘2d。此外，微型芯片3和第三焊盘2e形成在重新连接线2f通过导线4连接在最上层次级存储芯片2上，从而能够实现多层叠存储芯片的线连接，而不需要间隔物的介入。版权所有（C）2009，JPO＆INPIT

9. 发明专利

JP2007173606A Electronic device and its manufacturing method 有权
标题翻译：电子设备及其制造方法
公开(公告)号：JP2007173606A
公开(公告)日：2007-07-05
申请号：JP2005370587
申请日：2005-12-22
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： SHINOHARA MINORU
IPC分类号： H01L25/18 , H01L23/00 , H01L25/04
CPC分类号： H01L2224/48247
摘要： PROBLEM TO BE SOLVED: To reduce the erroneous mounting of a semiconductor memory device to a socket and reduce the number of times of mounting to the socket. SOLUTION: The electronic device is provided with a plurality of semiconductor devices in which semiconductor chips are sealed by a resin sealing body, and a plurality of first terminals for external connection electrically connected to the semiconductor chips are projected out of the resin sealing body; a wiring substrate having a main surface and a rear surface which are positioned on the opposite side of each other and the plurality of semiconductor devices are mounted on the main surface; and a cover member provided on the main surface of the wiring substrate so as to cover the plurality of semiconductor devices. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了减少半导体存储器件错误地安装到插座上并减少安装到插座的次数。解决方案：电子设备设置有多个半导体器件，其中半导体芯片被树脂密封体密封，并且多个用于外部连接的第一端子电连接到半导体芯片从树脂密封件中突出出来身体; 具有主表面和后表面的布线基板彼此相对并且多个半导体器件安装在主表面上; 以及设置在所述布线基板的主表面上以覆盖所述多个半导体器件的盖构件。版权所有（C）2007，JPO＆INPIT

10. 发明专利

JP2004349396A Semiconductor device and its manufacturing method 审中-公开
公开(公告)号：JP2004349396A
公开(公告)日：2004-12-09
申请号：JP2003143545
申请日：2003-05-21
申请人： Renesas Eastern Japan Semiconductor Inc , Renesas Technology Corp , 株式会社ルネサステクノロジ , 株式会社ルネサス東日本セミコンダクタ
发明人： SHIMOISHI TOMOAKI , SHINOHARA MINORU , TAKAHASHI HIDEYUKI
IPC分类号： G06K19/077 , H05K1/02 , H05K3/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device effectively applicable to a CF card, and also to provide its manufacturing technology which reduces a cost of the CF card. SOLUTION: A printed wiring board 3 of the CF card 1 is formed into an L-shaped planar shape. The printed wiring board 3 comprises a broad region 3a and a strip region 3b of a narrow width. In the broad region 3a, electronic components 4 such as packages 4a and 4c and a chip component 4b are mounted. To a long side of the strip region 3b, a connector 5 to be used for connection with an external device is attached. By the L-shaped planar shape of the printed wiring board 3, a free area 6 is formed inside a housing 2 of the CF card 1. COPYRIGHT: (C)2005,JPO&NCIPI

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式