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1. 发明专利

JP2003309182A Method of manufacturing semiconductor device and semiconductor device 审中-公开
标题翻译：制造半导体器件和半导体器件的方法
公开(公告)号：JP2003309182A
公开(公告)日：2003-10-31
申请号：JP2002114967
申请日：2002-04-17
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： OKAZAKI TSUTOMU , OKADA DAISUKE , IKEDA YOSHIHIRO , TSUKAMOTO KEISUKE , FUKUMURA TATSUYA , YADORI SHOJI , HARAGUCHI KEIICHI , KISHI KOJI
IPC分类号： H01L21/8247 , H01L21/20 , H01L21/334 , H01L21/82 , H01L21/822 , H01L21/8234 , H01L21/8239 , H01L21/8242 , H01L27/04 , H01L27/06 , H01L27/088 , H01L27/10 , H01L27/105 , H01L27/115 , H01L29/78 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11536 , H01L27/105 , H01L27/115 , H01L27/11526 , H01L29/66181 , H01L29/7833
摘要： PROBLEM TO BE SOLVED: To provide a technique by which the capacity of a capacitor per unit area can be improved and a manufacturing process associated with the improvement can be simplified.
SOLUTION: The capacity of the capacitor per unit area is improved by increasing the surface area of the capacitor by forming at least one or more uneven capacitor forming grooves 4a on the surface of a capacitor forming area. In addition, the manufacturing process of the capacitor can be simplified by forming the grooves 4a and element separating grooves 4 formed on the surface of a semiconductor substrate 1 in the same step. Moreover, a dielectric film 16a of the capacitor formed in the capacitor forming area and a gate insulating film 16 for high withstand voltage formed in an MISFET forming area are formed in the same step. Alternatively, the dielectric film 16a of the capacitor formed in the capacitor forming area and a memory/gate interlayer film 11 formed between polycrystalline silicon layers 10a and 17 in a memory cell forming area are formed in the same step.
COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：提供一种可以提高每单位面积的电容器的容量并且可以简化与改进相关的制造工艺的技术。解决方案：通过在电容器形成区域的表面上形成至少一个或多个不均匀的电容器形成槽4a来增加电容器的表面积来提高每单位面积电容器的容量。此外，通过在同一步骤中形成形成在半导体衬底1的表面上的沟槽4a和元件分离槽4，可以简化电容器的制造工艺。此外，在同一步骤中形成在电容器形成区域中形成的电容器的电介质膜16a和形成在MISFET形成区域中的高耐压栅极绝缘膜16。或者，形成在电容器形成区域中的电容器的电介质膜16a和形成在存储单元形成区域中的多晶硅层10a和17之间的存储/栅极层间膜11形成在同一步骤中。版权所有（C）2004，JPO

2. 发明专利

JP2003078040A Semiconductor integrated circuit device and its fabricating method 有权
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：JP2003078040A
公开(公告)日：2003-03-14
申请号：JP2001263736
申请日：2001-08-31
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： TSUKAMOTO KEISUKE , IKEDA YOSHIHIRO , OKAZAKI TSUTOMU , OKADA DAISUKE , YANAGIDA HIROSHI
IPC分类号： H01L29/78 , H01L21/8247 , H01L27/10 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11543
摘要： PROBLEM TO BE SOLVED: To reduce leak current by reducing defects in an element forming region for forming the memory cells of a nonvolatile memory.
SOLUTION: End part of an element forming region Ac for forming nonvolatile memory cells is elongated by a length D utilizing the region beneath a dummy conductive film DSG and stress applied from an insulation film 6 surrounding the element forming region Ac is concentrated in the elongated region. Since a defect does not extend to the region for forming a memory cell, leak current of the memory cell can be reduced.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：通过减少用于形成非易失性存储器的存储单元的元件形成区域中的缺陷来减少泄漏电流。解决方案：用于形成非易失性存储单元的元件形成区域Ac的端部利用虚设导电膜DSG下面的区域延伸长度D，并且从围绕元件形成区域Ac的绝缘膜6施加的应力集中在细长区域。由于缺陷不延伸到用于形成存储单元的区域，所以可以减小存储单元的泄漏电流。

3. 发明专利

JP2003023117A Method for manufacturing semiconductor integrated circuit device 审中-公开
标题翻译：制造半导体集成电路器件的方法
公开(公告)号：JP2003023117A
公开(公告)日：2003-01-24
申请号：JP2001209542
申请日：2001-07-10
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： WATANABE KEIZO , IKEDA YOSHIHIRO , YANAGIDA HIROSHI , TSUKAMOTO KEISUKE , OKAZAKI TSUTOMU
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To improve a yield of manufacturing steps of a flash memory by increasing a process margin in a SAC technique.
SOLUTION: A method for manufacturing a semiconductor integrated circuit device comprises steps of coating an overhanging shape of a silicon nitride film 7 on a two-layer gate of a laminated structure having a conductor film 2 for a floating gate formed on a main surface of a semiconductor substrate 1 and a conductor film 3 for a control gate, and subsequently depositing an insulating film 8 made of a silicon oxide on the substrate 1. The method further comprises steps of perforating a contact hole CONT in the insulating film 8 with the silicon nitride film 7 as an etching stopper layer, then removing the exposed silicon nitride film 7, and then exposing an n-type semiconductor region D for forming a drain.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：通过增加SAC技术中的处理余量来提高闪存的制造步骤的产量。解决方案：一种用于制造半导体集成电路器件的方法包括以下步骤：将氮化硅膜7的悬垂形状涂覆在层压结构的双层栅极上，该叠层结构具有形成在主表面上的浮栅的导体膜2 半导体衬底1和用于控制栅极的导体膜3，随后在衬底1上沉积由氧化硅制成的绝缘膜8.该方法还包括以下步骤：在绝缘膜8中用氮化硅膜7作为蚀刻停止层，然后除去暴露的氮化硅膜7，然后露出用于形成漏极的n型半导体区域D.

4. 发明专利

JP2000332114A MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JP2000332114A
公开(公告)日：2000-11-30
申请号：JP13519699
申请日：1999-05-17
申请人： HITACHI LTD
发明人： TSUCHIYA OSAMU , IKEDA YOSHIHIRO , OKAZAKI TSUTOMU
IPC分类号： H01L21/82
摘要： PROBLEM TO BE SOLVED: To reduce the number of steps in forming a semiconductor integrated circuit device by forming a photosensitive resin layer on a passivation film, exposing and developing the resin layer to form a resin pattern, removing the passivation film on a fuse to form an opening. SOLUTION: A passivation film 74 is deposited on a third layer at the uppermost interconnections 70 to 72, and a photosensitive polyimide resin is applied on the film 74. Then, the photosensitive polyimide resin is exposed using a photoresist film provided with a predetermined pattern, and then developed, thereby laminating a resin layer 75, which has a resin pattern formed on the film 74. Etching is effected using the resin pattern of the layer 75 as a mask to remove the film 74 on a fuse FS, whereby an opening 76 is formed in a fuse forming region.

5. 发明专利

JP2000236074A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JP2000236074A
公开(公告)日：2000-08-29
申请号：JP30911499
申请日：1999-10-29
申请人： HITACHI LTD
发明人： OYU SHIZUNORI , OGISHIMA JUNJI , TSUCHIYA OSAMU , TADAKI YOSHITAKA , WATABE KOZO , UCHIYAMA HIROYUKI , IKEDA YOSHIHIRO , OKAZAKI TSUTOMU , ASAKURA HISAO , KAWAKITA KEIZO , SHIGENIWA MASAHIRO , KUBOTA KATSUHIKO , KUJIRAI YUTAKA , KAJITANI KAZUHIKO , NAGASHIMA YASUSHI , NAKAMURA MASAYUKI
IPC分类号： H01L27/108 , H01L21/8242
摘要： PROBLEM TO BE SOLVED: To provide a highly reliable DRAM by obtaining a desired threshold voltage in a memory cell and at the same time improving refresh characteristics. SOLUTION: A threshold voltage of 1.1 V of a memory cell selecting MISFET (Qs) is obtained by forming a p-type semiconductor region 27 and n--type semiconductor regions 8a, 8b whose impurity concentration is relatively high in a p-type well 4 on a data line side of the memory cell selecting MISFET (Qs). Junction field strength near the end part at an information storing capacity element side of a gate electrode 7a is reduced, by not forming the p-type semiconductor region 27 in the p-type well 4 at an information storing capacity element side but by forming the n--type semiconductor region 8b whose impurity concentration is relatively low.

6. 发明专利

JPH11135652A SEMICONDUCTOR INTEGRATED CIRCUIT AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH11135652A
公开(公告)日：1999-05-21
申请号：JP29654097
申请日：1997-10-29
申请人： HITACHI LTD
发明人： IKEDA YOSHIHIRO , OKAZAKI TSUTOMU , OWADA FUKUO , TSUCHIYA OSAMU
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To secure insulation between a floating gate electrode and a semiconductor substrate in a semiconductor integrated circuit device which has a nonvolatile memory. SOLUTION: After patterning a lower floating gate electrode 5fg1, a semiconductor substrate 1 is oxidation-treated. Through this method, a thin insulating film 10 is formed on a side face section of the lower floating gate electrode 5fg1 so as to make up for a scraped-off part of a tunnel insulating film 5Ti under the edge of the lower floating gate electrode 5fg1 and thereby a thin insulating film 11a, which is part of a sidewall 11 and constituted of a silicon nitride film, is prevented form coming under the edge of the lower floating gate electrode 5fg1.

7. 发明专利

JPH11111865A SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH11111865A
公开(公告)日：1999-04-23
申请号：JP26548597
申请日：1997-09-30
申请人： HITACHI LTD
发明人： ASAKA KATSUYUKI , OKAZAKI TSUTOMU , IKEDA YOSHIHIRO , TAKAKURA TOSHIHIKO , OKADA DAISUKE , OSHIMA KAZUYOSHI
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To enlarge the area of overlapped portions of a floating gate and control gate by providing side walls projecting from a floating gate lower layer film so as to cover the side face of this film and forming an upper layer film bent by the side walls. SOLUTION: The manufacturing method comprises forming a floating gate lower layer film 8 on a main surface of a semiconductor substrate 1 through a gate insulation film 7, self-aligningly forming source regions and drain regions 4 on the lower layer film 8, forming a floating gate upper layer film 11 extending along the lower layer film 8 on the source and drain regions 4 through an insulation film 10 adjacent to the film 11, and forming side walls 9 projecting from the side face of the lower layer film 8 to bend the upper layer film 11 at the projecting portions.

8. 发明专利

JPH09320982A MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURING DEVICE THEREOF 失效
公开(公告)号：JPH09320982A
公开(公告)日：1997-12-12
申请号：JP13604696
申请日：1996-05-30
申请人： HITACHI LTD , TEXAS INSTRUMENTS JAPAN
发明人： IKEDA YOSHIHIRO , SAKAI SATORU , OGASAWARA MAKOTO , SATO KAZUO , KAERIYAMA TOSHIYUKI , MATSUNAGA KATSUTOSHI , MATSUI TAKESHI
IPC分类号： H01L21/28 , H01L21/3205 , H01L23/52 , H01L29/43 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a technique which improves reliability of an MISFET comprising a gate electrode of a tungsten polycide film. SOLUTION: An n-type impurity for forming an n-type semiconductor region 7 is doped into a semiconductor substrate 1 with a gate electrode 6, comprising a WSix (tungsten polycide) film 5 and a polycrystalline silicon film 4, as a mask. Next, the semiconductor substrate 1 is cleaned using liquid which does not etch silicon oxide or silicon oxidizable liquid, and immediately after the exposed surface of the WSix film 5 is covered with a thin natural oxide film 8, heat processing at a temperature of 900 deg.C is performed on the semiconductor substrate 1 for activating the n-type impurity. This processing causes composition change in the WSix film 5, however, as the extraction of W or WSi is suppressed by the natural oxide film 8, short circuit between adjacent gate electrodes can be prevented.

9. 发明专利

JPH08250682A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH08250682A
公开(公告)日：1996-09-27
申请号：JP6407596
申请日：1996-03-21
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SUGIURA JUN , TSUCHIYA OSAMU , OGASAWARA MAKOTO , OTSUKA FUMIO , TORII KAZUNARI , ASANO ISAMU , OWADA NOBUO , HORIUCHI MITSUAKI , TAMARU TAKESHI , AOKI HIDEO , OTSUKA NOBUHIRO , SHIRAI SEIICHIRO , SAGAWA MASAKAZU , IKEDA YOSHIHIRO , KAGA TORU , TSUNEOKA MASATOSHI , NIINA TOMOJI , OGISHI HIDEJI , KASAHARA OSAMU , ENAMI HIROMITSU , WAKAHARA ATSUSHI , AKIMORI HIROYUKI , SUZUKI SHINICHI , FUNATSU YOSHIAKI , KAWASAKI YOSHINAO , TSUBONE TSUNEHIKO , KOGANO MASAYOSHI , TSUGANE MASARU
IPC分类号： H01L21/3205 , H01L21/768 , H01L21/8242 , H01L23/52 , H01L23/522 , H01L27/108
摘要： PURPOSE: To reduce resistance of an interface between a transition metal film buried in a connection hole and an aluminum alloy wiring and hence reduce a disconnection failure of a wiring by providing a barrier layer between the transition metal film and the aluminum alloy wiring. CONSTITUTION: A semiconductor integrated circuit device includes a first wiring 52 formed on a semiconductor substrate 20, and an interlayer insulating film 53 having an opening (connection hole) through which part of the first wiring 52 is exposed and formed on the first wiring 52. It further includes a transition metal film 54 formed over the connection hole 53D in the interlayer insulating film 53 and an aluminum alloy wiring 55B containing an additive Si formed on the transition metal film 54 and the interlayer insulating film 53. Particularly, a barrier layer (transition metal silicide film) 55A is provided between the transition metal film 54 and the aluminum alloy wiring 55B. Hereby, the transition metal silicide film 55A can connect, even if the aluminum alloy wiring 55B is cut down owing to a migration phenomenon for example, the aluminum alloy wirings 55B putting the cut part therebetween, and can hence reduce a disconnection failure of a wiring.

10. 发明专利

JP2001148189A DATA WRITE-IN METHOD 失效
公开(公告)号：JP2001148189A
公开(公告)日：2001-05-29
申请号：JP32928299
申请日：1999-11-19
申请人： HITACHI LTD
发明人： IKEDA YOSHIHIRO , TSUCHIYA OSAMU
IPC分类号： G11C11/14 , G11C11/15 , H01L21/8246 , H01L27/105 , H01L43/08
摘要： PROBLEM TO BE SOLVED: To improve largely write-in speed of data for a memory cell consisting of magnetroresisters. SOLUTION: When data of '001' is written in memory cells S1-S3 on the same word line WLn, a current is made to flow from one side of a word line WLn and bit lines BLn-1 to BLn+1 to the other side, and '0' is written in M cells S1-S3. After that, a current is made to flow from the other side to one side of the word line WLn, and '1' is written in only the memory cell S3 by flowing a current from the other side to one side in only the bit line BLn+1, to which the memory cell S3 in which '1' is desired to write is connected. Thereby, data can be written in a memory cell by write-in operation of two times, and write-in speed of a memory can be substantially improved.

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