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1. 发明专利

JPH08250682A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH08250682A
公开(公告)日：1996-09-27
申请号：JP6407596
申请日：1996-03-21
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SUGIURA JUN , TSUCHIYA OSAMU , OGASAWARA MAKOTO , OTSUKA FUMIO , TORII KAZUNARI , ASANO ISAMU , OWADA NOBUO , HORIUCHI MITSUAKI , TAMARU TAKESHI , AOKI HIDEO , OTSUKA NOBUHIRO , SHIRAI SEIICHIRO , SAGAWA MASAKAZU , IKEDA YOSHIHIRO , KAGA TORU , TSUNEOKA MASATOSHI , NIINA TOMOJI , OGISHI HIDEJI , KASAHARA OSAMU , ENAMI HIROMITSU , WAKAHARA ATSUSHI , AKIMORI HIROYUKI , SUZUKI SHINICHI , FUNATSU YOSHIAKI , KAWASAKI YOSHINAO , TSUBONE TSUNEHIKO , KOGANO MASAYOSHI , TSUGANE MASARU
IPC分类号： H01L21/3205 , H01L21/768 , H01L21/8242 , H01L23/52 , H01L23/522 , H01L27/108
摘要： PURPOSE: To reduce resistance of an interface between a transition metal film buried in a connection hole and an aluminum alloy wiring and hence reduce a disconnection failure of a wiring by providing a barrier layer between the transition metal film and the aluminum alloy wiring. CONSTITUTION: A semiconductor integrated circuit device includes a first wiring 52 formed on a semiconductor substrate 20, and an interlayer insulating film 53 having an opening (connection hole) through which part of the first wiring 52 is exposed and formed on the first wiring 52. It further includes a transition metal film 54 formed over the connection hole 53D in the interlayer insulating film 53 and an aluminum alloy wiring 55B containing an additive Si formed on the transition metal film 54 and the interlayer insulating film 53. Particularly, a barrier layer (transition metal silicide film) 55A is provided between the transition metal film 54 and the aluminum alloy wiring 55B. Hereby, the transition metal silicide film 55A can connect, even if the aluminum alloy wiring 55B is cut down owing to a migration phenomenon for example, the aluminum alloy wirings 55B putting the cut part therebetween, and can hence reduce a disconnection failure of a wiring.

2. 发明专利

JPH08241968A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH08241968A
公开(公告)日：1996-09-17
申请号：JP6404596
申请日：1996-03-21
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SUGIURA JUN , TSUCHIYA OSAMU , OGASAWARA MAKOTO , OTSUKA FUMIO , TORII KAZUNARI , ASANO ISAMU , OWADA NOBUO , HORIUCHI MITSUAKI , TAMARU TAKESHI , AOKI HIDEO , OTSUKA NOBUHIRO , SHIRAI SEIICHIRO , SAGAWA MASAKAZU , IKEDA YOSHIHIRO , KAGA TORU , TSUNEOKA MASATOSHI , NIINA TOMOJI , OGISHI HIDEJI , KASAHARA OSAMU , ENAMI HIROMITSU , WAKAHARA ATSUSHI , AKIMORI HIROYUKI , SUZUKI SHINICHI , FUNATSU YOSHIAKI , KAWASAKI YOSHINAO , TSUBONE TSUNEHIKO , KOGANO MASAYOSHI , TSUGANE MASARU
IPC分类号： H01L21/76 , H01L21/8242 , H01L27/08 , H01L27/108 , H01L29/78
摘要： PURPOSE: To obtain a semiconductor integrated circuit device which enhances the junction breakdown strength of a substrate to an element and which reduces a leakage current amount at the junction part of the substrate to the element by a method wherein an active region is not arranged in the boundary region between a first channel stopper region and a second channel stopper region. CONSTITUTION: In a DRAM, a memory cell and an n-channel MISFET in a peripheral circuit are arranged respectively on main faces inside respective different active regions in a p-type well region which is prescribed by a p-type channel stopper region formed on the main face of an inactive region in the p-type well region. Here, a p-type channel stopper region 25A which surrounds the circumference of the memory cell and an n-channel stopper region 24 in the peripheral circuit are constituted independently in separate manufacturing processes. Then, an active region Act such as the memory cell, the n-channel MISFET or the like in the peripheral circuit are not arranged in the boundary region between the p-type channel stopper region 25A and the n-type channel region 24.

3. 发明专利

JPH0258376A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH0258376A
公开(公告)日：1990-02-27
申请号：JP20843188
申请日：1988-08-24
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： UDO SHINJI , TAKANO MITSUHIRO , WADA SHOJI , KOMATSU NOBUO , TSUCHIYA OSAMU
IPC分类号： H01L27/10 , H01L21/8242 , H01L27/105 , H01L27/108
摘要： PURPOSE:To prevent the breakdown of the dielectric film of a guard ring by applying voltage lower than power source voltage to the plate electrode of a memory cell, and also making the diffusion layer of the guard ring and the plate electrode the same potential. CONSTITUTION:A guard ring G is composed of a plate electrode 4a extending outward from a memory mat M, a dielectric film 9b consisting of SiO2 which is formed on the surface of a substrate 1 being its lower layer, and an n-type diffusion layer 8b being formed in its further lower layer. This guard ring G is formed to trap a small number of carriers which are implanted into the memory mat M from a peripheral circuit through the substrate 1, and it is so arranged as to surround the memory mat M over the whole area in the peripheral part. By making the plate electrode 4a of the guard ring G and the n-type diffusion layer 8b the same potential (1/2VCC) this way, even in the case that power source voltage higher than the ordinary power source voltage (VCC) is charged at the time of aging, etc., this high voltage is never applied to the dielectric film 9b, therefore the breakdown of the dielectric film 9b is prevented effectively, and the function of the guard ring G can be exhibited without obstacle.

4. 发明专利

JPH01145852A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH01145852A
公开(公告)日：1989-06-07
申请号：JP30319287
申请日：1987-12-02
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： TAKANO MITSUHIRO , UDO SHINJI , KOMATSU NOBUO , KASAMA YASUHIRO , TSUCHIYA OSAMU
IPC分类号： H01L27/10 , H01L21/76 , H01L21/8242 , H01L27/105 , H01L27/108
摘要： PURPOSE:To decrease soft errors, to form channel stopper regions at a boundary part and to improve breakdown strength in insulation and isolation at the boundary part, by increasing and optimizing the impurity concentration of a potential barrier layer in a memory cell array. CONSTITUTION:A channel stopper region 4A beneath a field insulating film 3, which specifies a region in a memory cell M in a DRAM, and a potential barrier layer 4B beneath the memory cell M are constituted in the same manufacturing step. At a boundary part between a memory cell array MA and a peripheral circuit region AL, the channel stopper region 4A or the potential barrier layer 4B and a channel stopper region 5 are overlapped by at least an amount equivalent to a deviated amount in mask alignment in the manufacturing process. Thus, the impurity concentration of the potential barrier layer 4A in the memory array MS can be increased and optimized. Therefore, soft errors can be decreased and the channel stopper regions 4A and 5 can be positively formed at the boundary part. In this way, the breakdown strength in insulation and isolation at the boundary part can be improved.

5. 发明专利

JPH08250681A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH08250681A
公开(公告)日：1996-09-27
申请号：JP6407496
申请日：1996-03-21
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SUGIURA JUN , TSUCHIYA OSAMU , OGASAWARA MAKOTO , OTSUKA FUMIO , TORII KAZUNARI , ASANO ISAMU , OWADA NOBUO , HORIUCHI MITSUAKI , TAMARU TAKESHI , AOKI HIDEO , OTSUKA NOBUHIRO , SHIRAI SEIICHIRO , SAGAWA MASAKAZU , IKEDA YOSHIHIRO , KAGA TORU , TSUNEOKA MASATOSHI , NIINA TOMOJI , OGISHI HIDEJI , KASAHARA OSAMU , ENAMI HIROMITSU , WAKAHARA ATSUSHI , AKIMORI HIROYUKI , SUZUKI SHINICHI , FUNATSU YOSHIAKI , KAWASAKI YOSHINAO , TSUBONE TSUNEHIKO , KOGANO MASAYOSHI , TSUGANE MASARU
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/108 , H01L29/78
摘要： PURPOSE: To flatten the surface of an interlayer insulating film by filling an interval between lower electrode layers with an interlayer insulating layer by making thicker the thickness of the interlayer insulating film than the specific amount of a distance between first electrodes of a memory cell where the first electrodes of the memory cell adjoin with a minimum interval. CONSTITUTION: This device comprises a plurality of word lines 27 that constitute a gate electrode 27 of a memory cell selecting MISFETQS, a first electrode 37 extending onto the word lines, and a second electrode 35 provided oppositely to the first electrode 37 through a dielectric 36. An interlayer insulating film 53 is provided between a second electrode 37 and a wiring 36. The first electrode 37 is independently of each memory cell M, and the second electrode 35 is formed commonly to a plurality of the memory cells. The interlayer insulating film 53 is constructed to be thicker than 1/2 of a distance between the first electrodes 37 where the first electrodes of the memory cell M adjoin with a minimum interval. Hereby, an interval between the lower layer electrode layers 35 is filled with the interlayer insulating film 53 to flatten the surface of the interlayer insulating film 53.

6. 发明专利

JPH08250601A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH08250601A
公开(公告)日：1996-09-27
申请号：JP6404696
申请日：1996-03-21
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SUGIURA JUN , TSUCHIYA OSAMU , OGASAWARA MAKOTO , OTSUKA FUMIO , TORII KAZUNARI , ASANO ISAMU , OWADA NOBUO , HORIUCHI MITSUAKI , TAMARU TAKESHI , AOKI HIDEO , OTSUKA NOBUHIRO , SHIRAI SEIICHIRO , SAGAWA MASAKAZU , IKEDA YOSHIHIRO , KAGA TORU , TSUNEOKA MASATOSHI , NIINA TOMOJI , OGISHI HIDEJI , KASAHARA OSAMU , ENAMI HIROMITSU , WAKAHARA ATSUSHI , AKIMORI HIROYUKI , SUZUKI SHINICHI , FUNATSU YOSHIAKI , KAWASAKI YOSHINAO , TSUBONE TSUNEHIKO , KOGANO MASAYOSHI , TSUGANE MASARU
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/8242 , H01L27/088 , H01L27/108 , H01L29/78
摘要： PURPOSE: To improve hot carrier withstand voltage by making virtually equal the dimensions in the direction of gate length of the semiconductor regions of low impurity concentration, which form the LDD structure of a first and a second MISFETs, respectively. CONSTITUTION: The n-channel MISFETs Qn of an input/output stage circuit and an internal circuit are composed of a gate insulating film 26, a gate electrode 27, a n-type semiconductor region 29, and a n--type semiconductor region 32, respectively. The side wall spacers 31 of these n-channel MISFETs Qn are virtually the same in size in the direction of gate length. The gate length of the n-channel MISFET Qn in the input/output stage circuit is made larger than that of the n-channel MISFET Qn in the internal circuit. Further, the n-type semiconductor regions 29 forming the LDD structure of the n-channel MISFETs are virtually the same in size in the direction of gate length. This improves hot carrier withstand voltage, and reduces threshold voltage drop with a lapse of time, which enables the improvement of electrical characteristics.

7. 发明专利

JPH08241969A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH08241969A
公开(公告)日：1996-09-17
申请号：JP6407696
申请日：1996-03-21
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SUGIURA JUN , TSUCHIYA OSAMU , OGASAWARA MAKOTO , OTSUKA FUMIO , TORII KAZUNARI , ASANO ISAMU , OWADA NOBUO , HORIUCHI MITSUAKI , TAMARU TAKESHI , AOKI HIDEO , OTSUKA NOBUHIRO , SHIRAI SEIICHIRO , SAGAWA MASAKAZU , IKEDA YOSHIHIRO , KAGA TORU , TSUNEOKA MASATOSHI , NIINA TOMOJI , OGISHI HIDEJI , KASAHARA OSAMU , ENAMI HIROMITSU , WAKAHARA ATSUSHI , AKIMORI HIROYUKI , SUZUKI SHINICHI , FUNATSU YOSHIAKI , KAWASAKI YOSHINAO , TSUBONE TSUNEHIKO , KOGANO MASAYOSHI , TSUGANE MASARU
IPC分类号： H01L21/768 , H01L21/3205 , H01L21/8242 , H01L23/522 , H01L27/108 , H01L29/78
摘要： PURPOSE: To obtain a semiconductor integrated circuit device which enhances the moisture-proof of a passivation film formed on an interconnection layer by a method wherein the film thickness of an insulating film formed on an aluminum interconnection is specified by using a CVD method in which tetraethoxysilane is used as a source gas. CONSTITUTION: A passivation film 56 is formed on interconnections 55 which are composed mainly of aluminum alloy films 55B. The passivation film 56 is constituted of a composite film in which each of a silicon oxide film 56A deposited by a C-CVD method by using tetraethoxysilane as a source gas and a silicon nitride film 56B deposited by a plasma CVD method have been laminated in order. The silicon oxide film 56A at the lower layer of the passivation film 56 is constituted at a film thickness at 1/2 or higher of the interval between the interconnections 55 in regions in which the aspect ratio of the interval between the interconnections 55 to the film thickness of the interconnections 55 is at 1 or higher. By this constitution, the silicon oxide film 56A can be deposited at high step coverage at a low temperature at which the aluminum alloy films 55B for the interconnections 55 are not melted.

8. 发明专利

JPH0316153A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURE THEREOF AND APPARATUS FOR PRODUCTION THEREOF 失效
公开(公告)号：JPH0316153A
公开(公告)日：1991-01-24
申请号：JP6584989
申请日：1989-03-20
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SUGIURA JUN , TSUCHIYA OSAMU , OGASAWARA MAKOTO , OTSUKA FUMIO , TORII KAZUNARI , ASANO ISAMU , OWADA NOBUO , HORIUCHI MITSUAKI , TAMARU TAKESHI , AOKI HIDEO , OTSUKA NOBUHIRO , SHIRAI SEIICHIRO , SAGAWA MASAKAZU , IKEDA YOSHIHIRO , KAGA TORU , TSUNEOKA MASATOSHI , NIINA TOMOJI , OGISHI HIDEJI , KASAHARA OSAMU , ENAMI HIROMITSU , WAKAHARA ATSUSHI , AKIMORI HIROYUKI , SUZUKI SHINICHI , FUNATSU YOSHIAKI , KAWASAKI YOSHINAO , TSUBONE TSUNEHIKO , KOGANO MASAYOSHI , TSUGANE MASARU
IPC分类号： G03F7/20 , G03F9/00 , H01L21/02 , H01L21/285 , H01L21/336 , H01L21/76 , H01L21/768 , H01L21/8238 , H01L21/8242 , H01L23/29 , H01L23/495 , H01L23/525 , H01L23/532 , H01L23/544 , H01L27/092 , H01L27/10 , H01L27/108 , H01L29/78
摘要： PURPOSE:To enhance an integration density by a method wherein a channel stopper region is formed in a main-face part under an insulating film for interelement isolation use of a substrate. CONSTITUTION:An oxidation-resistant mask whose film thickness is thin as compared with an oxidation-resistant mask of a first mask and an etching mask are laminated one after another; thereby, a second mask is formed. An etching treatment of a main face in an inert region of a substrate is executed by using the first and second masks; a groove is formed in the inert region of the substrate. Then, an oxidation treatment is executed by using the first and second masks; an insulating film for interelement isolation use (field insulating film) is formed on the main face of the inert region of the substrate. Then, the first and second masks are removed; after that, impurities are introduced into the whole main-face part including an active region and the inert region of the substrate; a channel stopper region is formed on the main-face part under the insulating film for interelement isolation use of the substrate. Thereby, an integration density can be enhanced.

9. 发明专利

JPH02144963A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH02144963A
公开(公告)日：1990-06-04
申请号：JP29812288
申请日：1988-11-28
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： TSUCHIYA OSAMU , KASAMA YASUHIRO , OSHIMA KAZUYOSHI , TAKANO MITSUHIRO , KOMATSU NOBUO , UDO SHINJI , SUWAUCHI NAOKATSU
IPC分类号： H01L27/10 , H01L27/108
摘要： PURPOSE:To enhance a refresh characteristic by a method wherein a high-concentration n-type impurity is introduced into a polycrystalline silicon film, its polycrystalline property is destroyed, an amorphous silicon film is formed, this amorphous silicon film is heat-treated, a single-crystal silicon film is formed and an intermediate conductive film is formed. CONSTITUTION:An intermediate conductive layer 34 is formed at the upper part of an interlayer insulating film 30 in such a way that it is connected to a semiconductor region 31 through a connecting hole 33 formed at the upper part of the other semiconductor region 31 in a MISFET Qs formation region. Then, when a high-concentration n-type impurity is introduced into the polycrystalline silicon film 34, the n-type impurity is diffused to a grain boundary of the polycrystalline silicon film 34; a crystal is destroyed; the polycrystalline silicon film 34 is transformed into an amorphous silicon film 34. Then, the amorphous silicon film 34C is patterned; after that, a heat treatment is executed; then, a grain is formed inside the amorphous silicon film 34 from a part coming into contact with the semiconductor region 31; the intermediate conductive film 34 which has been made to be a single crystal is formed. By this heat-treatment process, the n-type impurity is diffused to the semiconductor region 31; a high-concentration n type semiconductor region 35 is formed. Thereby, it is possible to eliminate an inflection point of the grain boundary in the intermediate conductive film and to prevent a disconnection of a data line.

10. 发明专利

JPH01298738A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH01298738A
公开(公告)日：1989-12-01
申请号：JP12834688
申请日：1988-05-27
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： UDO SHINJI , TSUCHIYA OSAMU
IPC分类号： H01L21/82 , H01L27/10
摘要： PURPOSE:To eliminate defects without increasing manufacturing steps by providing a step of opening a second interlayer insulating film covering a metal layer, a step of forming an opening at the upper region of a fuse layer, a step of exposing the fuse layer, and a step of fusion-disconnecting the fuse layer to eliminate defects, thereby forming a semiconductor device. CONSTITUTION:When a metal film made of aluminum or the like covering the surface of a substrate 1 is patterned to form a second layer wiring 17, a fuse protective layer 9 and a metal layer 14 are simultaneously etched, and the opening of the upper region of a fuse layer 5 is accelerated. Since the surface of the layer 5 is protected y an insulating film 7, the layer 5 operates as an etching stopper for the layers 14 and 9. In this case, since the sidewall of the opening 19 formed at the upper region of the layer 5 is insulated by a passivation film 18, it can effectively prevent the layers 14, 9, 5 from short- circuiting.

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