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1. 发明专利

JP2006252648A Dynamic random access memory device and test method therefor 有权
标题翻译：动态随机存取存储器及其测试方法
公开(公告)号：JP2006252648A
公开(公告)日：2006-09-21
申请号：JP2005066657
申请日：2005-03-10
申请人： Elpida Memory Inc , Hitachi Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所
发明人： MORI TOMONORI , YAMADA RENICHI , TSUKADA SHUICHI , OYU SHIZUNORI
IPC分类号： G11C29/56 , G01R31/28 , G01R31/30 , G11C11/401 , G11C29/44
CPC分类号： G11C29/50 , G11C11/401 , G11C29/50016
摘要： PROBLEM TO BE SOLVED: To screen a so-called variable retention time (VRT) defect caused by the fact that a data retention time varies like random telegraph noise in DRAM. SOLUTION: A bit which may cause a retention defect of a data retention capability resulting from random changes with time is screened by repeating a pause refresh test for checking a data retention function in the whole chip surface and the whole bits by an optimized frequency. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了屏蔽由DRAM中的随机电报噪声等数据保持时间变化所引起的所谓可变保留时间（VRT）缺陷。解决方案：通过重复暂停刷新测试来检查可能导致随时间随机变化产生的数据保留能力的一个位，以便通过优化的整个芯片表面和整个比特来检查数据保留功能频率。版权所有（C）2006，JPO＆NCIPI

2. 发明专利

JP2006040991A Method of evaluating semiconductor device and manufacturing method thereof 审中-公开
标题翻译：评估半导体器件的方法及其制造方法
公开(公告)号：JP2006040991A
公开(公告)日：2006-02-09
申请号：JP2004215183
申请日：2004-07-23
申请人： Elpida Memory Inc , Hitachi Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所
发明人： TAKATO ATSUKO , NOZOE MARI , OYU SHIZUNORI
IPC分类号： H01L21/66 , H01L21/8238 , H01L21/8242 , H01L27/092 , H01L27/108
CPC分类号： H01L22/14 , G01R31/2653 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a technology which makes it possible to evaluate the leak characteristics distribution in a pn junction in the middle of manufacturing process of a semiconductor device having the pn junction, and to rapidly feed back the evaluation results to decision making of manufacturing process conditions. SOLUTION: For a wafer in the middle of manufacturing process, an electron beam is irradiated several times on the surface of the wafer whereon a plug is exposed at prescribed intervals under such a condition that the pn junction may be reverse-biased. Monitoring the charged potential of the surface of the plug, the electron beam irradiation conditions are changed to such ones that the charged potential may come within a desired range. Under such irradiation conditions, a secondary electron signal of a circuit pattern is obtained and the leak characteristics are evaluated. Since the charged potential in the pn junction is relaxed according to the size of the leakage current within intermittent time, the leak characteristics are evaluated from the brightness signal of a potential contrast image. Thus, by measuring the charged potential and making it within a desired range, the evaluation results reflect a state in actual operation and thereby the accuracy improves. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种能够在具有pn结的半导体器件的制造过程中评估pn结中的泄漏特性分布的技术，并且将评估结果快速反馈到制造工艺条件的决策。解决方案：对于在制造过程中间的晶片，在pn结可以被反向偏置的条件下，以规定的间隔将电子束照射在晶片的表面上，在该表面上暴露一个电极。监测插头表面的带电电位，将电子束照射条件改变为充电电位可能在期望范围内的条件。在这种照射条件下，获得电路图案的二次电子信号，并评价泄漏特性。由于根据间歇时间内的漏电流的大小使pn结中的充电电位松弛，所以根据潜在对比度图像的亮度信号来评价泄漏特性。因此，通过测量充电电位并使其在期望的范围内，评价结果反映实际操作中的状态，从而提高精度。版权所有（C）2006，JPO＆NCIPI

3. 发明专利

JP2003068878A Semiconductor integrated circuit device and method of manufacturing the same 审中-公开
标题翻译：半导体集成电路装置及其制造方法
公开(公告)号：JP2003068878A
公开(公告)日：2003-03-07
申请号：JP2001253028
申请日：2001-08-23
申请人： Hitachi Ltd , Nec Corp , 日本電気株式会社 , 株式会社日立製作所
发明人： KUJIRAI YUTAKA , OKUYAMA KOSUKE , HATA KAZUHIRO , OYU SHIZUNORI , NAGAI AKIRA , UCHIYAMA HIROYUKI , KUMOCHI TAKAHIRO , ICHINOSE TERUYUKI
IPC分类号： H01L21/768 , H01L21/28 , H01L21/60 , H01L21/8242 , H01L27/092 , H01L27/108 , H01L29/49 , H01L29/78
CPC分类号： H01L29/4983 , H01L21/28061 , H01L21/28247 , H01L21/76897 , H01L27/10811 , H01L27/10814 , H01L27/10873 , H01L29/4941
摘要： PROBLEM TO BE SOLVED: To reduce a leak current by reducing contamination of metal forming the polymetal gate of a MISFET.
SOLUTION: A cap insulation film 10a, a W film 9c and a WN film 9b among polycrystal silicon film 9a, WN film 9b, W film 9c and gap insulation film 10a deposited on a gate insulation film 8 on a p-type well 3 (semiconductor substrate) are etched, the polycrystal silicon film 9a as the under layer is over- etched, side wall films SW are formed to the side walls of these films, and the polycrystal silicon film 9a is etched using the side wall film SW as the mask. Thereafter, a light oxide film 11a is formed to the side wall of the polycrystal silicon film 9a by conducting heat treatment in the oxidation atmosphere. As a result, contamination on the gate insulation film 8 by tungsten W and its oxide can be reduced and these substances are diffused into the semiconductor substrate (p type well 3) to prevent increase of a leak current.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：通过减少形成MISFET的多金属栅极的金属的污染来减少泄漏电流。解决方案：在多晶硅膜9a中的帽绝缘膜10a，W膜9c和WN膜9b，沉积在p型阱3上的栅绝缘膜8上的WN膜9b，W膜9c和间隙绝缘膜10a（半导体衬底）被蚀刻，作为下层的多晶硅膜9a被过度蚀刻，侧壁膜SW形成在这些膜的侧壁上，并且使用侧壁膜SW蚀刻多晶硅膜9a作为面具。此后，通过在氧化气氛中进行热处理，在多晶硅膜9a的侧壁上形成光氧化膜11a。结果，可以减少钨W及其氧化物对栅极绝缘膜8的污染，并且这些物质扩散到半导体衬底（p型阱3）中以防止泄漏电流的增加。

4. 发明专利

JP2001332706A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JP2001332706A
公开(公告)日：2001-11-30
申请号：JP2000147157
申请日：2000-05-19
申请人： HITACHI LTD
发明人： OYU SHIZUNORI , KUMOCHI TAKAHIRO
IPC分类号： H01L21/76 , H01L21/8238 , H01L21/8242 , H01L27/08 , H01L27/092 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device having pair transistors wherein influence of SGI stress is reduced. SOLUTION: A first and a second MOSFETs which are operated in a differential mode are aligned in a first direction. A plurality of pairs of the first and the second MOSFETs are arranged in a second direction perpendicular to the first direction. Dummy element forming regions are stretched in the second direction so as to reduce the difference between a stress directed from a first SGI to a first element forming region of the first MOSFET and a stress directed from a second SGI to a second element forming region of the second MOSFET. Further, the regions are arranged on the first SGI arranged between the first MOSFET and the adjacent first element forming region and on the second SGI arranged between the second MOSFET and the adjacent second element forming region. The dummy element forming regions are made to have a role as a stress interference preventing pattern.

5. 发明专利

JP2001203337A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURING METHOD THEREOF 失效
公开(公告)号：JP2001203337A
公开(公告)日：2001-07-27
申请号：JP2000013476
申请日：2000-01-21
申请人： HITACHI LTD
发明人： YAMADA SATORU , OYU SHIZUNORI , TOKUNAGA TAKAFUMI , ENOMOTO HIROYUKI , SEKIGUCHI TOSHIHIRO
IPC分类号： H01L21/02 , H01L21/768 , H01L21/8234 , H01L21/8242 , H01L27/088 , H01L27/108 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To reduce the bit line capacity of a DRAM reduced in memory size. SOLUTION: A sidewall insulating film of a gate electrode 7 (word line WL) is composed of a sidewall insulating film 10 made of silicon nitride and a sidewall insulating film 11 made of silicon oxide having a smaller relative permittivity. The capacity of a bit line formed on the gate electrode 7 (word line WL) with respect to the word line is reduced. Further, the upper end of the side wall insulating film 11 made of silicon oxide is set lower than the upper surface of a cap insulating film 9. Thus, an upper diameter of a plug 14, which is placed into a space (contact holes 12 and 13) of the gate electrode 7 (word line WL), is set larger than a diameter of the bottom to obtain a contact area between the contact hole 13 and a through hole formed thereon.

6. 发明专利

JP2000174225A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JP2000174225A
公开(公告)日：2000-06-23
申请号：JP34159998
申请日：1998-12-01
申请人： HITACHI LTD
发明人： OGISHIMA JUNJI , OYU SHIZUNORI
IPC分类号： H01L21/8234 , H01L21/02 , H01L21/768 , H01L21/8242 , H01L27/088 , H01L27/10 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To improve the refresh characteristic by making the conductivity type of polysilicon opposite to that of the semiconductor region of source and drain of a MIS transistor and forming a device isolation region which defines an active region by embedding an insulating film in an isolation trench. SOLUTION: A device isolation region 4 of an embedded shallow-trench type is formed in an upper layer part of a semiconductor substrate 1. With this device isolation region 4 of the embedded type, the impurity concentration of a p-n junction at the interface between the impurity-doped region for an accumulation node of a MOS.FET for memory cell selection and the device isolation region 4 becomes low, and the electric field near the junction of a semiconductor region 5a connecting to a capacitor C is relaxed. Therefore, the leakage current between the accumulation node and the semiconductor substrate 1 is reduced. By this decrease of the leakage current, the refresh characteristic of the memory cell can be improved.

7. 发明专利

JPH1186554A DYNAMIC RAM 失效
公开(公告)号：JPH1186554A
公开(公告)日：1999-03-30
申请号：JP25138597
申请日：1997-09-01
申请人： HITACHI LTD
发明人： OYU SHIZUNORI , NAKAGOME YOSHINOBU
IPC分类号： G11C11/409 , G11C11/401 , G11C11/403 , G11C11/407 , H01L21/8242 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To prolong a memory cell information holding time by making the plate and precharge voltages of a complementary bit line pair to be leaning toward the intermediate potential side of high and low levels so that the voltages and the residual voltage, which is varied during the elapsed time corresponding to a specified refresh period while the high and the low levels are written into the accumulation nodes of a storage capacitor, become equal. SOLUTION: A plate voltage VPL is leaned toward a low level side rather than the intermediate of the high/low levels of bit lines BL so that a refresh period is made longer and a lower power consumption is realized during a battery backup. A subword line SWL selection level is set to a high voltage VPP which is set higher with respect to a high level internal voltage VDL of the lines BL for the amount equivalent to the threshold voltage of a an address selection MOSFET Qm. Thus, if the precharge voltage is set 1/2 of the voltage VDL, a holding potential becomes lower than the above voltage and the memory cell, which has a tendency to make a maloperation, maintains the potential difference in which a high level reading is conducted.

8. 发明专利

JPH10242284A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH10242284A
公开(公告)日：1998-09-11
申请号：JP4240797
申请日：1997-02-26
申请人： HITACHI LTD
发明人： OYU SHIZUNORI , HASEGAWA NORIO , KOBAYASHI NOBUYOSHI , KAWAMOTO YOSHIFUMI
IPC分类号： H01L21/3205 , H01L21/82 , H01L21/822 , H01L21/8242 , H01L23/52 , H01L27/04 , H01L27/10 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To easily form wirings between logic parts and memories by providing multilayer logic wiring groups, memory wiring groups, scribe region wiring and below-terminal wiring and interconnecting the wiring groups to connect the logic parts and memories. SOLUTION: Surface wirings 5, 15 of logic parts 1 and memories 2 are composed of wirings 5a, 15a constructing a first through sixth layers, conductive plugs 5b, 15b extending in a direction Z for connecting the upper and lower wirings 5a, 15a, and conductive plugs 5c, 15c for connecting the wirings 5a, 15a to semiconductor regions 45 on the surface layer of a semiconductor substrate 6 of the logic parts 1 and memories 2. Multilayer wiring structured wiring groups 3 are provided at the periphery and surface and formed on the surface of the substrate 6 having no element such as transistor and hence the no. of layers of the wirings on the parts 1 and memories 2 is equal to that of the multilayer wirings between the parts, it is planarized to facilitate the wiring work.

9. 发明专利

JPH0982807A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH0982807A
公开(公告)日：1997-03-28
申请号：JP24130095
申请日：1995-09-20
申请人： HITACHI LTD
发明人： OYU SHIZUNORI , OKURA OSAMU , KAWAMOTO YOSHIFUMI
IPC分类号： H01L27/088 , H01L21/8234
摘要： PROBLEM TO BE SOLVED: To suppress the movement of a parasitic bipolar, to restrain a junction leak current, and to suppress the deterioration of reliability of an insulating film by a method wherein a heavily doped well layer of carrier density distribution having the highest concentration is formed deeper than the well layer on the surface side of a semiconductor substrate, with crystal defects included in the well layer. SOLUTION: A plurality of well layers 2a, 2b, 3a, 3b, 4a and 4b are formed on the main surface side of a semiconductor substrate 1. Heavily doped well layers 2b, 3b and 4b, having the carrier density distribution of highest concentrations 5, 6 and 7, are formed deeper than the well layers 2a, 3a and 4a on the surface side of the semiconductor substrate. A layer, having a crystal defect 8, is formed at least in a kind of well layer. As a result, the diffusion into the well layer of minority carrier from the side of the substrate 1 can be prevented, and the leak current of source/drain junction can be decreased. Also, a parasitic bipolar action and a soft error can be suppressed.

10. 发明专利

JPH08213379A THIN FILM STACK FORMING METHOD AND THIN FILM FORMING EQUIPMENT 失效
公开(公告)号：JPH08213379A
公开(公告)日：1996-08-20
申请号：JP28014595
申请日：1995-10-27
申请人： HITACHI LTD
发明人： OYU SHIZUNORI , KASHU NOBUYOSHI , IIJIMA SHINPEI , WADA YASUO
IPC分类号： H01L21/205 , H01L21/31 , H01L21/316 , H01L21/318
摘要： PURPOSE: To easily form thin film excellent in characteristics with high controllability, and prevent strain and damage to a reaction vessel, by making the degree of vacuum in a lamp house equal to that of the inside of a thermal reaction vessel, forming a first film by setting a specimen in a first atmosphere at a first temperature, and treating the specimen by second order in a second atmosphere at a second temperature. CONSTITUTION: A vacuum exhaust control part 19 is installed in order to make the degree of vacuum in a reaction vessel 9 equal to that of the inside of a lamp house 15. The temperature of a specimen 8 is monitored by using a pyrometer 20, and kept at a specific value by controlling the input of a lamp 13. A gas control part 34 can assign a plurality of gas seeds whose flow rate is controlled to 100 reaction gas introducing cylinders 11 installed in the reaction vessel 9, in order that a uniform thin film may be formed on the specimen 8 surface. In the reaction vessel 9, a film is formed in a first atmosphere at a controlled first temperature, and then the specimen treatment is performed in a second atmosphere by controlling the temperature to be a second temperature in second order.

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