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1. 发明专利

JP2010245494A Self-assembled monolayer film forming method, and copper wiring for use in semiconductor device and method of making the same 审中-公开
标题翻译：自组装单层膜形成方法和用于半导体器件的铜线及其制造方法
公开(公告)号：JP2010245494A
公开(公告)日：2010-10-28
申请号：JP2009154385
申请日：2009-06-29
申请人： Hanyang Univ Industry-Univ Cooperation Foundation , Hynix Semiconductor Inc , 株式会社ハイニックスセミコンダクターHynix Semiconductor Inc. , 漢陽大学校産学協力団
发明人： YEOM SEUNG-JIN , KIM JAE HONG , KANG SUNG GOON , HAN WON KYU
IPC分类号： H01L21/288 , C23C18/18 , C23C18/38 , C25D7/12 , H01L21/3205 , H01L23/52
CPC分类号： H01L23/53238 , H01L21/288 , H01L21/76861 , H01L21/76873 , H01L21/76874 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a self-assembled monolayer film forming method that prevents the occurrence of voids or seams from being created, and to provide copper wiring for use in a semiconductor device and a method of making the same. SOLUTION: The method of forming the copper wiring of the semiconductor device includes the steps of forming an interlayer dielectric film on a semiconductor substrate having a metal line forming region; forming a self-assembled monolayer film on the interlayer dielectric film including a metal line forming region surface; adsorbing catalytic particles on a surface of the self-assembled monolayer; forming using an electroless plating process a copper seed layer on the self-assembled monolayer having the catalytic particles adsorbed thereto; and forming a copper film on the copper seed layer to fill in the metal line forming region. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种防止产生空隙或接缝的自组装单层膜形成方法，以及提供用于半导体器件的铜布线及其制造方法。解决方案：形成半导体器件的铜布线的方法包括在具有金属线形成区域的半导体衬底上形成层间绝缘膜的步骤; 在包括金属线形成区域表面的层间电介质膜上形成自组装单层膜; 将催化颗粒吸附在自组装单层的表面上; 使用化学镀方法在其上吸附催化剂颗粒的自组装单层上形成铜籽晶层; 并在铜籽晶层上形成铜膜以填充金属线形成区域。版权所有（C）2011，JPO＆INPIT

2. 发明专利

JP2007073926A Dielectric film and its forming method, and semiconductor memory device equipped with dielectric film and its manufacturing method 审中-公开
标题翻译：电介质膜及其成型方法，以及配备电介质膜的半导体存储器件及其制造方法
公开(公告)号：JP2007073926A
公开(公告)日：2007-03-22
申请号：JP2006129808
申请日：2006-05-09
申请人： Hynix Semiconductor Inc , 株式会社ハイニックスセミコンダクターHynix Semiconductor Inc.
发明人： KIL DEOK-SIN , KO KEN , YEOM SEUNG-JIN
IPC分类号： H01L21/8242 , H01L21/316 , H01L21/8247 , H01L27/108 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L29/7881 , H01L21/28273 , H01L29/513
摘要： PROBLEM TO BE SOLVED: To provide a dielectric film and its forming method, and a semiconductor memory device and its manufacturing method, which keep electrostatic capacity and improve leakage current property.
SOLUTION: A dielectric film (50) comprises: a first dielectric film (10) having at least 25 of specific inductive capacity; a second dielectric film (20) formed on the first dielectric film (10) using a substance lower in a modulus of crystallization than that of the first dielectric film (10); and a third dielectric film (30) formed on the second dielectric film (20) using the same substance as that of the first dielectric film (10). The semiconductor memory device comprises: a substrate in which a lower electrode is formed; the dielectric film (50) formed on the lower electrode; and an upper electrode formed on the dielectric film (50).
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种电介质膜及其形成方法以及保持静电容量并提高漏电流性能的半导体存储器件及其制造方法。电介质膜（50）包括：具有至少25的电感率的第一介电膜（10）使用比第一电介质膜（10）的结晶度低的物质形成在第一电介质膜（10）上的第二电介质膜（20）。以及使用与第一电介质膜（10）相同的物质在第二电介质膜（20）上形成的第三电介质膜（30）。半导体存储器件包括：形成下电极的衬底; 形成在下电极上的电介质膜（50）和形成在电介质膜（50）上的上电极。版权所有（C）2007，JPO＆INPIT

3. 发明专利

JP2007013086A Nano-mixed dielectric film, capacitor having the same, and its manufacturing method 审中-公开
标题翻译：纳米混合电介质膜，其电容器及其制造方法
公开(公告)号：JP2007013086A
公开(公告)日：2007-01-18
申请号：JP2006000060
申请日：2006-01-04
申请人： Hynix Semiconductor Inc , 株式会社ハイニックスセミコンダクターHynix Semiconductor Inc.
发明人： KIL DEOK-SIN , KO KEN , YEOM SEUNG-JIN
IPC分类号： H01L21/8242 , C23C16/40 , H01L21/316 , H01L27/108
CPC分类号： H01G4/1218 , H01G4/12 , H01G4/1236 , H01G4/206 , H01L28/40 , Y10S977/70 , Y10S977/902
摘要： PROBLEM TO BE SOLVED: To provide a nano-mixed dielectric film that has EOT of 10 Å or less and is excellent in leakage current characteristics, a capacitor have the same, and its manufacturing method.
SOLUTION: The dielectric film of the capacitor is provided with the nano-mixed dielectric film where ZrO
2 and TiO
2 are nano-mixed in a nano-mixed state. The capacitor is provided with a lower electrode, the nano-mixed dielectric film formed by allowing ZrO
2 and TiO
2 to be mixed in a nano-mixed state on the lower electrode, and an upper electrode on the nano-mixed dielectric film. The method for manufacturing the dielectric film of the capacitor includes a step for forming the nano-mixed dielectric film where ZrO
2 and TiO
2 are nano-mixed in a nano-mixed state, by repeating a ZrO
2 deposition cycle and a TiO
2 deposition cycle m times and n times, respectively, using Atomic Layer Deposition; and a step for densifying the nano-mixed dielectric film.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了提供具有10埃以下的EOT和漏电流特性优异的纳米混合电介质膜，电容器具有相同的制造方法。解决方案：电容器的电介质膜设置有纳米混合电介质膜，其中ZrO 2 SBB和TiO 2 SBB在纳米混合状态下纳米混合。电容器设有下电极，将纳米混合电介质膜以纳米混合状态混合在下电极上形成，该纳米混合电介质膜通过使ZrO 2 SB 2和/ 和纳米混合电介质膜上的上电极。用于制造电容器的电介质膜的方法包括在纳米混合物中纳米混合形成纳米混合电介质膜的步骤，其中ZrO 2 SB 2和/ 状态，通过使用原子层沉积分别重复ZrO 2 SBS沉积循环和TiO 2 SB 2沉积循环m次和n次; 以及用于使纳米混合电介质膜致密化的步骤。版权所有（C）2007，JPO＆INPIT

4. 发明专利

JP2010004082A Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：JP2010004082A
公开(公告)日：2010-01-07
申请号：JP2009231557
申请日：2009-10-05
申请人： Hynix Semiconductor Inc , 株式会社ハイニックスセミコンダクターHynix Semiconductor Inc.
发明人： KWEON SOON YONG , YEOM SEUNG-JIN , SAI INSEKI , SEONG JIN-YONG
IPC分类号： H01L21/768 , H01L21/8242 , H01L21/02 , H01L21/8246 , H01L27/105 , H01L27/108 , H01L27/115 , H01L31/0328 , H01L31/062
CPC分类号： H01L27/11502 , H01L21/76895 , H01L27/11507 , H01L28/60
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device suppressing generation of step difference to ensure flatness of an underlying electrode of a capacitor to stabilize characteristics of the capacitor.
SOLUTION: The semiconductor device including a basic conductive film 51, an inter-layer insulation film 52 having an inter-layer film contact hole and formed on the upper surface of the basic conductive film 51, an adhesion layer 54 having an adhesion layer contact hole formed in succession to the inter-layer film contact hole and formed on the upper surface of the inter-layer insulation film, a connection part 200 connected to the basic conductive film 51 and flattened on a level with the upper surface of the adhesion layer 54 in a composite contact hole composed of the inter-layer film contact hole and the adhesion layer contact hole and the capacitor having first electrodes 57, 58, a dielectric film 59 and a second electrode 60 formed on the upper surfaces of the connection part 200 and the adhesion layer 54 is manufactured by this manufacturing method.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种制造抑制阶梯差的产生的半导体器件的方法，以确保电容器的底部电极的平坦度，以稳定电容器的特性。解决方案：包括基本导电膜51，具有层间膜接触孔并形成在基底导电膜51的上表面上的层间绝缘膜52的半导体器件，具有粘附力的粘合层54 层间接触孔，形成在层间绝缘膜的上表面上并与层间膜接触孔连续形成;连接部200，其与基本导电膜51连接，在由层间膜接触孔和粘附层接触孔构成的复合接触孔中的粘合层54和具有形成在连接部的上表面上的第一电极57,58，电介质膜59和第二电极60的电容器通过该制造方法制造部件200和粘合层54。版权所有（C）2010，JPO＆INPIT

5. 发明专利

JP2007281407A Method for forming zirconium oxide film of tetragonal structure, and method of manufacturing capacitor provided with the film 有权
标题翻译：用于形成四面体结构的氧化锆薄膜的方法以及用薄膜制造电容器的方法
公开(公告)号：JP2007281407A
公开(公告)日：2007-10-25
申请号：JP2006180955
申请日：2006-06-30
申请人： Hynix Semiconductor Inc , 株式会社ハイニックスセミコンダクターHynix Semiconductor Inc.
发明人： KIL DEOK-SIN , SO KANSO , YEOM SEUNG-JIN , BOKU KIZEN , RO SAISEI , KIM JIN-HYOCK
IPC分类号： H01L21/316 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/108
CPC分类号： H01L21/3141 , C23C16/405 , C23C16/45527 , H01L21/31641 , H01L28/40 , Y02T50/67
摘要： PROBLEM TO BE SOLVED: To provide a method of forming a zirconium oxide film having tetragonal structure of high dielectricity constant and stableness at high temperature, and to provide a method of manufacturing a capacitor comprising the film.
SOLUTION: A tetragonal zirconium oxide film is formed on a substrate by repeating a unit cycle in which injection and purging of zirconium source and injection and purging of an oxidant are continuously performed in a unit atom vapor deposition chamber where the substrate is arranged. Otherwise, a unit cycle is repeated which consists of a first cycle in which injection and purging of zirconium source and injection and purging of oxidant are continuously performed in the unit atom vapor deposition chamber, and a second cycle in which injection of the oxidant (EXTRA_O
3 ) and purging are continuously performed. In the unit atom vapor deposition process, the temperature of a substrate, concentration of the oxidant, and exposure condition of the oxidant are adjusted.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：解决的问题：提供一种在高温下形成具有高介电常数和稳定性的四边形结构的氧化锆膜的方法，并提供一种制造包含该膜的电容器的方法。解决方案：通过重复单元循环在基板上形成四方晶氧化锆膜，其中在单元原子气相沉积室中连续进行锆源的注入和净化以及氧化剂的注入和净化，其中基板布置。否则，重复单元循环，其包括在单元原子气相沉积室中连续执行锆源的注入和净化以及氧化剂的注入和净化的第一循环，以及其中注入氧化剂（EXTRA_O ＆lt; SB＆gt; 3＆lt; SB＆gt;）并进行清洗。在单位原子气相沉积工艺中，调节衬底的温度，氧化剂的浓度和氧化剂的暴露条件。版权所有（C）2008，JPO＆INPIT

6. 发明专利

JP2003179164A SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR 审中-公开
公开(公告)号：JP2003179164A
公开(公告)日：2003-06-27
申请号：JP2002265456
申请日：2002-09-11
申请人： HYNIX SEMICONDUCTOR INC
发明人： KWEON SOON YONG , YEOM SEUNG-JIN , SAI INSEKI , SEONG JIN-YONG
IPC分类号： H01L21/768 , H01L21/02 , H01L21/8242 , H01L21/8246 , H01L27/105 , H01L27/108 , H01L27/115 , H01L27/11507 , H01L31/0328 , H01L31/062
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor element and its manufacturing method which can restrict the occurrence of a step for ensuring the planarity of the lower electrode of a capacitor, and can stabilize capacitor characteristics. SOLUTION: There are provided a basic conductive film 51; an interlayer insulating film 52 which has an interlayer film contact hole and is formed on an upper surface of the basic conductive film 51; an adhesive layer 54 which has an adhesion layer contact hole continuous to the interlayer film contact hole and is formed on an upper surface of the interlayer insulating film; a connection part 200 which is connected to the basic conductive film 51 and is formed by flattening in conformity with the upper surface of the adhesion layer 54, in a composite contact hole composed of the interlayer film contact hole and the adhesion layer contact hole; and a capacitor equipped with first electrodes 57, 58, a dielectric film 59 and a second electrode 60 formed on the upper surface of the connection part 200 and the adhesion layer 54. COPYRIGHT: (C)2003,JPO

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