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1. 发明专利

JP2008226421A Charge trap type nonvolatile memory device, and its programming method 审中-公开
标题翻译：充电陷阱型非易失性存储器件及其编程方法
公开(公告)号：JP2008226421A
公开(公告)日：2008-09-25
申请号：JP2007213283
申请日：2007-08-20
申请人： Hynix Semiconductor Inc , 株式会社ハイニックスセミコンダクターHynix Semiconductor Inc.
发明人： SAI INSEKI , KIM SE JUN , PARK KYOUNG HWAN , YOO HYUN SEUNG
IPC分类号： G11C16/02 , G11C16/04
CPC分类号： G11C16/3454 , G11C16/0466
摘要： PROBLEM TO BE SOLVED: To provide a charge trap type nonvolatile memory device which prevents the phenomenon in which threshold voltage distribution is varied by applying voltage detrapping electric charges shallow-trapped during applying program pulse voltage, and improves reliability of read-out, and also to provide its programming method. SOLUTION: Such processes are included that: the program pulse voltage is applied to a selected memory cell; detrapping pulse voltage for removing shallow-trapped electric charges is applied to the cell to which the program pulse voltage is applied; and the program verification pulse voltage is applied to the memory cell. phenomenon in which distribution of threshold voltage is varied is, therefore, prevented by performing a process in which shallow-trapped electric charges is removed, and reliability of read-out is secured. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种电荷陷阱型非易失性存储装置，其防止在施加编程脉冲电压期间通过施加浅陷阱的电压去除电荷来改变阈值电压分布的现象，并且提高读出的可靠性，并提供其编程方法。解决方案：包括以下过程：将编程脉冲电压施加到选定的存储单元; 去除浅陷阱电荷的去除脉冲电压被施加到施加了编程脉冲电压的单元; 并且将程序验证脉冲电压施加到存储单元。因此，通过执行去除浅陷阱电荷的处理来防止阈值电压的分布变化的现象，并且确保读出的可靠性。版权所有（C）2008，JPO＆INPIT

2. 发明专利

JP2007013171A Method of manufacturing nand flash memory device 审中-公开
标题翻译：制造NAND闪存存储器件的方法
公开(公告)号：JP2007013171A
公开(公告)日：2007-01-18
申请号：JP2006178906
申请日：2006-06-29
申请人： Hynix Semiconductor Inc , 株式会社ハイニックスセミコンダクターHynix Semiconductor Inc.
发明人： SAI INSEKI , KIM NAM KYEONG
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/49 , H01L29/788 , H01L29/792
CPC分类号： H01L29/42324 , H01L21/28273 , H01L27/105 , H01L27/11519 , H01L27/11521 , H01L27/11551
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method of a NAND flash memory device capable of increasing the static capacitance of a floating gate, and improving the reliability of a device.
SOLUTION: The method of manufacturing a NAND flash memory device includes steps of sequentially forming a first conductive film 104 and a hard mask film over a semiconductor substrate 100 in which device insulation films are formed, and then etching given areas of the hard mask film and the first conductive film; forming a second conductive film 108 over the overall structure, and then removing the second conductive film so as to expose the upper portion of the hard mask film; removing the hard mask film and forming three-dimensional floating gates having a jar structure made of the first and second conductive films; and forming a dielectric film 110 and a conductive film 112 for a control gate over the overall structure. Consequently, the static capacitance can be increased in the floating gate, and a program speed can be improved.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供能够增加浮动栅极的静态电容并提高器件的可靠性的NAND闪存器件的制造方法。解决方案：制造NAND闪速存储器件的方法包括以下步骤：在其上形成器件绝缘膜的半导体衬底100上顺序地形成第一导电膜104和硬掩模膜，然后蚀刻给定的硬区域掩模膜和第一导电膜; 在整个结构上形成第二导电膜108，然后去除第二导电膜以暴露硬掩模膜的上部; 去除硬掩模膜并形成具有由第一和第二导电膜制成的罐结构的三维浮动栅; 并在整个结构上形成用于控制栅的电介质膜110和导电膜112。因此，可以在浮动栅极中增加静态电容，并且可以提高编程速度。版权所有（C）2007，JPO＆INPIT

3. 发明专利

JP2010004082A Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：JP2010004082A
公开(公告)日：2010-01-07
申请号：JP2009231557
申请日：2009-10-05
申请人： Hynix Semiconductor Inc , 株式会社ハイニックスセミコンダクターHynix Semiconductor Inc.
发明人： KWEON SOON YONG , YEOM SEUNG-JIN , SAI INSEKI , SEONG JIN-YONG
IPC分类号： H01L21/768 , H01L21/8242 , H01L21/02 , H01L21/8246 , H01L27/105 , H01L27/108 , H01L27/115 , H01L31/0328 , H01L31/062
CPC分类号： H01L27/11502 , H01L21/76895 , H01L27/11507 , H01L28/60
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device suppressing generation of step difference to ensure flatness of an underlying electrode of a capacitor to stabilize characteristics of the capacitor.
SOLUTION: The semiconductor device including a basic conductive film 51, an inter-layer insulation film 52 having an inter-layer film contact hole and formed on the upper surface of the basic conductive film 51, an adhesion layer 54 having an adhesion layer contact hole formed in succession to the inter-layer film contact hole and formed on the upper surface of the inter-layer insulation film, a connection part 200 connected to the basic conductive film 51 and flattened on a level with the upper surface of the adhesion layer 54 in a composite contact hole composed of the inter-layer film contact hole and the adhesion layer contact hole and the capacitor having first electrodes 57, 58, a dielectric film 59 and a second electrode 60 formed on the upper surfaces of the connection part 200 and the adhesion layer 54 is manufactured by this manufacturing method.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种制造抑制阶梯差的产生的半导体器件的方法，以确保电容器的底部电极的平坦度，以稳定电容器的特性。解决方案：包括基本导电膜51，具有层间膜接触孔并形成在基底导电膜51的上表面上的层间绝缘膜52的半导体器件，具有粘附力的粘合层54 层间接触孔，形成在层间绝缘膜的上表面上并与层间膜接触孔连续形成;连接部200，其与基本导电膜51连接，在由层间膜接触孔和粘附层接触孔构成的复合接触孔中的粘合层54和具有形成在连接部的上表面上的第一电极57,58，电介质膜59和第二电极60的电容器通过该制造方法制造部件200和粘合层54。版权所有（C）2010，JPO＆INPIT

4. 发明专利

JP2008141153A Semiconductor memory element, and method of manufacturing the same 审中-公开
标题翻译：半导体存储元件及其制造方法
公开(公告)号：JP2008141153A
公开(公告)日：2008-06-19
申请号：JP2007125211
申请日：2007-05-10
申请人： Hynix Semiconductor Inc , 株式会社ハイニックスセミコンダクターHynix Semiconductor Inc.
发明人： PARK KYOUNG HWAN , SAI INSEKI , KIM SE JUN , YOO HYUN SEUNG
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L29/42324 , H01L21/28282 , H01L29/4234 , H01L29/7881 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory element and a method of manufacturing the same capable of preventing damage of a semiconductor substrate and forming a junction that allows a stable operation by performing an ion-implantation process and then performing a patterning process for forming a blocking layer.
SOLUTION: A semiconductor memory element includes a semiconductor substrate on which a junction is formed, a tunnel insulating film, a charge storage film, a blocking layer and a gate electrode pattern which are sequentially laminated on the semiconductor substrate. The blocking layer has a structure in which a blocking insulating film is surrounded by a high dielectric film.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：解决的问题：提供一种能够防止半导体衬底的损坏并形成通过进行离子注入工艺而允许稳定操作然后进行图案化的结的半导体存储元件及其制造方法形成阻挡层的方法。解决方案：半导体存储元件包括依次层叠在半导体衬底上的形成有结的半导体衬底，隧道绝缘膜，电荷存储膜，阻挡层和栅电极图案。阻挡层具有阻挡绝缘膜被高电介质膜包围的结构。版权所有（C）2008，JPO＆INPIT

5. 发明专利

JP2008091915A Method for manufacturing flash memory device 审中-公开
标题翻译：制造闪速存储器件的方法
公开(公告)号：JP2008091915A
公开(公告)日：2008-04-17
申请号：JP2007253736
申请日：2007-09-28
申请人： Hynix Semiconductor Inc , 株式会社ハイニックスセミコンダクターHynix Semiconductor Inc.
发明人： SAI INSEKI
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521
摘要： PROBLEM TO BE SOLVED: To minimize trap phenomenon, in which charges are confined in an insulating layer on an element isolation structure, and prevent interference between bit lines, in the method for manufacturing flash memory device.
SOLUTION: A tunnel oxide layer 102 and a first conductive layer 103 are formed in an active region on a semiconductor substrate 101, an element isolation structure 104 is formed in a field region. A dielectric layer 105 is formed along the surface of the first conductive layer 103 and an element isolation structure 104, a capping layer 106a is formed along the surface of the dielectric layer 105, and then a hard mask layer 107 is formed on it. Holes 108 are formed by etching the capping layer and the insulating layer on the element isolation structure using the hard mask as an etching mask in a first etching step. In a second etching step, under cuts are formed in the dielectric layer by removing the hard mask layer, then a second conductive layer 106b is formed on a structure consisting of holes 108 and undercuts 109.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了最小化陷波现象，其中电荷被限制在元件隔离结构上的绝缘层中，并且防止位线之间的干扰，在制造闪存器件的方法中。解决方案：在半导体衬底101上的有源区中形成隧道氧化物层102和第一导电层103，在场区域中形成元件隔离结构104。沿着第一导电层103的表面和元件隔离结构104形成电介质层105，沿着电介质层105的表面形成覆盖层106a，然后在其上形成硬掩模层107。通过在第一蚀刻步骤中使用硬掩模作为蚀刻掩模来蚀刻元件隔离结构上的覆盖层和绝缘层来形成孔108。在第二蚀刻步骤中，通过去除硬掩模层在电介质层中形成下切口，然后在由孔108和底切109构成的结构上形成第二导电层106b。（C）2008， JPO＆INPIT

6. 发明专利

JP2003179164A SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR 审中-公开
公开(公告)号：JP2003179164A
公开(公告)日：2003-06-27
申请号：JP2002265456
申请日：2002-09-11
申请人： HYNIX SEMICONDUCTOR INC
发明人： KWEON SOON YONG , YEOM SEUNG-JIN , SAI INSEKI , SEONG JIN-YONG
IPC分类号： H01L21/768 , H01L21/02 , H01L21/8242 , H01L21/8246 , H01L27/105 , H01L27/108 , H01L27/115 , H01L27/11507 , H01L31/0328 , H01L31/062
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor element and its manufacturing method which can restrict the occurrence of a step for ensuring the planarity of the lower electrode of a capacitor, and can stabilize capacitor characteristics. SOLUTION: There are provided a basic conductive film 51; an interlayer insulating film 52 which has an interlayer film contact hole and is formed on an upper surface of the basic conductive film 51; an adhesive layer 54 which has an adhesion layer contact hole continuous to the interlayer film contact hole and is formed on an upper surface of the interlayer insulating film; a connection part 200 which is connected to the basic conductive film 51 and is formed by flattening in conformity with the upper surface of the adhesion layer 54, in a composite contact hole composed of the interlayer film contact hole and the adhesion layer contact hole; and a capacitor equipped with first electrodes 57, 58, a dielectric film 59 and a second electrode 60 formed on the upper surface of the connection part 200 and the adhesion layer 54. COPYRIGHT: (C)2003,JPO

7. 发明专利

JP2002343940A FERROELECTRIC MEMORY ELEMENT AND MANUFACTURING METHOD THEREOF 审中-公开
公开(公告)号：JP2002343940A
公开(公告)日：2002-11-29
申请号：JP2001392020
申请日：2001-12-25
申请人： HYNIX SEMICONDUCTOR INC
发明人： SAI INSEKI
IPC分类号： H01L27/105 , H01L21/02 , H01L21/288 , H01L21/8246 , H01L27/115
摘要： PROBLEM TO BE SOLVED: To provide a ferroelectric memory element and a manufacturing method thereof capable of reducing a load in an etching process for a storage electrode and a plate electrode, and capable of realizing higher integration of a ferroelectric capacitor module. SOLUTION: The manufacturing method includes a step where seed layers 38a and 38b and a sacrifice film are sequentially formed on a semiconductor substrate 31, a step where the sacrifice film is selectively etched to form a center pattern and an annular pattern, a step where first and second electrodes 40a and 40b are formed on the seed layers 38a and 38b exposed in the pattern, a step where, after the sacrifice film is removed, the seed layers 38a and 38b in the region except for the exposed first and second electrode parts are etched and removed, and a step where a ferroelectric film 41 is formed over the entire surface comprising the first and second electrodes 40a and 40b.

8. 发明专利

JP2002053959A THIN FILM DEPOSITION METHOD USING ATOMIC LAYER DEPOSITION METHOD 失效
公开(公告)号：JP2002053959A
公开(公告)日：2002-02-19
申请号：JP2001122184
申请日：2001-04-20
申请人： HYNIX SEMICONDUCTOR INC
发明人： IN SHOKO , SAI INSEKI
IPC分类号： C23C16/40 , H01L21/20 , H01L21/316
摘要： PROBLEM TO BE SOLVED: To provide a thin film deposition method using an atomic layer deposi tion method by which a thin film can be deposited at a high vapor deposition rate. SOLUTION: As a first reactant, Zr (OBut)4 is injected into a chamber loaded with a substrate to adsorb Zr (OBut)4 on the substrate, after that, inert gaseous argon is injected into the chamber to exhaust Zr (OBut)4 or the like which have not been adsorbed on the substrate to the outside of the chamber, and a first purge stage is performed (S100 to S300). Then, as a second reactant, gaseous ammonia is injected into the chamber to decompose Zr (OBut)4 adsorbed on the substrate and to deposit a zirconium oxide thin film, after that, inert gaseous argon is injected into the chamber to exhaust gaseous ammonia or the like which have not reacted to the outside of the chamber, and a second purge stage is performed (S400 and S500).

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