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1. 发明专利

JP2010004082A Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：JP2010004082A
公开(公告)日：2010-01-07
申请号：JP2009231557
申请日：2009-10-05
申请人： Hynix Semiconductor Inc , 株式会社ハイニックスセミコンダクターHynix Semiconductor Inc.
发明人： KWEON SOON YONG , YEOM SEUNG-JIN , SAI INSEKI , SEONG JIN-YONG
IPC分类号： H01L21/768 , H01L21/8242 , H01L21/02 , H01L21/8246 , H01L27/105 , H01L27/108 , H01L27/115 , H01L31/0328 , H01L31/062
CPC分类号： H01L27/11502 , H01L21/76895 , H01L27/11507 , H01L28/60
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device suppressing generation of step difference to ensure flatness of an underlying electrode of a capacitor to stabilize characteristics of the capacitor.
SOLUTION: The semiconductor device including a basic conductive film 51, an inter-layer insulation film 52 having an inter-layer film contact hole and formed on the upper surface of the basic conductive film 51, an adhesion layer 54 having an adhesion layer contact hole formed in succession to the inter-layer film contact hole and formed on the upper surface of the inter-layer insulation film, a connection part 200 connected to the basic conductive film 51 and flattened on a level with the upper surface of the adhesion layer 54 in a composite contact hole composed of the inter-layer film contact hole and the adhesion layer contact hole and the capacitor having first electrodes 57, 58, a dielectric film 59 and a second electrode 60 formed on the upper surfaces of the connection part 200 and the adhesion layer 54 is manufactured by this manufacturing method.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种制造抑制阶梯差的产生的半导体器件的方法，以确保电容器的底部电极的平坦度，以稳定电容器的特性。解决方案：包括基本导电膜51，具有层间膜接触孔并形成在基底导电膜51的上表面上的层间绝缘膜52的半导体器件，具有粘附力的粘合层54 层间接触孔，形成在层间绝缘膜的上表面上并与层间膜接触孔连续形成;连接部200，其与基本导电膜51连接，在由层间膜接触孔和粘附层接触孔构成的复合接触孔中的粘合层54和具有形成在连接部的上表面上的第一电极57,58，电介质膜59和第二电极60的电容器通过该制造方法制造部件200和粘合层54。版权所有（C）2010，JPO＆INPIT

2. 发明专利

JP2003179164A SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR 审中-公开
公开(公告)号：JP2003179164A
公开(公告)日：2003-06-27
申请号：JP2002265456
申请日：2002-09-11
申请人： HYNIX SEMICONDUCTOR INC
发明人： KWEON SOON YONG , YEOM SEUNG-JIN , SAI INSEKI , SEONG JIN-YONG
IPC分类号： H01L21/768 , H01L21/02 , H01L21/8242 , H01L21/8246 , H01L27/105 , H01L27/108 , H01L27/115 , H01L27/11507 , H01L31/0328 , H01L31/062
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor element and its manufacturing method which can restrict the occurrence of a step for ensuring the planarity of the lower electrode of a capacitor, and can stabilize capacitor characteristics. SOLUTION: There are provided a basic conductive film 51; an interlayer insulating film 52 which has an interlayer film contact hole and is formed on an upper surface of the basic conductive film 51; an adhesive layer 54 which has an adhesion layer contact hole continuous to the interlayer film contact hole and is formed on an upper surface of the interlayer insulating film; a connection part 200 which is connected to the basic conductive film 51 and is formed by flattening in conformity with the upper surface of the adhesion layer 54, in a composite contact hole composed of the interlayer film contact hole and the adhesion layer contact hole; and a capacitor equipped with first electrodes 57, 58, a dielectric film 59 and a second electrode 60 formed on the upper surface of the connection part 200 and the adhesion layer 54. COPYRIGHT: (C)2003,JPO

3. 发明专利

JP2012104221A Reading of page buffer circuit with area reduced and program operation method 审中-公开
标题翻译：阅读具有减少和程序操作方法的页面缓冲电路
公开(公告)号：JP2012104221A
公开(公告)日：2012-05-31
申请号：JP2012014417
申请日：2012-01-26
申请人： Hynix Semiconductor Inc , ハイニックスセミコンダクターインク
发明人： SEONG JIN-YONG , WON SAM KYU
IPC分类号： G11C16/02 , G11C16/06
CPC分类号： G11C16/26 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/12 , G11C16/3459 , G11C2211/5642
摘要： PROBLEM TO BE SOLVED: To provide technology for making the area of a page buffer circuit small and also improving operation performance.SOLUTION: Reading is performed in response to a first or second high-order reading signal to store first or second high-order read data in a high-order bit register in accordance with the result, or first or second internal data is stored in the high-order bit register in response to the first or second high-order reading signal and input data received through an input-output node, output data is outputted from an output drive circuit in response to one to be received among the first high-order read data, the second high-order read data, the first internal data and the second internal data, reading is performed in response to a first or second low-order reading signal to store first or second low-order read data in a low-order bit register in accordance with the result, output data is outputted from a first transmission circuit to a sensing node in response to a first writing signal, and the first or second low-order read data is outputted from a second transmission circuit to the sensing node in response to a second writing signal.
摘要翻译：要解决的问题：提供使页面缓冲电路的面积小的技术，并且还提高操作性能。解决方案：响应于第一或第二高阶读取信号执行读取，以根据结果将高位读取数据存储在高位位寄存器中，或者第一或第二内部数据是响应于第一或第二高阶读取信号和通过输入 - 输出节点接收的输入数据存储在高位位寄存器中，输出数据从输出驱动电路输出，以响应于要在第一响应于第一或第二低位读取信号执行高阶读取数据，第二高阶读取数据，第一内部数据和第二内部数据读取，以将第一或第二低位读取数据存储在根据结果的低位寄存器，响应于第一写入信号将输出数据从第一传输电路输出到感测节点，并且第一或第二低位读取数据从第二传输电路输出到了响应于第二写入信号。版权所有（C）2012，JPO＆INPIT

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