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1. 发明专利

JPS56110151A COMBINATION SYSTEM ARITHMETIC CIRCUIT 失效
公开(公告)号：JPS56110151A
公开(公告)日：1981-09-01
申请号：JP1279480
申请日：1980-02-05
申请人： NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , NIPPON ELECTRIC CO , HITACHI LTD , FUJITSU LTD
发明人： MIYAGUCHI SHIYOUJI , MIZUTA HIROSHI , MIZUTA MASANORI , FURUYA KUNIO , HIGUCHI TAIHOU
IPC分类号： G09C1/00 , G06F7/72 , G09C1/10
摘要： PURPOSE:To attain a high speed and economical circuit by constituting the circuit mainly of a controlling circuit correcting a multiplying circuit which calculates a temporary remainder, and a temporary remainder, by means of comparison and subtraction of two times. CONSTITUTION:When a data I and a dividend P are input to the multiplication part 10, the product Q2 of P and I is output. This product Q2 is provided to the operation part 20 for omitting fractions, and the value Q1 whose low rank bit has been omitted can be obtained. When this data Q1 and a divisor N are input to the multiplier 30, NXQ1=P1 is output to the signal line. On the other hand, the data P and P1 are input to the subtraction and comparison part 40. The control circuit 43 executes a subtraction P-P1=R1 and outputs it to the shift register 42. Keeping pace with said operation, the circuit 43 inputs the divisor N, and in case of R1>=N, R1-N=R2 is calculated, and it is output to the register 42. Also, in case of R2>=N, the circuit 43 calculates R2-N=R3, and outputs it to the register 42. When R1, R2 or R3 has become smaller than N, keeping pace with said operation, the value R is output onto the signal line 50.

2. 发明专利

JPS5633732A CHARACTER COMPRESSING DEVICE 失效
公开(公告)号：JPS5633732A
公开(公告)日：1981-04-04
申请号：JP10879879
申请日：1979-08-27
申请人： NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , NIPPON ELECTRIC CO , HITACHI LTD , FUJITSU LTD
发明人： HORIGUCHI MASATOSHI , MIYAGUCHI SHIYOUJI , KAWAMURA YASUSUKE , MIZUTA MASANORI , FURUYA KUNIO , HIGUCHI TAIHOU
IPC分类号： H04L23/00 , G06F5/00 , G06F13/00
摘要： PURPOSE:To ensure a high-speed process and then realize an effective use of the external memory device within the system, by securing an independence of the function to give a high-speed compression and restoration to the information composed of the code raw from the process part of the CPU and also realizing the function with the hardware such as the LSI or the like. CONSTITUTION:Receiving the indication for start of the process, the character compressing device 102 reads the unprocessed data within the memory 104 via the memory control part 103 and based on the information given from the process part 101. Then the process indicated in the working mode is applied, and the processed data is written into the prescribed position of the memory 104. This action is given to all data, and an interruption is applied to the part 101 when the process completes. And in case the device 102 gives a process of compression, the part 101 transmits the processed data to the external unit via the communication control part 105. While in case the data received from the external unit is restored, the process restoration is completed by the interruption. In this way, a high-speed process is possible for the character compressing device, thus ensuring an effective use of the external unit in the system.

3. 发明专利

JPS5640343A DATA CONVERTING METHOD 失效
公开(公告)号：JPS5640343A
公开(公告)日：1981-04-16
申请号：JP11620279
申请日：1979-09-12
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO , FUJITSU LTD , OKI ELECTRIC IND CO LTD
发明人： FURUYA KUNIO , MIYAGUCHI SHIYOUJI , MIZUTA MASANORI , HIGUCHI TAIHOU , KAWAMURA YASUSUKE
IPC分类号： H04K1/00 , H04L9/06 , H04L9/18
摘要： PURPOSE:To shorten the processing time, by dividing input data into every several bits and by arranging divided input data in arbitrary several bytes respectively and by performing the ciphering processing by the unit of one or more bytes, in data conversion for ciphering. CONSTITUTION:The ordinary writing of 8-byte codes is subjected to the character transfer processing first. Next, input data is divided by four bits successively, and divided four bits are stuffed to the right half of one byte of output data to expand the preceding 8-byte output to double 16 bytes. These 16 bytes are divided into right 8 bytes and left 8 bytes (r0 and l0), and r0 is subjected to the expansion character transfer processing. Meanwhile, 48-bit (6-byte) key is expanded to 8-bytes, and exclusive OR between this key and the output of the expansion transfer processing is operated for every bit. Next, the compressional character conversion processing and the character transfer processing are performed to operate exclusive OR between the key and l0 for every bit. By repeating these processings, the original code is converted to a new code.

4. 发明专利

JPS5642852A MULTIPLICATION*DIVISION CIRCUIT 失效
公开(公告)号：JPS5642852A
公开(公告)日：1981-04-21
申请号：JP11979379
申请日：1979-09-18
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , NIPPON ELECTRIC CO , HITACHI LTD
发明人： HIGUCHI TAIHOU , MIYAGUCHI SHIYOUJI , KAWAMURA YASUSUKE , MIZUTA MASANORI , FURUYA KUNIO
IPC分类号： G06F7/496 , G06F7/507 , G06F7/52 , G06F7/527 , G06F7/72 , G09C1/00 , H04L9/30
摘要： PURPOSE:To ensure an effective operation of ME(MODN), by giving a control to the arithmetic process based on the result of the binary expansion of the power multiplier. CONSTITUTION:The data M, the divisor N and the power multiplier E are stored in the registers 2, 3 and 4 each. And the process is carried out as follows based on the result of the binary expansion of the multiplier E in the register 4. That is, the gate 8 is opened in case the bit is 0 as the result of expansion, and the contents of the register 1 is squared via the multiplier 5. And this result receives a division by the divider 6 and via the contents of the register 3, and the residue thus obtained is stored in the register 1. And in case the bit is 1, the same operation as the bit 0 is carried out. And furthermore the gate 9 is opened to give the multiplication 5 to the contents of the registers 1 and 2 each, and this result is divided 5 by the contents of the register 3 with the residue stored in the register 1. In such way, no repetition is required for the multiplication of the frequency of the power multiplier, thus ensuring an effective operation.

5. 发明专利

JPS5642449A CODER 失效
公开(公告)号：JPS5642449A
公开(公告)日：1981-04-20
申请号：JP11734579
申请日：1979-09-14
申请人： OKI ELECTRIC IND CO LTD , NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO , HITACHI LTD , FUJITSU LTD
发明人： KAWAMURA YASUSUKE , MIYAGUCHI SHIYOUJI , MIZUTA MASANORI , FURUYA KUNIO , HIGUCHI TAIHOU
IPC分类号： H04K1/00 , G09C1/00 , H04L9/00 , H04L9/10 , H04L9/30
摘要： PURPOSE:To make it possible to shorten coding or decoding time by providing a coding or decoding arithmetic part with two modulo calculation parts that include multipliers and dividers and then by putting them in parallel operation. CONSTITUTION:Coder 10 is provided with two modulo calculation parts All and B12, which include multipliers 13a and 13b, registers 14a and 14b stored with results of multipliers 13a and 13b, dividers 15a and 15b outputting only remainders, and registers 16a and 16b. For coding process, the 1st and 2nd key codes (n) and (e) are externally set in the 5th and 7th registers 18 and 20, and data bit block (m) as a coding unit in the 6th register 19. On receiving coding operation indication signal 34 externally, control part 21 sets the contents of register 19 in register 16a and then repeats the modulo calculation from the least significant bit to the most significant bit by the bit length of binary expanded key code (e).

6. 发明专利

JPS5713529A PROGRAM LOADING SYSTEM 失效
公开(公告)号：JPS5713529A
公开(公告)日：1982-01-23
申请号：JP8750680
申请日：1980-06-27
申请人： NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO , FUJITSU LTD , HITACHI LTD
发明人： AOYAMA MASAO , TAMADA SHINICHI , GOUHARA MASAO , FURUYA KUNIO
IPC分类号： G06F1/00 , G06F9/445
摘要： PURPOSE:To diminish the number of man-hours for preparing a bootstrap program BSP, by providing a means for freely setting a classification of a program PRG to be loaded, by manual operation, in each control part which is under control of a higher rank prcessing part. CONSTITUTION:A CPU24 which is higher rank processing part is connected to a control part 21 of an external memory control device or a communication control devie, etc., by an interface signal line 25. The control part 21 is provided with a ROM23 in which a BSP is stored, a RAM22 to which a PRG is loaded, and a register 26 which is able to freely set a classification of a program to be loaded newly, by manual operation. When an electric power source is closed to the control part or a start commnad for loading is received from the CPU24, the BSP of the ROM23 starts its operation, and contents which have been set to the register 26 are read out and are informed to the CPU through the signal line 25. The CPU 24 recognizes a classification of the PRG which has been informed, and transfers a related PRG to the control part 21. In this way, since one kind of BSP will do, the number of man-hours for preparing a BSP is diminished.

7. 发明专利

JPS56123032A COMMUNICATION CONTROLLING PROCESSOR 失效
公开(公告)号：JPS56123032A
公开(公告)日：1981-09-26
申请号：JP2711280
申请日：1980-03-04
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO , HITACHI LTD
发明人： OGASAWARA SHIGERU , TAKAHASHI HIROSHI , AOYAMA MASAO , MIURA TETSUO , FURUYA KUNIO
IPC分类号： H04L29/04 , G06F13/00 , G06F13/12
摘要： PURPOSE:To reduce the hardware constitution of the line controlling common part, by reading the command word, which is held in the main memory, to transfer it to the line controlling adapter part, in the line controlling common part where command word address information can be held. CONSTITUTION:The address storing memory where address information on main storage device 6 storing the command word read from the host data processor 1 side can be held is provided in line controlling common part 9 which is provided in communication controlling processor 4 and controls plural line controlling adaper parts LCA in common. When a designated line is started, address information of the command word on this line is stored in this memory, and the command word on device 6 is received on the basis of address information according to following processing by line controlling common part 9 and is transferred to adapter LCA. By this constitution, hardware of line controlling common part 9 is reduced.

8. 发明专利

JPS5750152A Communication control processor 失效
标题翻译：通信控制处理器
公开(公告)号：JPS5750152A
公开(公告)日：1982-03-24
申请号：JP12548880
申请日：1980-09-10
申请人： Fujitsu Ltd , Hitachi Ltd , Nec Corp , Nippon Telegr & Teleph Corp
发明人： MIURA TETSUO , HIRAIDE TOSHIHIKO , AOYAMA MASAO , FURUYA KUNIO , OGASAWARA SHIGERU
IPC分类号： H04L29/04 , G06F13/00 , G06F13/22
CPC分类号： G06F13/22
摘要： PURPOSE:To achieve start control saving the hardware, by minimizing the effect on other line control adaptor. CONSTITUTION:A line common control section 1 consists of a control circuit 2, a start flag 3 storing the indication of start, an address register storing the line address indicated of starting, a scanning counter 5, a switching circuit 6 and a data buffer 7, and it is connected to a data bus 8 and a control bus 9. A line control adaptor 10 consists of an adaptor control circuit 11, a start-enable-flag 12 which displays the start reception enable being logic ''1'' when the preparation of reception of start information is finished, processing request flag 13 displaying the processing request, data buffer 14 in an adaptor, common bus 15 in the adaptor and a plurality of line interface circuits 16.
摘要翻译：目的：通过最小化对其他线路控制适配器的影响，实现启动控制，节省硬件。线路公共控制部分1包括控制电路2，存储开始指示的开始标志3，存储起始线路地址的地址寄存器，扫描计数器5，切换电路6和数据缓冲器7 ，并且连接到数据总线8和控制总线9.线路控制适配器10包括适配器控制电路11，启动使能标志12，其将起始接收使能显示为逻辑“1” 开始信息的接收准备完成，显示处理请求的处理请求标志13，适配器中的数据缓冲器14，适配器中的公共总线15以及多个线路接口电路16。

9. 发明专利

JPH02133844A MEMORY DIAGNOSTIC SYSTEM 失效
公开(公告)号：JPH02133844A
公开(公告)日：1990-05-23
申请号：JP28863588
申请日：1988-11-14
申请人： HITACHI LTD , HITACHI COMPUTER ELECTRONIC
发明人： SASAKI SATOSHI , SHIMIZU RYOICHI , MORITA EIBOKU , FURUYA KUNIO
IPC分类号： G06F12/16
摘要： PURPOSE:To perform both the data writing and verifying jobs in a single DMA transfer and to effectively diagnose a memory by collating the data latched by the data writing and reading with each other, and performing the memory diagnosis. CONSTITUTION:A write data latch circuit 3 latches the data on a data bus 11 when a CPU 1 writes data into a memory 2. While a read data latch circuit 4 latches the data on the bus 11 when the CPU 1 reads data out of the memory 2. A comparator 5 compares the data received from both circuits 3 and 4 with each other. Then the data transmitter and receiver addresses are set at the same value when the memory 2 is diagnosed, and the comparator 5 compares the write data with the read data. As a result, both the data writing and verifying are carried out at one time in a single DMA transfer. Then the memory state is diagnosed at a high speed and with high efficiency.

10. 发明专利

JPS62214454A EVENT RECORDING SYSTEM FOR INPUT/OUTPUT CONTROLLER 失效
公开(公告)号：JPS62214454A
公开(公告)日：1987-09-21
申请号：JP5685586
申请日：1986-03-17
申请人： HITACHI LTD , HITACHI COMPUTER ELECTRONIC
发明人： SHIMIZU RYOICHI , FURUYA KUNIO
IPC分类号： G06F11/34 , G06F13/00 , G06F13/12
摘要： PURPOSE:To monitor the state of the titled device by recording events related to status information of an input/output controller in time series and transmitting these events by an instruction from a processor and making it possible to start and stop a recording means. CONSTITUTION:An input/output controller 2 is provided with a ROM 100 for microprogram storage and a RAM 101 for storage of recording and control information of events, and the controller 2 is controlled through a channel 8 by a program 5, a main storage 6 of a processor 3, and an arithmetic unit 7. In this case, the controller 2 is started by an instruction from the processor 3 to decode the instruction by the program in the ROM 100; and if the instruction indicates the start of event recording, event recording conditions are analyzed to give an address of the RAM 101, and objects of event recording are set to record them on the RAM 101 in time series. Event recording is stopped by decoding the instruction by the program, and recording on the RAM 101 in time series is stopped when the stop is indicated.

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