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1. 发明专利

JPS5633732A CHARACTER COMPRESSING DEVICE 失效
公开(公告)号：JPS5633732A
公开(公告)日：1981-04-04
申请号：JP10879879
申请日：1979-08-27
申请人： NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , NIPPON ELECTRIC CO , HITACHI LTD , FUJITSU LTD
发明人： HORIGUCHI MASATOSHI , MIYAGUCHI SHIYOUJI , KAWAMURA YASUSUKE , MIZUTA MASANORI , FURUYA KUNIO , HIGUCHI TAIHOU
IPC分类号： H04L23/00 , G06F5/00 , G06F13/00
摘要： PURPOSE:To ensure a high-speed process and then realize an effective use of the external memory device within the system, by securing an independence of the function to give a high-speed compression and restoration to the information composed of the code raw from the process part of the CPU and also realizing the function with the hardware such as the LSI or the like. CONSTITUTION:Receiving the indication for start of the process, the character compressing device 102 reads the unprocessed data within the memory 104 via the memory control part 103 and based on the information given from the process part 101. Then the process indicated in the working mode is applied, and the processed data is written into the prescribed position of the memory 104. This action is given to all data, and an interruption is applied to the part 101 when the process completes. And in case the device 102 gives a process of compression, the part 101 transmits the processed data to the external unit via the communication control part 105. While in case the data received from the external unit is restored, the process restoration is completed by the interruption. In this way, a high-speed process is possible for the character compressing device, thus ensuring an effective use of the external unit in the system.

2. 发明专利

JPS5177147A Deetashorihoshiki 失效
公开(公告)号：JPS5177147A
公开(公告)日：1976-07-03
申请号：JP258375
申请日：1974-12-27
申请人： Nippon Electric Co , Nippon Telegraph & Telephone , Oki Electric Ind Co Ltd , Hitachi Ltd , Fujitsu Ltd
发明人： ARAI SHIGERU , YOSHIDA SHINICHIRO , YAMAZAKI SHINJI , KAWAMURA YASUSUKE , HORIKI AKIRA , NOMURA TETSUHIRO
IPC分类号： G06F3/00 , G06F13/00

3. 发明专利

JPS5640343A DATA CONVERTING METHOD 失效
公开(公告)号：JPS5640343A
公开(公告)日：1981-04-16
申请号：JP11620279
申请日：1979-09-12
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO , FUJITSU LTD , OKI ELECTRIC IND CO LTD
发明人： FURUYA KUNIO , MIYAGUCHI SHIYOUJI , MIZUTA MASANORI , HIGUCHI TAIHOU , KAWAMURA YASUSUKE
IPC分类号： H04K1/00 , H04L9/06 , H04L9/18
摘要： PURPOSE:To shorten the processing time, by dividing input data into every several bits and by arranging divided input data in arbitrary several bytes respectively and by performing the ciphering processing by the unit of one or more bytes, in data conversion for ciphering. CONSTITUTION:The ordinary writing of 8-byte codes is subjected to the character transfer processing first. Next, input data is divided by four bits successively, and divided four bits are stuffed to the right half of one byte of output data to expand the preceding 8-byte output to double 16 bytes. These 16 bytes are divided into right 8 bytes and left 8 bytes (r0 and l0), and r0 is subjected to the expansion character transfer processing. Meanwhile, 48-bit (6-byte) key is expanded to 8-bytes, and exclusive OR between this key and the output of the expansion transfer processing is operated for every bit. Next, the compressional character conversion processing and the character transfer processing are performed to operate exclusive OR between the key and l0 for every bit. By repeating these processings, the original code is converted to a new code.

4. 发明专利

JPS515910A 失效
公开(公告)号：JPS515910A
公开(公告)日：1976-01-19
申请号：JP7664474
申请日：1974-07-04
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , NIPPON ELECTRIC CO , FUJITSU LTD
发明人： HORIKI AKIRA , SAKAI YOICHI , KAWAMURA YASUSUKE , YOSHIDA YOSHINORI , SATO HIROAKI
IPC分类号： H04Q3/545 , H04Q3/54 , H04Q11/04

5. 发明专利

JPS5222406A CONTROL SYSTEM AMONG INFORMATION PROCESSING UNITS 失效
公开(公告)号：JPS5222406A
公开(公告)日：1977-02-19
申请号：JP9872375
申请日：1975-08-13
申请人： NIPPON ELECTRIC CO , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , HITACHI LTD , FUJITSU LTD
发明人： MAKINO HIDEYO , MORI MASAHARU , KAWAMURA YASUSUKE , KOUNO YOSHIYA , URUSHIHARA TETSUO
IPC分类号： G06F13/38 , H04Q3/545
摘要： PURPOSE:To simplify the installation, without lowering the efficiency of the equipment, by performing information transmission among the ifformation processing units by a serial transmission of one bit at a time with the use of shift registers.

6. 发明专利

JPS5642852A MULTIPLICATION*DIVISION CIRCUIT 失效
公开(公告)号：JPS5642852A
公开(公告)日：1981-04-21
申请号：JP11979379
申请日：1979-09-18
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , NIPPON ELECTRIC CO , HITACHI LTD
发明人： HIGUCHI TAIHOU , MIYAGUCHI SHIYOUJI , KAWAMURA YASUSUKE , MIZUTA MASANORI , FURUYA KUNIO
IPC分类号： G06F7/496 , G06F7/507 , G06F7/52 , G06F7/527 , G06F7/72 , G09C1/00 , H04L9/30
摘要： PURPOSE:To ensure an effective operation of ME(MODN), by giving a control to the arithmetic process based on the result of the binary expansion of the power multiplier. CONSTITUTION:The data M, the divisor N and the power multiplier E are stored in the registers 2, 3 and 4 each. And the process is carried out as follows based on the result of the binary expansion of the multiplier E in the register 4. That is, the gate 8 is opened in case the bit is 0 as the result of expansion, and the contents of the register 1 is squared via the multiplier 5. And this result receives a division by the divider 6 and via the contents of the register 3, and the residue thus obtained is stored in the register 1. And in case the bit is 1, the same operation as the bit 0 is carried out. And furthermore the gate 9 is opened to give the multiplication 5 to the contents of the registers 1 and 2 each, and this result is divided 5 by the contents of the register 3 with the residue stored in the register 1. In such way, no repetition is required for the multiplication of the frequency of the power multiplier, thus ensuring an effective operation.

7. 发明专利

JPS5642449A CODER 失效
公开(公告)号：JPS5642449A
公开(公告)日：1981-04-20
申请号：JP11734579
申请日：1979-09-14
申请人： OKI ELECTRIC IND CO LTD , NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO , HITACHI LTD , FUJITSU LTD
发明人： KAWAMURA YASUSUKE , MIYAGUCHI SHIYOUJI , MIZUTA MASANORI , FURUYA KUNIO , HIGUCHI TAIHOU
IPC分类号： H04K1/00 , G09C1/00 , H04L9/00 , H04L9/10 , H04L9/30
摘要： PURPOSE:To make it possible to shorten coding or decoding time by providing a coding or decoding arithmetic part with two modulo calculation parts that include multipliers and dividers and then by putting them in parallel operation. CONSTITUTION:Coder 10 is provided with two modulo calculation parts All and B12, which include multipliers 13a and 13b, registers 14a and 14b stored with results of multipliers 13a and 13b, dividers 15a and 15b outputting only remainders, and registers 16a and 16b. For coding process, the 1st and 2nd key codes (n) and (e) are externally set in the 5th and 7th registers 18 and 20, and data bit block (m) as a coding unit in the 6th register 19. On receiving coding operation indication signal 34 externally, control part 21 sets the contents of register 19 in register 16a and then repeats the modulo calculation from the least significant bit to the most significant bit by the bit length of binary expanded key code (e).

8. 发明专利

JPS5222846A DATA PROCESSING UNIT 失效
公开(公告)号：JPS5222846A
公开(公告)日：1977-02-21
申请号：JP9856775
申请日：1975-08-15
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , NIPPON ELECTRIC CO , FUJITSU LTD
发明人： HIRAI FUMIO , HONMA KATSUTOSHI , KAWAMURA YASUSUKE , YAZAWA KATSUHIKO , KATSUKI TOSHIO
IPC分类号： G06F9/24 , G06F9/22 , G06F9/28 , G06F9/445 , G06F11/22 , G06F15/16 , G06F15/177
摘要： PURPOSE:To provide a micro program loading method which is flexible and requires less hardware components among the miscellaneous circuits in the unit.

9. 发明专利

JPS5933557A Data flow control system 失效
标题翻译：数据流量控制系统
公开(公告)号：JPS5933557A
公开(公告)日：1984-02-23
申请号：JP14218182
申请日：1982-08-18
申请人： Oki Electric Ind Co Ltd
发明人： KUZUMI SHIYOUSUKE , ITOU NORIYOSHI , YASUHARA HIROSHI , KAWAMURA YASUSUKE
IPC分类号： G06F9/44 , G06F12/00
CPC分类号： G06F9/4436
摘要： PURPOSE:To increase the utilizing efficiency of a memory and to prevent overflow, by using separately an area where an operand memory is assigned in the unit of block and the unit of one entry. CONSTITUTION:A chain storage section CHM11 of a physical block managing table 8 stores the next physical block number when the physical block is chained. A logical block number storage section LBM10 stores the logical block number LB when the physical block is assigned to the logical block. A talk number storage section 12 represents the operand number and when it is 0, it represents that the physical block is not in use. When a chain end indicating flag 13 is 0, it represents that the physical block is located on the way of chain and when it is 1, the flag 13 represents that the block is at the end of chain as one-bit flag. The CHM11 and a LBM10 assign the operand memory in the unit of one entry in the overflow area or brings the operand memory into a chain state.
摘要翻译：目的：为了提高存储器的利用效率和防止溢出，通过单独使用以块为单位分配操作数存储器的区域和一个条目的单位。构成：当物理块被链接时，物理块管理表8的链存储部CHM11存储下一个物理块号。当物理块被分配给逻辑块时，逻辑块号存储部分LBM10存储逻辑块号LB。通话号码存储部分12表示操作数，当它为0时，它表示物理块未被使用。当链末端指示标志13为0时，它表示物理块位于链路上，当它为1时，标志13表示该块作为一位标志在链的末尾。 CHM11和LBM10以溢出区域中的一个条目为单位分配操作数存储器，或将操作数存储器置于链状态。

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