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1. 发明专利

JPS6077253A CONTROL SYSTEM OF INPUT/OUTPUT INSTRUCTION 失效
公开(公告)号：JPS6077253A
公开(公告)日：1985-05-01
申请号：JP18555583
申请日：1983-10-04
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO , HITACHI LTD
发明人： SHIBATA HIROKI , OGASAWARA SHIGERU , SAWAI TOSHIO , AOYAMA MASAO , IDE DAISAKU , YAMAGA MITSUHIRO
IPC分类号： G06F13/36 , G06F13/10 , G06F13/12
摘要： PURPOSE:To attain I/O instruction control preventing overrun or underrun by providing an instruction retry requesting signal and an instruction suppressing signal between a processing part and a peripheral part and opening a common bus temporally or quickly on the basis of the state of peripheral parts. CONSTITUTION:A processing part PU of an information processor reads out an instruction stored in a memory part MM and executes the instruction successively. If the read-out instruction is an I/O instruction to/from the peripheral parts (ADP0-ADPn), the I/O instruction operation is specified by using the common bus. Each peripheral part discriminates the I/O instruction operating information on the common bus and an external register address, and if the address is the self-address, the I/O instruction operation is executed. An I/O instruction retry requesting signal RETRY is a signal informing the busy status of the peripheral parts and an instruction suppressing signal WAIT is a signal displaying the execution status at the operation of the output instruction of the peripheral part and is used for the suppression of advancement of the instruction in the processing part.

2. 发明专利

JPS5714939A COMMUNICATION CONTROLLING PROCESSOR 失效
公开(公告)号：JPS5714939A
公开(公告)日：1982-01-26
申请号：JP9013880
申请日：1980-07-02
申请人： NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO , FUJITSU LTD , HITACHI LTD
发明人： AOYAMA MASAO , MIURA TETSUO , OGASAWARA SHIGERU , NAGAFUKU KATSUTERU
IPC分类号： H04L29/04 , G06F13/00 , G06F13/22 , H04L29/10
摘要： PURPOSE:To ensure a highly efficient transfer of information, by varying the scan time to a circuit adaptor in accodance with the presence of absence of transfer of information as well as the type of the information tranferred between the circuit adaptor and the circuit control common part. CONSTITUTION:Both the transfer-enable-or-unable-information plus a transfer request to be given to a circuit adaptor 1 is informed to a circuit control common part 3, and a prescribed number of information are transferred 4 en bloc with just one scan to the adaptor 1 for control 8. At the same time, the end of transfer of information is informed to the part 3. The part 3 gives an indication 2 of information transfer control to the adaptor 1 during scan of the adaptor 1 and in accordance with the presence or absence of the transfer-enable-or-unable information plus the transfer request and others. And the selection of the adaptor 1 is kept for the scan during transfer of information.

3. 发明专利

JPS56110128A DATA TRANSFER SYSTEM 失效
公开(公告)号：JPS56110128A
公开(公告)日：1981-09-01
申请号：JP1328280
申请日：1980-02-06
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO , HITACHI LTD
发明人： NAKAMURA TAKASHI , OGASAWARA SHIGERU , AOYAMA MASAO , SHIMADA SETSUO , MAKIURA YASUHIKO
IPC分类号： G06F13/38 , G06F9/48 , G06F13/24
摘要： PURPOSE:To make it possible to exactly transfer a data without requiring many registers, by generating an interruption signal when the transfer register has become vacant after reading it to the processor that said register is full. CONSTITUTION:When a data to be transferred has been generated, a state of the latch FF-1 which has been defined to the address (b) is read. As a result, if it is shown that the FF-1 is vacant, it is possible to write in the register RG, and a data is written in the register RG. On the other hand, when a state of the FF-1 has been read, if it is displayed that the FF-1 is full, the program of the processor P is unable to write a data in the register RG. In this case, the hardware stores by the latch FF- 2 that it has been read into the processor P that the FF-1 is full, and after that, when the register RG has become vacant, an interruption signal I is generated. The program writes a data into the register RG by detecting this interruption.

4. 发明专利

JPS6081648A INFORMATION PROCESSOR 失效
公开(公告)号：JPS6081648A
公开(公告)日：1985-05-09
申请号：JP18851983
申请日：1983-10-11
申请人： NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO , HITACHI LTD , FUJITSU LTD
发明人： AOYAMA MASAO , NAKAMURA KOUICHI , YAMAGA MITSUHIRO , OGASAWARA SHIGERU
IPC分类号： G06F9/46 , G06F9/48 , G06F15/16 , G06F15/177
摘要： PURPOSE:To generate program control interruption to one processing part simultaneously with the interruption to another processing part by providing an FF, and an interruption control circuit, etc. which can be set up by an instruction holding the program control interruption. CONSTITUTION:When an processing part 2 executes instructions successively and executes an instruction to set up an FF7, the FF7 is set up. Consequently, an output signal from the FF7 is immediately informed to respective processing parts 2 through a signal line 8. If te state of the signal line 8 is changed, an interruption control circuit 9 detects an interruption request and allows the interruption request to interrupt an instruction execution part 6. The instruction execution part 6 accepts the interruption request at the end of the operation of the executing instruction to execute interrupting processing. Thus, the program control interruption request specified by a certain processing part 2 can be informed to all the processing parts at the end of the execution of the instruction of another processing part when the interruption is generated. If it is unnecessary to left the processing status at the generation of the interruption, it may be also available to set up an interruption masking setting circuit 11 to accept the interruption.

5. 发明专利

JPS56123032A COMMUNICATION CONTROLLING PROCESSOR 失效
公开(公告)号：JPS56123032A
公开(公告)日：1981-09-26
申请号：JP2711280
申请日：1980-03-04
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO , HITACHI LTD
发明人： OGASAWARA SHIGERU , TAKAHASHI HIROSHI , AOYAMA MASAO , MIURA TETSUO , FURUYA KUNIO
IPC分类号： H04L29/04 , G06F13/00 , G06F13/12
摘要： PURPOSE:To reduce the hardware constitution of the line controlling common part, by reading the command word, which is held in the main memory, to transfer it to the line controlling adapter part, in the line controlling common part where command word address information can be held. CONSTITUTION:The address storing memory where address information on main storage device 6 storing the command word read from the host data processor 1 side can be held is provided in line controlling common part 9 which is provided in communication controlling processor 4 and controls plural line controlling adaper parts LCA in common. When a designated line is started, address information of the command word on this line is stored in this memory, and the command word on device 6 is received on the basis of address information according to following processing by line controlling common part 9 and is transferred to adapter LCA. By this constitution, hardware of line controlling common part 9 is reduced.

6. 发明专利

JPS5750152A Communication control processor 失效
标题翻译：通信控制处理器
公开(公告)号：JPS5750152A
公开(公告)日：1982-03-24
申请号：JP12548880
申请日：1980-09-10
申请人： Fujitsu Ltd , Hitachi Ltd , Nec Corp , Nippon Telegr & Teleph Corp
发明人： MIURA TETSUO , HIRAIDE TOSHIHIKO , AOYAMA MASAO , FURUYA KUNIO , OGASAWARA SHIGERU
IPC分类号： H04L29/04 , G06F13/00 , G06F13/22
CPC分类号： G06F13/22
摘要： PURPOSE:To achieve start control saving the hardware, by minimizing the effect on other line control adaptor. CONSTITUTION:A line common control section 1 consists of a control circuit 2, a start flag 3 storing the indication of start, an address register storing the line address indicated of starting, a scanning counter 5, a switching circuit 6 and a data buffer 7, and it is connected to a data bus 8 and a control bus 9. A line control adaptor 10 consists of an adaptor control circuit 11, a start-enable-flag 12 which displays the start reception enable being logic ''1'' when the preparation of reception of start information is finished, processing request flag 13 displaying the processing request, data buffer 14 in an adaptor, common bus 15 in the adaptor and a plurality of line interface circuits 16.
摘要翻译：目的：通过最小化对其他线路控制适配器的影响，实现启动控制，节省硬件。线路公共控制部分1包括控制电路2，存储开始指示的开始标志3，存储起始线路地址的地址寄存器，扫描计数器5，切换电路6和数据缓冲器7 ，并且连接到数据总线8和控制总线9.线路控制适配器10包括适配器控制电路11，启动使能标志12，其将起始接收使能显示为逻辑“1” 开始信息的接收准备完成，显示处理请求的处理请求标志13，适配器中的数据缓冲器14，适配器中的公共总线15以及多个线路接口电路16。

7. 发明专利

JPS58169261A ALARM DISPLAY 失效
公开(公告)号：JPS58169261A
公开(公告)日：1983-10-05
申请号：JP5259182
申请日：1982-03-31
申请人： NIPPON ELECTRIC CO
发明人： OGASAWARA SHIGERU
IPC分类号： G06F11/32
摘要： PURPOSE:To control alarm factor information concentrically and to facilitate the diversion of a program of a data processor to an other system, by making an alarm display independent of the data processor, and performing operation according to the contents of the memory in the display device. CONSTITUTION:An alarm display 2 is made independent of a data processor 1 and an alarm control circuit 4 of the display 2 receives the indication of alarm information from a processor 1. This indication is written in the memory through an alarm writing circuit 5 to store the alarm information. Then, when the processor 1 detects the generation of an alarm factor, the control circuit 4 instructs a decoder 6 to turn on alarm lamps L0-Ln selectively corresponding to the alarm factor. The decoder 6 receiving the indication reads information corresponding to the alarm factor in a memory 7 to turn on the lamps L0-Ln seletively. Thus, the alarm factor information is controlled concentrically to facilitate the diversion of programs of the processor 1 to other systems.

8. 发明专利

JPS6158067A Maintenance system of communication control device 失效
标题翻译：通信控制设备维护系统
公开(公告)号：JPS6158067A
公开(公告)日：1986-03-25
申请号：JP17955584
申请日：1984-08-29
申请人： Fujitsu Ltd
发明人： OGASAWARA SHIGERU
IPC分类号： H04L29/04 , G06F11/30 , G06F11/34 , G06F13/00 , H04L13/00
摘要： PURPOSE: To retrieve a trouble easily by sampling a hardware condition of a designated circuit after the designated time from the designated microstep in a request processing condition.
CONSTITUTION: A register SLNR is installed so that a trace of a hardware condition can be obtained when a designated circuit is scanned, and a circuit number of a checking object is set to this register. When a microprogram step is successively read from a memory MPM, a trigger effective bit TEB is read, this is inputted through a register OP to only one AND gate G2. A non-scanning circuit number is coincident with a circuit number set to the register SLNR, and then, a comparing circuit COMP generates an coincident output, and when the trigger effective bit TEB is outputted, the AND gate G2 generates a H level output and sets a flip-flop FF. When a counter CTR overflows, a hardware trace momentum signal TC is outputted.
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：通过在请求处理条件下从指定的微步指定的时间之后，对指定电路的硬件条件进行采样，轻松获取故障。构成：安装寄存器SLNR，以便在指定的电路被扫描时，可以获得硬件条件的跟踪，并且将检查对象的电路号设置为该寄存器。当从存储器MPM连续读取微程序步骤时，读取触发有效位TEB，通过寄存器OP将其输入到仅一个与门G2。非扫描电路号与设置到寄存器SLNR的电路号一致，然后，比较电路COMP产生一致的输出，当输出触发有效位TEB时，与门G2产生H电平输出，设置一个触发器FF。当计数器CTR溢出时，输出硬件轨迹动量信号TC。

9. 发明专利

JPS6072358A PARITY CHECK SYSTEM 失效
公开(公告)号：JPS6072358A
公开(公告)日：1985-04-24
申请号：JP17971883
申请日：1983-09-28
申请人： FUJITSU LTD
发明人： OGASAWARA SHIGERU
IPC分类号： H03M13/00 , H04L13/00 , H04L29/02
摘要： PURPOSE:To reduce signal lines of interface between a controlling section and a connecting common section by comparing each parity bit held by an address line and a data line in a circuit controlling section and the parity bit from a circuit connecting common section. CONSTITUTION:A communication controlling and processing devide is made up of a communication controlling and processing section PC, circuit controlling section LC, circuit connecting common section LAB, rotary adapter LA and an interface bus B. The parity generate bit of an address line at the time of data transfer just before, the parity generate bit of a data line or the held parity bit is placed from the LAB on the data line after completion of data transfer of read or write and before starting next data transfer under control of a service processor SVP and CPU. Then, the parity bit or generate bit held by the address line is compared with each parity bit sent from the LAB in the LC.

10. 发明专利

JPS59127153A Program loading system 失效
标题翻译：程序加载系统
公开(公告)号：JPS59127153A
公开(公告)日：1984-07-21
申请号：JP22863182
申请日：1982-12-28
申请人： Fujitsu Ltd
发明人： OGASAWARA SHIGERU
IPC分类号： G06F15/177 , G06F9/445 , G06F15/16
CPC分类号： G06F9/445
摘要： PURPOSE:To load simultaneously programs of same contents by connecting these programs to a common bus via plural data processors which sets a memory in a writable state after deciding whether an address is for a program storing memory or not. CONSTITUTION:The signals ai indicating each device through a repeating device are turned on at a time when the programs are loaded to memories MAi which serve as program storing circuits of each device from a service processor. When a comparator 2 detects that the address signal designating a memory MAi1 is on an address signal line, the output of an AND circuit 3 is turned on. Then the write control signal is sent to the memory MAi1 via an OR circuit 4. The data on a write data signal line 6 is written at the address position of the memory MAi1 that is indicated by an address signal line 5. Then the programs can be simultaneously loaded when the signals ai (a1-an) are turned on at a time.
摘要翻译：目的：通过在决定是否存储存储程序的地址之后，将存储器设置为可写状态的多个数据处理器将这些程序连接到公共总线来同时加载相同内容的程序。构成：当将程序从服务处理器加载到作为每个设备的程序存储电路的存储器MAi时，通过重复设备指示每个设备的信号ai被接通。当比较器2检测到指定存储器MAi1的地址信号在地址信号线上时，AND电路3的输出导通。然后，写入控制信号通过OR电路4发送到存储器MAi1。写入数据信号线6上的数据被写入由地址信号线5指示的存储器MAi1的地址位置。然后程序可以当信号ai（a1-a）一次接通时同时加载。

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