专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JPS5713529A PROGRAM LOADING SYSTEM 失效
公开(公告)号：JPS5713529A
公开(公告)日：1982-01-23
申请号：JP8750680
申请日：1980-06-27
申请人： NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO , FUJITSU LTD , HITACHI LTD
发明人： AOYAMA MASAO , TAMADA SHINICHI , GOUHARA MASAO , FURUYA KUNIO
IPC分类号： G06F1/00 , G06F9/445
摘要： PURPOSE:To diminish the number of man-hours for preparing a bootstrap program BSP, by providing a means for freely setting a classification of a program PRG to be loaded, by manual operation, in each control part which is under control of a higher rank prcessing part. CONSTITUTION:A CPU24 which is higher rank processing part is connected to a control part 21 of an external memory control device or a communication control devie, etc., by an interface signal line 25. The control part 21 is provided with a ROM23 in which a BSP is stored, a RAM22 to which a PRG is loaded, and a register 26 which is able to freely set a classification of a program to be loaded newly, by manual operation. When an electric power source is closed to the control part or a start commnad for loading is received from the CPU24, the BSP of the ROM23 starts its operation, and contents which have been set to the register 26 are read out and are informed to the CPU through the signal line 25. The CPU 24 recognizes a classification of the PRG which has been informed, and transfers a related PRG to the control part 21. In this way, since one kind of BSP will do, the number of man-hours for preparing a BSP is diminished.

2. 发明专利

JPS6240561A DATA COMMUNICATION CONTROL DEVICE 失效
公开(公告)号：JPS6240561A
公开(公告)日：1987-02-21
申请号：JP18057185
申请日：1985-08-19
申请人： NEC CORP , NIPPON TELEGRAPH & TELEPHONE
发明人： TAMADA SHINICHI , YORUNO HIDEAKI
IPC分类号： H04L29/10 , G06F13/00 , G06F15/16 , G06F15/177 , H04L13/00 , H04L29/00
摘要： PURPOSE:To shorten the command execution time by executing a left-behind control with regard to only the command processing of an output instruction. CONSTITUTION:A processor 143 detects an input/output instruction receiving display outputted by a bus controlling circuit 142 by a micro-instruction and decodes an output instruction. If the output instruction is a command, the output instruction is ended by driving a ready controlling circuit 145 and applying an end signal to a protocol processing part 130 through a control bus 152. By ending the output instruction, the protocol processing part 130 can execute the next instruction. The contents of the command which is decoded are saved in a memory 144 and the processing of its command is executed. When the command processing is being executed, the output instruction sent out of the protocol processing part 130 is detected and if its output instruction is a command addressed to itself, the output instruction is ended by applying the end signal to the protocol processing part 130 by driving the ready controlling circuit 145 and opening a system bus 150.

3. 发明专利

JPS6225539A PSEUDO FAULT SETTING SYSTEM FOR HIGH SPEED DIGITAL INTERFACE 失效
公开(公告)号：JPS6225539A
公开(公告)日：1987-02-03
申请号：JP16381885
申请日：1985-07-26
申请人： NEC CORP , NIPPON TELEGRAPH & TELEPHONE
发明人： TAMADA SHINICHI , MARUYAMA MASATO
摘要： PURPOSE:To change the content of a pseudo faulty data at every erroneous bit by generating pseudo faulty information corresponding to a faulty bit and setting the pseudo fualty information as the faulty bit of a high speed digital interface. CONSTITUTION:When a transmission command is sent from a host device and a multi-frame data is given to a transmission control circuit 4 via a data bus 1, data are assembled into the data arrangement for the high speed digital interface and the result is led to a channel selection circuit 7. The channel selection circuit 7 selects the data by the control of a counter 6 to send the result to an opposite line. If a data in a frame comes to a faulty bit location at the said transmission, the counter 6 detects the point of time and the channel selection circuit 7 is switched to lead the pseudo fault bit of a pseudo fault setting circuit 5 to an output side by using the output.

4. 发明专利

JPS60254349A CIRCUIT CONTROL DEVICE 失效
公开(公告)号：JPS60254349A
公开(公告)日：1985-12-16
申请号：JP11133884
申请日：1984-05-31
申请人： NIPPON ELECTRIC CO
发明人： TAMADA SHINICHI
IPC分类号： G06F9/22 , G06F13/00 , H04L13/00 , H04L29/02
摘要： PURPOSE:To reduce the number of microinstructions required for the formation of a control word and to shorten a command execution processing time and a circuit processing time by providing a control word constitution part and a microinstruction for the formation of control words. CONSTITUTION:An instruction N is read out from a control storage part storing a microprogram by a microprocessor 1. An address in an address field of the instruction N is supplied to a memory 10 in the control word constitution part 9. The contents of a control word specification field specifying the kinds of trigger code obtained from the memory 10 and a control word in the instruction N and the contents of a register 13 are simultaneously stored in a bus buffer register of a bus control circuit 2 through a selecting circuit 11 to form a control word consisting of 32 bits.

5. 发明专利

JPS5829049A MICROPROCESSOR 失效
公开(公告)号：JPS5829049A
公开(公告)日：1983-02-21
申请号：JP12723581
申请日：1981-08-12
申请人： NIPPON ELECTRIC CO
发明人： TAMADA SHINICHI
IPC分类号： G06F9/22
摘要： PURPOSE:To decrease the load of an output signal, by setting the same two word instruction for two-words' share to a microinstruction register even for one word instruction, in a microprocessor having instructions constituting two-word. CONSTITUTION:When a microinstruction read out from a storage device 1 is short and stored in one microinstruction register MIR, even if the instruction is one word instruction, the instruction is set to both the 1st and 2nd MIR 2 and 3 of a microprocessor at the same time, and bit location of processing field 10 for one word instruction and processing fields 11 and 12 for two word instruction is matched beforehand. Thus, the information output of the processing fields set to the 1st MIR 2 drives the 1st processing circuit 7 and the information output of the processing field set to the 2nd MIR drives the 2nd processing circuit 8.

6. 发明专利

JPS6027942A MICROPROGRAM CONTROL SYSTEM 失效
公开(公告)号：JPS6027942A
公开(公告)日：1985-02-13
申请号：JP13703783
申请日：1983-07-27
申请人： NIPPON ELECTRIC CO
发明人： TAMADA SHINICHI
IPC分类号： G06F9/26 , G06F9/22
摘要： PURPOSE:To increase a processing speed and to reduce storage capacity by switching an ROM for address conversion according to processing contents. CONSTITUTION:A microinstruction from a storage device 1 for control is read out of an instruction register 2 as specified by a register 7, and then executed. When there is a request for processing from a low-priority module 4, a microprogram stores its control information or status information in a holding circuit 10-1 dedicated to address conversion through a data register 3. Further, the control information and status, etc., of a program controller are stored in holding circuits 10-2 and 10-3 dedicated to address converson. Furthermore, the contents of the register 2 are decoded by a decoding circuit 11, and when the decoded contents relate to the ROM9-1, a signal for allowing the ROM9-1 to be read is supplied. The ROM9-1, on the other hand, is supplid with outputs of the holding circuits 10-1-10-3, so address assignment is performed by them and the output of the ROM9-1 is supplied to the storage device 1 for control through an address selecting circuit 5.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式