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1. 发明专利

JPS56110151A COMBINATION SYSTEM ARITHMETIC CIRCUIT 失效
公开(公告)号：JPS56110151A
公开(公告)日：1981-09-01
申请号：JP1279480
申请日：1980-02-05
申请人： NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , NIPPON ELECTRIC CO , HITACHI LTD , FUJITSU LTD
发明人： MIYAGUCHI SHIYOUJI , MIZUTA HIROSHI , MIZUTA MASANORI , FURUYA KUNIO , HIGUCHI TAIHOU
IPC分类号： G09C1/00 , G06F7/72 , G09C1/10
摘要： PURPOSE:To attain a high speed and economical circuit by constituting the circuit mainly of a controlling circuit correcting a multiplying circuit which calculates a temporary remainder, and a temporary remainder, by means of comparison and subtraction of two times. CONSTITUTION:When a data I and a dividend P are input to the multiplication part 10, the product Q2 of P and I is output. This product Q2 is provided to the operation part 20 for omitting fractions, and the value Q1 whose low rank bit has been omitted can be obtained. When this data Q1 and a divisor N are input to the multiplier 30, NXQ1=P1 is output to the signal line. On the other hand, the data P and P1 are input to the subtraction and comparison part 40. The control circuit 43 executes a subtraction P-P1=R1 and outputs it to the shift register 42. Keeping pace with said operation, the circuit 43 inputs the divisor N, and in case of R1>=N, R1-N=R2 is calculated, and it is output to the register 42. Also, in case of R2>=N, the circuit 43 calculates R2-N=R3, and outputs it to the register 42. When R1, R2 or R3 has become smaller than N, keeping pace with said operation, the value R is output onto the signal line 50.

2. 发明专利

JPS5640343A DATA CONVERTING METHOD 失效
公开(公告)号：JPS5640343A
公开(公告)日：1981-04-16
申请号：JP11620279
申请日：1979-09-12
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO , FUJITSU LTD , OKI ELECTRIC IND CO LTD
发明人： FURUYA KUNIO , MIYAGUCHI SHIYOUJI , MIZUTA MASANORI , HIGUCHI TAIHOU , KAWAMURA YASUSUKE
IPC分类号： H04K1/00 , H04L9/06 , H04L9/18
摘要： PURPOSE:To shorten the processing time, by dividing input data into every several bits and by arranging divided input data in arbitrary several bytes respectively and by performing the ciphering processing by the unit of one or more bytes, in data conversion for ciphering. CONSTITUTION:The ordinary writing of 8-byte codes is subjected to the character transfer processing first. Next, input data is divided by four bits successively, and divided four bits are stuffed to the right half of one byte of output data to expand the preceding 8-byte output to double 16 bytes. These 16 bytes are divided into right 8 bytes and left 8 bytes (r0 and l0), and r0 is subjected to the expansion character transfer processing. Meanwhile, 48-bit (6-byte) key is expanded to 8-bytes, and exclusive OR between this key and the output of the expansion transfer processing is operated for every bit. Next, the compressional character conversion processing and the character transfer processing are performed to operate exclusive OR between the key and l0 for every bit. By repeating these processings, the original code is converted to a new code.

3. 发明专利

JPS5642852A MULTIPLICATION*DIVISION CIRCUIT 失效
公开(公告)号：JPS5642852A
公开(公告)日：1981-04-21
申请号：JP11979379
申请日：1979-09-18
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , NIPPON ELECTRIC CO , HITACHI LTD
发明人： HIGUCHI TAIHOU , MIYAGUCHI SHIYOUJI , KAWAMURA YASUSUKE , MIZUTA MASANORI , FURUYA KUNIO
IPC分类号： G06F7/496 , G06F7/507 , G06F7/52 , G06F7/527 , G06F7/72 , G09C1/00 , H04L9/30
摘要： PURPOSE:To ensure an effective operation of ME(MODN), by giving a control to the arithmetic process based on the result of the binary expansion of the power multiplier. CONSTITUTION:The data M, the divisor N and the power multiplier E are stored in the registers 2, 3 and 4 each. And the process is carried out as follows based on the result of the binary expansion of the multiplier E in the register 4. That is, the gate 8 is opened in case the bit is 0 as the result of expansion, and the contents of the register 1 is squared via the multiplier 5. And this result receives a division by the divider 6 and via the contents of the register 3, and the residue thus obtained is stored in the register 1. And in case the bit is 1, the same operation as the bit 0 is carried out. And furthermore the gate 9 is opened to give the multiplication 5 to the contents of the registers 1 and 2 each, and this result is divided 5 by the contents of the register 3 with the residue stored in the register 1. In such way, no repetition is required for the multiplication of the frequency of the power multiplier, thus ensuring an effective operation.

4. 发明专利

JPS5642449A CODER 失效
公开(公告)号：JPS5642449A
公开(公告)日：1981-04-20
申请号：JP11734579
申请日：1979-09-14
申请人： OKI ELECTRIC IND CO LTD , NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO , HITACHI LTD , FUJITSU LTD
发明人： KAWAMURA YASUSUKE , MIYAGUCHI SHIYOUJI , MIZUTA MASANORI , FURUYA KUNIO , HIGUCHI TAIHOU
IPC分类号： H04K1/00 , G09C1/00 , H04L9/00 , H04L9/10 , H04L9/30
摘要： PURPOSE:To make it possible to shorten coding or decoding time by providing a coding or decoding arithmetic part with two modulo calculation parts that include multipliers and dividers and then by putting them in parallel operation. CONSTITUTION:Coder 10 is provided with two modulo calculation parts All and B12, which include multipliers 13a and 13b, registers 14a and 14b stored with results of multipliers 13a and 13b, dividers 15a and 15b outputting only remainders, and registers 16a and 16b. For coding process, the 1st and 2nd key codes (n) and (e) are externally set in the 5th and 7th registers 18 and 20, and data bit block (m) as a coding unit in the 6th register 19. On receiving coding operation indication signal 34 externally, control part 21 sets the contents of register 19 in register 16a and then repeats the modulo calculation from the least significant bit to the most significant bit by the bit length of binary expanded key code (e).

5. 发明专利

JPS5633732A CHARACTER COMPRESSING DEVICE 失效
公开(公告)号：JPS5633732A
公开(公告)日：1981-04-04
申请号：JP10879879
申请日：1979-08-27
申请人： NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , NIPPON ELECTRIC CO , HITACHI LTD , FUJITSU LTD
发明人： HORIGUCHI MASATOSHI , MIYAGUCHI SHIYOUJI , KAWAMURA YASUSUKE , MIZUTA MASANORI , FURUYA KUNIO , HIGUCHI TAIHOU
IPC分类号： H04L23/00 , G06F5/00 , G06F13/00
摘要： PURPOSE:To ensure a high-speed process and then realize an effective use of the external memory device within the system, by securing an independence of the function to give a high-speed compression and restoration to the information composed of the code raw from the process part of the CPU and also realizing the function with the hardware such as the LSI or the like. CONSTITUTION:Receiving the indication for start of the process, the character compressing device 102 reads the unprocessed data within the memory 104 via the memory control part 103 and based on the information given from the process part 101. Then the process indicated in the working mode is applied, and the processed data is written into the prescribed position of the memory 104. This action is given to all data, and an interruption is applied to the part 101 when the process completes. And in case the device 102 gives a process of compression, the part 101 transmits the processed data to the external unit via the communication control part 105. While in case the data received from the external unit is restored, the process restoration is completed by the interruption. In this way, a high-speed process is possible for the character compressing device, thus ensuring an effective use of the external unit in the system.

6. 发明专利

JPS5380928A RENEWAL SYSTEM FOR MEMORY ADDRESS 失效
公开(公告)号：JPS5380928A
公开(公告)日：1978-07-17
申请号：JP15719676
申请日：1976-12-25
申请人： NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO , HITACHI LTD , FUJITSU LTD
发明人： MATSUYAMA TAKAKI , NAGAI SHIYOUTA , YAMASHITA YOSHIAKI , HIGUCHI TAIHOU
IPC分类号： G06F12/04 , G06F12/06 , G06F12/10 , G06F13/12 , G06F13/16
摘要： PURPOSE:To ensure a high-speed address renewal process and the fetch action for the address of the command ward, by setting the address byte boundary of the command ward to 2 byte and the address byte boundary of the command word address to 2 respectively.

7. 发明专利

JPS60173955A LINE INTERFACE CONNECTING SYSTEM 失效
公开(公告)号：JPS60173955A
公开(公告)日：1985-09-07
申请号：JP2902184
申请日：1984-02-17
申请人： FUJITSU LTD
发明人： CHIBA HIDEAKI , HIGUCHI TAIHOU , HANAZAWA AKIO
IPC分类号： H04L29/10 , H04L12/00
摘要： PURPOSE:To decrease the operation disable part produced at a mounting location by changing the address of a line register and a connection device number of a line connecting section to set the communication mode. CONSTITUTION:A connection device number register NRB and a line address register LAR to be set by a supervisory device 3 are provided to line connecting sections #11-#23. A required address is set to the registers NRB and LAR ahead the start of communication. Thus, when the line connecting sections #11- #23 are scanned, both the registers NBR and LAR belonging to each are checked and a data on a common bus 2 is fetched to the own line connection sections #11-#23 and the data is transmitted to connected communication lines 4-9 or the data from the communication lines 4-9 is transmitted to the common bus 2. The communication mode like this is set and changed freely by changing the address of both the registers NBR and LAR.

8. 发明专利

JPS5888941A OUTPUT CONTROLLING SYSTEM 失效
公开(公告)号：JPS5888941A
公开(公告)日：1983-05-27
申请号：JP18651281
申请日：1981-11-20
申请人： FUJITSU LTD
发明人： INOUE YUKINORI , MITA TERUYOSHI , HIGUCHI TAIHOU
IPC分类号： H04B10/572 , H04B10/00 , H04B10/07 , H04B10/27 , H04B10/275 , H04B10/29 , H04B10/293 , H04B10/564 , H04L12/42
摘要： PURPOSE:To eliminate the need for level adjustment at the reception side, by measuring the photodetecting level of an optical signal from a transmission side node and controlling the output level of a transmitted optical signal from the transmitted node through the return of the result of measurement from the reception side to the transmission side, in an optical communication system. CONSTITUTION:Nodes 1-3 storing a plurality of terminal devices 7 are connected in ring shape by optical transmission lines 4-6 with an otical communication system, and a control code transmitted in the form of packet consists of a transmission number and information D discriminating a transmitted node from an incoming number DA and a transmission node from a terminal device. At the node 2, an optial signal L from the node 1 is converted into an electric signal at a photodetection section 11 and transmitted to a branch section 12, the photodetection level is measured, the esult LV is given to an encoding section 18 to detect whether or not the level is within the permissible range for encoding. Its code RL is assembled in a packet at a packet assembling section 15 and transmitted from an optical transmission section 17 to a transmission line. This is received at the node 1, an output control signal LC is sent to the section 17 based on the code RL to control the output level of the optical signal L.

9. 发明专利

JPS5854429A REMOTE CHANNEL SYSTEM IN DATA PROCESSING SYSTEM 失效
公开(公告)号：JPS5854429A
公开(公告)日：1983-03-31
申请号：JP15251881
申请日：1981-09-25
申请人： FUJITSU LTD
发明人： HIGUCHI TAIHOU , MITA TERUYOSHI
IPC分类号： G06F13/38 , G06F13/12
摘要： PURPOSE:To freely extend the distance of a cable independently of the number of signal lines of the cable, by enabling plural host processing units to use files in common, and using a bit serial transmission line. CONSTITUTION:An I/O instruction from a host processing unit 1 is set up in a register 14. The instruction is sent to a channel control word processing part 22 through conversion circuits 17, 16, so that channel control word existence address information is set up in a register 20 and transferred to a register 10 through conversion circuits 18, 15. Consequently a main memory is accessed and a channel control word is read out from the main memory and transferred to the channel control word processing part 22 through the conversion circuits 17, 16.

10. 发明专利

JPS56169457A LINE ADDRESS CONTROLLING SYSTEM 失效
公开(公告)号：JPS56169457A
公开(公告)日：1981-12-26
申请号：JP7224180
申请日：1980-05-30
申请人： FUJITSU LTD
发明人： HIWATARI AKITO , HIGUCHI TAIHOU , HANAZAWA AKIO
IPC分类号： H04L5/14 , H04L1/24 , H04L29/04
摘要： PURPOSE:To perform the folded test without making the replacing operation of MODEM cable, by enabling the full duplex operation even to any line, by distinguishing one address into transmission and reception at semidouplex communication. CONSTITUTION:At semiduplex communication, DPXN (the N-th line full duplex mode) and DPXN+1 are both off, and an address N is assigned to an S address N and an R address N with an address switching line 5, and an address N+1 is assigned to an S address N+1 and an R address N+1 with the address switching section 2 similarly for semiduplex operation. When the signal DPXN indicating the full duplex operation is fed from the section 2 to the line number N, the address N is assigned to the S address N in the circuit 5 and no address is given to the S address N+1. Thus, the full duplex operation is made to an MODEM 3 of the line number N to constitute the folded loop at the failure.

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