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1. 发明专利

JP2003243527A MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：JP2003243527A
公开(公告)日：2003-08-29
申请号：JP2002038430
申请日：2002-02-15
申请人： HITACHI LTD
发明人： KUROKAWA ATSUSHI , KITAHARA TOSHIAKI , INAGAWA HIROMI , IMAMURA YOSHINORI
IPC分类号： H01L29/872 , H01L21/3205 , H01L21/329 , H01L21/331 , H01L21/822 , H01L21/8222 , H01L23/52 , H01L27/04 , H01L27/06 , H01L29/47 , H01L29/737
摘要： PROBLEM TO BE SOLVED: To improve the yield of a semiconductor device and reduce its manufacturing cost, in the manufacturing method of the semiconductor device having a heterojunction bipolar transistor (HBT), a Schottky diode, and a resistance element. SOLUTION: In the manufacturing method of the semiconductor device, after successively forming respective semiconductor layers to become a collector layer, a base layer, a wide-gap emitter layer, and an emitter layer on the surface of a semiconductor substrate, the respective semiconductor layers are so processed respectively as to form the heterojunction bipolar transistor, the Schottky diode, and the resistor element in a monolithic way. In this case, the emitter electrode of the HBT, the Schottky electrode of the Schottky diode, and the resistance film of the resistance element are concurrently formed of the same material (e.g. WSiN). Consequently, the number of the processes of the semiconductor device is reduced, to reduce its manufacturing cost. COPYRIGHT: (C)2003,JPO

2. 发明专利

JP2514948B2 失效
公开(公告)号：JP2514948B2
公开(公告)日：1996-07-10
申请号：JP4024387
申请日：1987-02-25
申请人： HITACHI LTD
发明人： GOSHIMA SHIGEO , USAGAWA TOSHUKI , IMAMURA YOSHINORI
IPC分类号： H01L21/28 , H01L21/338 , H01L29/43 , H01L29/778 , H01L29/80 , H01L29/812

3. 发明专利

JPH07283201A DRY ETCHING METHOD 失效
公开(公告)号：JPH07283201A
公开(公告)日：1995-10-27
申请号：JP6924294
申请日：1994-04-07
申请人： HITACHI LTD
发明人： UCHIYAMA HIROYUKI , IMAMURA YOSHINORI
IPC分类号： C23F4/00 , H01L21/302 , H01L21/3065
摘要： PURPOSE:To accomplish equal speed, anisotropic and smooth processed surface of a semiconductor multilayer film by a method wherein, an etching treatment is conducted using CH4 mixed gas, as reaction gas, of specific mixing ratio which is mixed at specific mixing ratio and reacted at specific pressure. CONSTITUTION:A compound semiconductor structure, composed of an emitter cap 2, an emitter 3, a base 4, a collector 5 and a subcollector 6, is etched from the emitter cap 2 to the emitter 3 using an emitter electrode 1 as a mask. CH4 mixed gas is used as reaction gas. The mixing ratio of CH4 is set at 60 to 85%. Desirably, the Cl2 and CH4 mixed gas of mixing ratio of 70 to 80% is used. The pressure of reaction is 2.0mToor or lower, or desirably 0.1 to 0.5mTorr. As a result, equal speed and anisotropic etching can be conducted on the compound semiconductor multilayer film of InP, InAlAs, InGaAs and the like.

4. 发明专利

JPH0677255A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH0677255A
公开(公告)日：1994-03-18
申请号：JP22383992
申请日：1992-08-24
申请人： HITACHI LTD
发明人： MORI MITSUHIRO , IMAMURA YOSHINORI , TANIMOTO TAKUMA , KUDO MAKOTO , NAKAJIMA AKISHIGE , KUSANO CHUSHIRO
IPC分类号： H01L29/812 , H01L21/338
摘要： PURPOSE:To enable an offset gate electrode where a gate and a drain can be optionally set in distance between them to be formed excellent in reproducibility through a self-alignment technique by a method wherein the recess of a semiconductor layer is covered with an insulating film whose side face is larger than its surface in etching rate, a resist opening is provided to the shoulder of a mesa of a semiconductor layer, and then an etching process is carried out. CONSTITUTION:A source electrode 14 and a drain electrode 15 are formed on a high concentration impurity doped layer 13, a part of the doped layer 13 located between the electrodes 14 and 15 is removed off to form a recess 16. An insulating film 17 whose side face is larger than its surface in etching rate is formed on all the surface of a wafer to cover the recess 16, and an opening of a resist 18 is provided to the mesa shoulder of the high concentration impurity doped layer 13 on the source electrode 14 side. Then, only the side wall 17 of the insulating film 17 is etched, and a gate electrode 19 is formed through the opening of a photoresist 18. For instance, the insulating film 17 whose side wall 17' is high in etching rate is formed of plasma SiN or the like deposited through an ECR plasma CVD method.

5. 发明专利

JPH0469436B2 失效
公开(公告)号：JPH0469436B2
公开(公告)日：1992-11-06
申请号：JP21618683
申请日：1983-11-18
申请人： HITACHI LTD
发明人： MARUYAMA EIICHI , IMAMURA YOSHINORI , ADAKA SABURO , INAO KYOHISA , TAKASAKI YUKIO , TSUKADA TOSHIHISA , HIRAI TADAAKI
IPC分类号： H01J29/45 , H01L27/146 , H01L31/0248 , H01L31/0264 , H01L31/09 , H01L31/20 , H04N5/335 , H04N5/361 , H04N5/369

6. 发明专利

JPH04123428A DRYETCHING METHOD 失效
公开(公告)号：JPH04123428A
公开(公告)日：1992-04-23
申请号：JP24234290
申请日：1990-09-14
申请人： HITACHI LTD
发明人： UCHIYAMA HIROYUKI , MORI MITSUHIRO , IMAMURA YOSHINORI
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/338 , H01L29/812
摘要： PURPOSE:To make a high-speed work with a very small amount of side etching and a smooth surface of etching by etching a compound semiconductor with SiCl4 gas as the etching gas by microwave plasma etching. CONSTITUTION:A GaAs-FET element consisting of a gate electrode 11 tungsten silicide deposited by the source-drain sputtering of an n-type active layer 10 selectively grown on a semiinsulating GaAs substrate 1. A photoresist 2 and an SiO2 3 serving as the etching mask are produced by interelement isolation by recess etching with the etching gas of SiCl4 gas of high effect in supplying chlorine ions in low pressure through microwave plasma etching easy of ion energy control. This process minimizes the side etching amount and smoothens the etching surface. This dryetching method can be applied for other compound semiconductors (e.g. InP, InAs, AlAs, or these mixed crystals) as well.

7. 发明专利

JPH01166541A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH01166541A
公开(公告)日：1989-06-30
申请号：JP32399287
申请日：1987-12-23
申请人： HITACHI LTD
发明人： YANAGISAWA HIROSHI , MIYAZAKI MASARU , SHIGETA JUNJI , MATSUNAGA NOBUTOSHI , IMAMURA YOSHINORI
IPC分类号： H01L21/3205 , H01L21/31 , H01L21/768 , H01L23/52 , H01L23/522
摘要： PURPOSE:To obtain the mechanical strength of metal wirings without increasing its parasitic capacitance by forming a thin film on the upside of the wiring to reinforce it. CONSTITUTION:After a whole element is covered with an SiO2 film 105, it is coated with photoresist, and etched to selectively remove the film 105 at a predetermined position on a source electrode 103. Then, the whole face is covered with metal wirings 107 made of a 3-layer structure of M-Au-Mo. Thereafter, a predetermined wiring pattern is formed of a thin boron nitride film 108, selectively processed thereby to complete metal wirings. Thereafter, the photoresist used to form the pattern of the metal wirings and the film 105 is removed by ashing, thereby forming air bridge wirings having a cavity 106. Accordingly, a mechanical strength is strengthened by the film 108, and the metal wiring of a thin film can be supported in the air without increasing its parasitic capacitance.

8. 发明专利

JPS62200771A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPS62200771A
公开(公告)日：1987-09-04
申请号：JP4176886
申请日：1986-02-28
申请人： HITACHI LTD
发明人： USAGAWA TOSHIYUKI , IMAMURA YOSHINORI , KOBAYASHI MASAYOSHI , OKUDAIRA HIDEKAZU , GOSHIMA SHIGEO
IPC分类号： H01L29/812 , H01L21/338 , H01L29/778 , H01L29/80
摘要： PURPOSE:To reduce parasitic resistance, to prevent the deterioration of voltage resistance of a gate and, moreover, to check an increase in gate capacity, by forming a gate electrode only in a part wherefrom a high concentration layer is removed, so that it is separated by an insulator from the high concentration layer formed on the upper side of an active layer. CONSTITUTION:A gate electrode 1 connecting to an active layer 12 of a field effect transistor is formed only in a part wherefrom a high concentration layer 13 is removed, so that it is separated by an insulator 4 from the high concentration layer 13 formed on the upper side of the active layer 12. When this method is applied to GaAs MESFET, for instance, the insulator 4 is formed only on the lateral wall of an N GaAs cap layer 13, and a gate metal 1 is formed only inside a recess structure. Between the N GaAs layer 13 and the gate metal 1, according to this method, there is only a parasitic resistance in an opened portion set by the film thickness of the lateral wall 4 of the insulator, and since this resistance is very small, no increase in parasitic resistance occurs. Moreover, there is no deterioration in the voltage resistance of a gate, since the gate metal 1 and the N GaAs layer 13 are separated from each other by the side wall insulator 4. In addition, there is also no increase in a source-gate capacity, since the gate metal is formed only inside the recess structure.

9. 发明专利

JPS6292327A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPS6292327A
公开(公告)日：1987-04-27
申请号：JP23122885
申请日：1985-10-18
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： GOSHIMA SHIGEO , IMAMURA YOSHINORI , MASUKI JIYUNJI , ISOBE YOSHIHIKO , MIYAZAKI MASARU
IPC分类号： H01L29/812 , H01L21/314 , H01L21/318 , H01L21/338 , H01L29/80
摘要： PURPOSE:To prevent contamination on ion implantation and deterioration caused by a knock-on effect by implanting ions, penetrating an insulating film consisting of an AlN film, laminating a protective film composed of SiN onto the AlN film and thermally treating the whole. CONSTITUTION:An AlN film 14 is applied onto a GaAs substrate 1. Ions are implanted in order to form a source region 3 and a drain region 4, using a photo-resist 8 as a mask. A photo-resist mask 8' is removed completely, and an SiN film 14' is laminated. The whole is thermally treated in hydrogen. The SiN film 14' is etched through dry etching employing a fluorine group gas, using a photo-resist 8'' as a mask, and the AlN film 14 is etched in a wet type by H3PO4. Source-drain electrode materials 15, 15', 15'' are evaporated, and the SiN film 14' is etched through a dry etching method and the AlN film 14 through wet type etching respectively, employing the photo-resist 8'' as the mask. Accordingly, contamination on ion implantation and deterioration caused by a knock-on effect are prevented.

10. 发明专利

JPS612230A MANUFACTURE OF IMAGE PICKUP DEVICE 失效
公开(公告)号：JPS612230A
公开(公告)日：1986-01-08
申请号：JP12172284
申请日：1984-06-15
申请人： HITACHI LTD
发明人： ISHIOKA YOSHIO , IMAMURA YOSHINORI , SHIMOMOTO TAIJI , OGAWA HIROBUMI , HIRAI TADAAKI
IPC分类号： H01J9/233 , H01L31/0248 , H01L31/08
摘要： PURPOSE:To reduce an after-image by heat-treating the photoconductive target of an image pickup tube after manufacturing it. CONSTITUTION:A glass faceplate 1 on which a transparent conductive layer 2 such as tin oxide film is provided is installed in a sputtering device and an SiO2 layer 3 and then non-crystalline silicon 4 are accumulated, thereon. Then, a photoconductive target section is manufactured by accumulating porous antimony trioxide through vacuum evaporation under inert gas atmosphere. An image pickup tube is completed by heat-treating this faceplate under vaccuum at 200 deg.C for 30min and the incorporating it in the tube. As a resutls, an after-image value is reduced to less than half as compared with the case where heat treatment is not applied and a significant after-image reduction effect can be obtained.

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