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1. 发明专利

JPH08181605A PHASE CONTROL CIRCUIT 失效
公开(公告)号：JPH08181605A
公开(公告)日：1996-07-12
申请号：JP33737494
申请日：1994-12-26
申请人： HITACHI LTD , HITACHI VIDEO IND INF SYST INC , HITACHI MICROCOMPUTER SYST
发明人： SASAKI MASAHIRO , FURUHATA MAKOTO , YAMAMOTO MOROHISA
IPC分类号： H04N5/92 , H03B5/32 , H03L7/099
摘要： PURPOSE: To make phase control stable by giving an output of a variable adder circuit whose plural input terminals receive an output signal of a subtractor circuit or an amplitude reduction circuit to an amplifier circuit so as to eliminate harmonics of an oscillating frequency. CONSTITUTION: One and other terminals of a resonance circuit RES1 provided to an external part are connected respectively to external terminals T0 , T1 and an input terminal of a band limit circuit BWC1 is substantially coupled with the terminals T0 , T1 . The phase control circuit is provided with a phase shift circuit PTR1 whose input terminal receives an output signal of the circuit BWC1, an amplitude reduction circuit ADC1, a subtractor circuit SUB1, a variable adder circuit VAD1, and an amplifier circuit AMP1. An output signal of the circuit PTR1 is given to an inverting input terminal (-) of the circuit SUB 1 and an output signal of the circuit ADC1 is given to its noninverting terminal (+). Furthermore, respective terminals of the circuit VAD1 receive outputs from the circuits SUB1, ADC1 and the result of the sum is given to the circuit AMP coupled with the terminals T0 , T1 . After the signal is amplified in the circuit AMP, from which the amplified signal is fed to a circuit RES1.

2. 发明专利

JPH0846986A AMPLITUDE LIMITER CIRCUIT 失效
公开(公告)号：JPH0846986A
公开(公告)日：1996-02-16
申请号：JP19489094
申请日：1994-07-27
申请人： HITACHI LTD , HITACHI VIDEO IND INF SYST INC , HITACHI MICROCOMPUTER SYST
发明人： SASAKI MASAHIRO , YAMAMOTO MOROHISA , NAKAGAWA TADASHI , TAKEBUCHI KENJI , TANABE HISANORI , ARAI IZUMI , KURIHARA TAKASHI , KASHIYA HIDEO
IPC分类号： H04N9/793 , H03G3/30 , H04N9/68
摘要： PURPOSE:To improve response to the variation of an input signal and to reduce and stabilize flickering at a transient time in processing a picture by adding linearity to a voltage signal for gain control so as to make a gain characteristic have linearity in over wide range. CONSTITUTION:After the input control voltage 4 of a smoothed color burst signal are converted into the current signals 5 and 6 of mutually opposite phases by a voltage-to-current converting circuit, the current signals 5 and 6 are converted into voltage signals 7 and 8 by a current-to-voltage converting circuit 2. The voltage signals 7 and 8 are logarithmic-compressed by respective diodes 13 and 14 and the signal 8 is made a voltage signal added with linearity by a prescribed resistor R1. The signals 7 and 8 are provided to the respective bases of balanced differential transistors Q2, Q3 and Q1, Q4, and the current signals of mutually opposite phases are provided to respective emitters 9 and 10 to obtain output current 12 and 13 which are gain-controlled. It is possible to make the gain characteristic with respect to control voltage have linearity over a wide range adding linearity to the signal 8 by the resistor R1 like this.

3. 发明专利

JPH098557A FREQUENCY DISCRIMINATING CIRCUIT 失效
公开(公告)号：JPH098557A
公开(公告)日：1997-01-10
申请号：JP14924395
申请日：1995-06-15
申请人： HITACHI LTD , HITACHI MICROCOMPUTER SYST
发明人： KANESHIRO KATSUMI , NAKAGAWA TADASHI , TAKEBUCHI KENJI , HORI HIROYUKI , YAMAMOTO MOROHISA
IPC分类号： H03D13/00
摘要： PURPOSE: To unnecessitate a phase shift circuit and to discriminate the frequency of an input signal with high accuracy without receiving effect of the dispersion in elements so much by converting the frequency of the input signal to acquire a voltage regardless of phase and making it possible to discriminate the frequency. CONSTITUTION: This circuit is provided with a first pulse generation circuit 1 forming a first pulse having the width corresponding to the frequency of an input signal V1 for each fixed period and a second pulse generation circuit 2 forming a second pulse having the width corresponding to the frequency of a reference signal V2 for each fixed period. The circuit is provided with capacity C1 to be charged or discharged by constant current for a first pulse period and to be charged or discharged by constant current for a second pulse period. Namely, the constant current charge (or discharge) of the capacity C1 is performed for the first pulse period, the constant current discharge (or charge) of the capacity C1 is performed for the second pulse period and the potential of the capacity C1 is taken out as the frequency discriminating output of an input signal V1.

4. 发明专利

JPH09130237A PLL CIRCUIT AND TRANSFER DATA SIGNAL PROCESSOR 失效
公开(公告)号：JPH09130237A
公开(公告)日：1997-05-16
申请号：JP27909395
申请日：1995-10-26
申请人： HITACHI LTD , HITACHI MICROCOMPUTER SYST , HITACHI TOBU SEMICONDUCTOR LTD
发明人： YAMAMOTO MOROHISA , FURUHATA MAKOTO , YAMAUCHI KIYONARI , JIN TAKASHI
IPC分类号： G06F1/12 , H03L7/087 , H03M1/12
摘要： PROBLEM TO BE SOLVED: To provide a PLL circuit capable of high-speed pull-in for the pull-in response of skewness and the pull-in response from a free-running oscillation state and to perform the A/D conversion processing of video signals and a character addition processing using it. SOLUTION: The output signals of a variable oscillator 101 oscillated by the frequency of N-fold of reference signals are frequency-divided to the frequency of L-fold (L

5. 发明专利

JPH09130166A CMOS DIFFERENTIAL AMPLIFIER CIRCUIT 失效
公开(公告)号：JPH09130166A
公开(公告)日：1997-05-16
申请号：JP27909495
申请日：1995-10-26
申请人： HITACHI LTD , HITACHI MICROCOMPUTER SYST
发明人： NACHI SHIKIKO , YAMAMOTO MOROHISA , NAKAUCHI ATSUHIKO , SUGANUMA MASANORI
IPC分类号： H03F3/45
摘要： PROBLEM TO BE SOLVED: To reduce the changes of both gain and phase frequency characteristics and to secure the satisfactory DG(differential gain) and DP(differential phase) characteristics by regulating the larger one of both currents amplified by a 1st or 3rd current mirror circuit by the other smaller current. SOLUTION: When a pair of input signals V (+) and V (-) are set at the same level, the voltage of the same level as these input signals is outputted to an output terminal OUT. If the potential of the signal V (+) rises under such conditions, the current I1 flowing to a MOS transistor TR MN9 increases and the current I2 flowing to a TR MN10 reduces. Therefore, the gate voltage of a MOS TR MP7 placed at the output side of a 1st current mirror circuit 23 rises to try to increase the drain current of the TR MP7. Thus the on- resistance of the TR MP7 reduces. Then the gate voltage of a MOS TR MN13 of a 3rd current mirror circuit 24 drops to try to reduce the drain current of the TR MN13. Thus the on-resistance of the TR MN13 increases. As a result, the output voltage rises.

6. 发明专利

JPH1022794A CURRENT CONTROL SYSTEM RING OSCILLATOR AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE USING IT 失效
公开(公告)号：JPH1022794A
公开(公告)日：1998-01-23
申请号：JP17082496
申请日：1996-07-01
申请人： HITACHI LTD , HITACHI MICROCOMPUTER SYST
发明人： NACHI SHIKIKO , YAMAMOTO MOROHISA
IPC分类号： H03K3/354 , H03L7/099
摘要： PROBLEM TO BE SOLVED: To provide the current control system ring oscillator in which the characteristic of an oscillator of a phase locked loop(PLL) using a complementary metal oxide semiconductor(CMOS) device used for a digital signal processing function and a high speed operation microcomputer or the like is improved. SOLUTION: The oscillator is a ring oscillator configured by connecting a plurality of stages of delay circuits in cascade, each delay circuit is made up of a CMOS differential amplifier circuit, which comprising a differential amplifier circuit 1 consisting of a couple of MOS TRs, an active load circuit 2 consisting of a couple of MOS TRs, and current sources CS1-CS3 each consisting of a MOS TR, and output terminals OUT1, OUT2 are configured so that they change invertingly/noninvertingly with respect to a DC voltage change at an input terminal IN1 and they change noninvertingly/invertingly with respect to a DC voltage change at an input terminal IN2 and the oscillated frequency is controlled by controlling a current I1 of the current source CS1 and a current I2 of the current sources CS2, CS3.

7. 发明专利

JPH0818919A FM MODULATION CIRCUIT 失效
公开(公告)号：JPH0818919A
公开(公告)日：1996-01-19
申请号：JP16904894
申请日：1994-06-28
申请人： HITACHI LTD , HITACHI MICROCOMPUTER SYST , VICTOR COMPANY OF JAPAN
发明人： KANESHIRO KATSUMI , YAMAMOTO MOROHISA , NAKAGAWA TADASHI , TAKEBUCHI KENJI , HORI HIROYUKI , HORI NOBUO , TANIDA YASUYUKI
IPC分类号： H04N5/922 , H03C3/09
摘要： PURPOSE:To obtain the FM modulation circuit in which an FM carrier frequency and an FM deviation are adjusted automatically with high accuracy and excellent reproduction performance, number of external terminals and external components is reduced and no-adjustment is realized. CONSTITUTION:A voltage clamping circuit 1 and an amplitude control circuit 2 make a peak level of a synchronizing signal in a video signal match with a 1st reference potential and a pedestal level match with a 2nd reference potential, and a DC current corresponding to the carrier frequency is formed by applying a reference voltage corresponding to a clamp voltage of a voltage clamp circuit 6 to a 1st resistive element. An output signal via the voltage clamping circuit 1 and the amplitude control circuit 2 is fed to a 2nd resistive element to generate an AC current corresponding to a luminance signal and the DC current and the AC current are fed to an oscillation circuit 8 via a current variable circuit 7 as a frequency control signal. Then a capacitor is charged or discharged by a 1st constant current for a 1st pulse period for an oscillation signal corresponding to a synchronizing signal period.

8. 发明专利

JPH1155588A VIDEO SIGNAL LINE COUNTER CONTROL CIRCUIT AND VIDEO SIGNAL PROCESSOR 失效
公开(公告)号：JPH1155588A
公开(公告)日：1999-02-26
申请号：JP21431497
申请日：1997-08-08
申请人： HITACHI LTD , HITACHI MICROCOMPUTER SYST
发明人： NACHI SHIKIKO , SUGANUMA MASANORI , UCHIYAMA KATSUMASA , TAKAHASHI FUMIHIRO , YAMAMOTO MOROHISA
IPC分类号： H04N5/06 , H04N5/10 , H04N5/445 , H04N7/025 , H04N7/03 , H04N7/035
摘要： PROBLEM TO BE SOLVED: To prevent a count by a video signal line counter value from being incorrectly counted. SOLUTION: The video signal line counter control circuit 50 to control the operation of a video signal line counter based on a composite synchronizing signal is provided with a vertical synchronizing separator circuit 55 that obtains a vertical synchronizing signal for a vertical fly-back period from a received composite synchronizing signal and with a trailing ridge pulse generating circuit 52 that generates a signal to reset the video signal line counter based on the trailing ridge of the vertical synchronizing signal obtained from the vertical synchronizing separator circuit. Even when a video signal in a weak electric field strength or a video signal at special reproduction is received by a television receiver, a longitudinal shake of displayed characters is reduced by using a trailing edge that is comparatively more stable than a leading edge of the vertical synchronizing signal so as to avoid delay in the detection of the vertical synchronizing signal V.

9. 发明专利

JPH07297644A FREQUENCY CONVERSION CIRCUIT 失效
公开(公告)号：JPH07297644A
公开(公告)日：1995-11-10
申请号：JP8875194
申请日：1994-04-26
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： KURIHARA TAKASHI , ARAI IZUMI , KURABAYASHI NAOKI , YAMAMOTO MOROHISA , FURUHATA MAKOTO
IPC分类号： H04N9/83 , H03C1/54
摘要： PURPOSE:To extremely reduce the leakage frequency component without preventing the construction of a semiconductor integrated circuit and its cost reduction. CONSTITUTION:When the input frequency f1 is converted into f2+ or -f1 by the conversion frequency f2, an input signal is divided into a positive phase one and a negative phase one/and transmitted by the use of two-transmission circuits. These two transmission outputs are alternately switched and connected to an output terminal synchronously with the frequency f2. At the same time, the connection is alternately switched synchronously with the frequency f2 between two bias circuits which sets the output bias levels of two transmission circuits respectively and these transmission circuits. Therefore the voltage set by the same bias circuit always emerges at each output terminal regardless of the conversion signal. Then the influence due to the variability caused between both bias circuits can be eliminated.

10. 发明专利

JPH06153230A COLOR SIGNAL LOW FREQUENCY CONVERSION CIRCUIT 失效
公开(公告)号：JPH06153230A
公开(公告)日：1994-05-31
申请号：JP31666492
申请日：1992-10-31
申请人： VICTOR COMPANY OF JAPAN , HITACHI MICOM SYST KK , HITACHI LTD
发明人： TONAMI JUNICHIRO , UBUKATA NORIO , YAMAMOTO MOROHISA
IPC分类号： H03L7/113 , F02B75/02 , H04N9/83 , H04N9/89
摘要： PURPOSE:To quickly lock a PLL generating a reference local signal for color signal low frequency conversion. CONSTITUTION:In the case of n=1, a multiplier 14 multiplies a signal fSC supplied from a crystal LOSC 10 with a reference local signal fC and an LPF 16 extracts a 40fH component from the multiplied signal. Since one horizontal period of this signal includes 40 cycles, and the oscillation control of a VCO 24 by an error signal from a phase detection circuit 18 is finished for 1/2 cycle, that is, for a time nearly 1/80 of one horizontal period and the PLL is locked with a reference local signal. In this case, since the lock frequency of the PLL is locked to a side point deviated by m-cycle (m=1, 2, 3,...) with respect to a frequency of the reference local signal, a discriminator 22 controls the oscillating frequency of the VCO 24 within a prescribed range.

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