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1. 发明专利

JPH0818919A FM MODULATION CIRCUIT 失效
公开(公告)号：JPH0818919A
公开(公告)日：1996-01-19
申请号：JP16904894
申请日：1994-06-28
申请人： HITACHI LTD , HITACHI MICROCOMPUTER SYST , VICTOR COMPANY OF JAPAN
发明人： KANESHIRO KATSUMI , YAMAMOTO MOROHISA , NAKAGAWA TADASHI , TAKEBUCHI KENJI , HORI HIROYUKI , HORI NOBUO , TANIDA YASUYUKI
IPC分类号： H04N5/922 , H03C3/09
摘要： PURPOSE:To obtain the FM modulation circuit in which an FM carrier frequency and an FM deviation are adjusted automatically with high accuracy and excellent reproduction performance, number of external terminals and external components is reduced and no-adjustment is realized. CONSTITUTION:A voltage clamping circuit 1 and an amplitude control circuit 2 make a peak level of a synchronizing signal in a video signal match with a 1st reference potential and a pedestal level match with a 2nd reference potential, and a DC current corresponding to the carrier frequency is formed by applying a reference voltage corresponding to a clamp voltage of a voltage clamp circuit 6 to a 1st resistive element. An output signal via the voltage clamping circuit 1 and the amplitude control circuit 2 is fed to a 2nd resistive element to generate an AC current corresponding to a luminance signal and the DC current and the AC current are fed to an oscillation circuit 8 via a current variable circuit 7 as a frequency control signal. Then a capacitor is charged or discharged by a 1st constant current for a 1st pulse period for an oscillation signal corresponding to a synchronizing signal period.

2. 发明专利

JPH098557A FREQUENCY DISCRIMINATING CIRCUIT 失效
公开(公告)号：JPH098557A
公开(公告)日：1997-01-10
申请号：JP14924395
申请日：1995-06-15
申请人： HITACHI LTD , HITACHI MICROCOMPUTER SYST
发明人： KANESHIRO KATSUMI , NAKAGAWA TADASHI , TAKEBUCHI KENJI , HORI HIROYUKI , YAMAMOTO MOROHISA
IPC分类号： H03D13/00
摘要： PURPOSE: To unnecessitate a phase shift circuit and to discriminate the frequency of an input signal with high accuracy without receiving effect of the dispersion in elements so much by converting the frequency of the input signal to acquire a voltage regardless of phase and making it possible to discriminate the frequency. CONSTITUTION: This circuit is provided with a first pulse generation circuit 1 forming a first pulse having the width corresponding to the frequency of an input signal V1 for each fixed period and a second pulse generation circuit 2 forming a second pulse having the width corresponding to the frequency of a reference signal V2 for each fixed period. The circuit is provided with capacity C1 to be charged or discharged by constant current for a first pulse period and to be charged or discharged by constant current for a second pulse period. Namely, the constant current charge (or discharge) of the capacity C1 is performed for the first pulse period, the constant current discharge (or charge) of the capacity C1 is performed for the second pulse period and the potential of the capacity C1 is taken out as the frequency discriminating output of an input signal V1.

3. 发明专利

JPH10243338A VIDEO RECORDING SYSTEM 失效
公开(公告)号：JPH10243338A
公开(公告)日：1998-09-11
申请号：JP4226897
申请日：1997-02-26
申请人： HITACHI LTD , HITACHI CHIYOU LSI SYS KK
发明人： TAKEBUCHI KENJI , KANESHIRO KATSUMI , KURIHARA TAKASHI , ICHIKAWA YOSHIHISA
IPC分类号： H04N5/91
摘要： PROBLEM TO BE SOLVED: To inhibit normal recording of a video signal processed by a copy prevention device and to secure normal recording of a video signal not processed by the copy prevention device excluding the malfunction of copy guard by detecting a peak level only in a specific period for superposing a copy guard signal to the video signal. SOLUTION: A peak value type AGC circuit 11 detects a peak level obtained immediately after temporarily allowing the instantaneous level of a video signal Vs2 of which period pulse top is DC clamped to a reference level VCL to fall to the reference level VCL and restricts the amplitude of the video signal Vs2 so that the peak level is less than the prescribed limit level V1 of the reference level VCL. A recording circuit 23 records the video signal of which amplitude is limited by the AGC circuit 11 in a recording medium. A timing control means allows the AGC circuit 11 to detect the peak level only to a specific period for superposing a copy guard signal to the video signal Vs2.

4. 发明专利

JPH06197309A FM MODULATOR 失效
公开(公告)号：JPH06197309A
公开(公告)日：1994-07-15
申请号：JP34721592
申请日：1992-12-25
申请人： HITACHI LTD , HITACHI MICOM SYST KK
发明人： YAMAMOTO MOROHISA , NAKAGAWA TADASHI , TAKEBUCHI KENJI , KANESHIRO KATSUMI
IPC分类号： H03C3/06 , H04N5/92 , H04N5/922
摘要： PURPOSE:To adjust an FM carrier frequency and a frequency transition automatically with high accuracy and excellent reproducibility by applying feedback control to a modulation input level so that a ratio of an FM carrier period and a subcarrier period of a chrominance carrier signal is a prescribed expected value. CONSTITUTION:When an FM carrier frequency in a synchronization period is higher than an object frequency fco, a 1st pulse width TW1 being a reciprocal to the FM signal is decreased and then a charged charge quantity in a capacitor Ca is decreased more than a discharged charge quantity and a level control voltage Va extracted from a terminal of the capacitor Ca is decreased. Thus, the level control voltage Va of a level variable circuit 13 is varied in response to the FM carrier frequency for a horizontal synchronizing signal period and a level of an input radio wave Tin to an FM modulation oscillator 141 is varied by the control voltage Va, then a feedback control loop to set the FM carrier frequency for the horizontal synchronizing signal period is an object frequency fsc is formed.

5. 发明专利

JPH10276394A VIDEO SIGNAL RECORDING CIRCUIT 失效
公开(公告)号：JPH10276394A
公开(公告)日：1998-10-13
申请号：JP7600697
申请日：1997-03-27
申请人： HITACHI LTD , HITACHI CHIYOU LSI SYS KK , HITACHI VIDEO IND INF SYST INC
发明人： TAKEBUCHI KENJI , KANESHIRO KATSUMI , ICHIKAWA YOSHIHISA , ICHIKAWA KATSUMI , TABATA AKIFUMI , KUNITAKE HIROYUKI
IPC分类号： H04N5/91
摘要： PROBLEM TO BE SOLVED: To record the amplitude and level of entire video signal while exactly adjusting them into specified level when recording an additional signal while superimposing it by providing a signal superimposing circuit for superimposing the additional signal at the specified level on the video signal before frequency modulation processing based on a control signal from the outside. SOLUTION: A video signal recording and reproducing integrated circuit device 1 forms the main circuit section of VTR, and a recording system circuit 100 and a reproducing system circuit 200 are formed while being integrated on the same semiconductor substrate. A signal superimposing circuit 110 at this recording system circuit 100 superimposes the additional signal at the specified level on the video signal, which is amplitude-controlled and level-controlled by an AGC circuit 104 and a synchronizing clamp circuit 108, based on a superimpose control signal Sc1 from the outside. The superimpose control signal Sc1 is generated based on the plotting information of characters or the like by an external signal superimpose control circuit 402 and arbitrarily inputted through an external terminal P1 at the integrated circuit device 1.

6. 发明专利

JPH07322291A VIDEO SIGNAL AMPLITUDE CONTROL CIRCUIT 失效
公开(公告)号：JPH07322291A
公开(公告)日：1995-12-08
申请号：JP13643294
申请日：1994-05-26
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： TAKEBUCHI KENJI , HORI HIROYUKI , NAKAGAWA TADASHI , YAMAMOTO MOROHISA , KANESHIRO KATSUMI
IPC分类号： H04N5/91 , H04N9/793
摘要： PURPOSE:To eliminate the need for adjustment of a signal amplitude using a variable resistor by controlling automatically an amplitude of the video signal with high accuracy and high reproducibility. CONSTITUTION:A variable gain amplifier circuit 3 varies simultaneously a DC voltage and an amplitude of a luminance signal and gives them to a voltage detection circuit 21 and a voltage detection circuit 58. The voltage detection circuit 21 generates a DC voltage control signal 9 so that a DC voltage VDC 1 and a tip potential of a synchronizing signal of an output video signal are coincident with each other based on a clamp pulse signal 20. The voltage detection circuit 58 generates a signal resulting from superimposing a signal amplifying a voltage between an output video signal and the voltage VDC 1 onto the DC voltage VDCI at an amplifier circuit 8. A charge discharge current corresponding to the voltage between an output of the amplifier circuit 8 and the DC voltage VDC 2 is generated by a voltage current conversion circuit 12, outputted to a capacitor 19 to control the gain of the variable gain amplifier circuit 3 so that the charge / discharge current to the capacitor 19 is made zero.

7. 发明专利

JPH0548355A ELECTRONIC VOLUME 失效
公开(公告)号：JPH0548355A
公开(公告)日：1993-02-26
申请号：JP22349491
申请日：1991-08-08
申请人： HITACHI LTD , HITACHI MICOM SYST KK
发明人： TAKEBUCHI KENJI , NAKAGAWA TADASHI , KANESHIRO KATSUMI , SATO TETSUO
IPC分类号： H03G3/10 , H03G3/20 , H03G3/30
摘要： PURPOSE:To control digitally the transmission quantity of the electronic volume accurately with excellent reproducibility by using a generating source for a control reference voltage at the side of an electronic volume circuit and a conversion reference voltage at the side of a D/A converter circuit generating a control voltage in common. CONSTITUTION:A control reference voltage Vref1 at the side of the electronic volume circuit 1 and a conversion reference voltage Vref2 at the side of a D/A converter circuit 2 are used in common. Thus, the frequency in the characteristics of the circuits 1,2 is interlocked with each other. Thus, the characteristic fluctuation values are canceled together. Then the transfer quantity of the electronic volume is digitally controlled accurately with excellent reproducibility. Furthermore, The circuits 1,2 are integrated and formed on one and same semiconductor substrate 100 to allow the fluctuation values of the transfer quantity due to the characteristic fluctuation of components such as transistors(TRs) and resistors or the like to be interlocked with each other thereby suppressing the fluctuation small.

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