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1. 发明专利

JP2002334927A METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2002334927A
公开(公告)日：2002-11-22
申请号：JP2001140822
申请日：2001-05-11
申请人： HITACHI LTD , HITACHI TOKYO ELECTRONICS
发明人： SAIKAWA KENJI , MAENO RYOHEI , OKUDAIRA SADAYUKI , SAITO TETSUO , TAMARU TAKESHI , OMORI KAZUTOSHI
IPC分类号： H01L23/522 , H01L21/3213 , H01L21/768 , H01L21/8238 , H01L27/08 , H01L27/092
摘要： PROBLEM TO BE SOLVED: To improve reliability of semiconductor devices by reducing the charge-up damage to substrates, in a manufacturing process using plasma. SOLUTION: An insulation film 22 is formed on the reverse side of the substrate 11, prior to a process for forming a first wiring layer. In this way, charges generated on the substrate 11 are prevented from flowing to the ground potential through the substrate 11, even when a plasma CVD method, a sputter method or a dry etching method is used in the wiring forming process afterward, and damages to the substrate 11 due to the charge-up are prevented.

2. 发明专利

JP2002270605A METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2002270605A
公开(公告)日：2002-09-20
申请号：JP2001069013
申请日：2001-03-12
申请人： HITACHI LTD , HITACHI TOKYO ELECTRONICS
发明人： MAENO RYOHEI , SAIKAWA KENJI , SAITO TETSUO , OKUDAIRA SADAYUKI , TAMARU TAKESHI , OMORI KAZUTOSHI
IPC分类号： H01L21/3213 , H01L21/316 , H01L21/318 , H01L21/8238 , H01L27/08 , H01L27/092 , H01L27/12
摘要： PROBLEM TO BE SOLVED: To enhance reliability of a semiconductor device by reducing damages due to a charging-up operation to a semiconductor substrate, in a manufacturing process which uses plasma. SOLUTION: An insulation film 11 is formed on the rear surface of the semiconductor substrate 1. Thereby, electric charge generated on the semiconductor substrate 1 in a plasma CVD reaction used to form a silicon oxide film 12 is suppressed to flow to a ground potential through the semiconductor substrate 1, and breakdown of the gate insulation film 5 of a MISFET caused by the charging-up operation can be prevented.

3. 发明专利

JP2003213421A SUBSTRATE TREATMENT APPARATUS 审中-公开
公开(公告)号：JP2003213421A
公开(公告)日：2003-07-30
申请号：JP2002011135
申请日：2002-01-21
申请人： HITACHI INT ELECTRIC INC , HITACHI LTD
发明人： WADA TETSUYA , SAKUMA HARUNOBU , ANDO TOSHIO , TAMARU TAKESHI
IPC分类号： C23C16/44 , C23C16/455 , C23C16/46 , H01L21/205 , H01L21/285
摘要： PROBLEM TO BE SOLVED: To reduce the maintenance cost, and to easily control the temperature of a surface being in contact with gas. SOLUTION: An exhaust port 2 is formed in a furnace body 1, a shower plate 5 having a large number of holes is provided on an upper part of the furnace body 1, a heater unit 20 is provided on the furnace body 1 in an elevating/lowering manner, a wafer carrying port 3 to carry a semiconductor wafer 13 into a reaction chamber 21 and carry it out from the reaction chamber 21 is formed in the furnace body 1, a cylindrical wall surface heater 15 is provided on a face side of an inner wall of the reaction chamber 21, a cylindrical protective cover 16 is provided on the inner side of the wall surface heater 15, a wall surface heater 17 is provided on the heater unit 20, and a cylindrical protective cover 18 is provided on the outer side of the wall surface heater 17. COPYRIGHT: (C)2003,JPO

4. 发明专利

JP2002343854A SAMPLE MOUNTING BASE AND SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2002343854A
公开(公告)日：2002-11-29
申请号：JP2001145770
申请日：2001-05-16
申请人： HITACHI LTD
发明人： HIRASAWA SHIGEKI , MISE NOBUYUKI , TAMARU TAKESHI , OKUDAIRA SADAYUKI , OMORI KAZUTOSHI
IPC分类号： H05H1/46 , C23C14/50 , C23C16/458 , H01L21/68 , H01L21/683 , H02N13/00
摘要： PROBLEM TO BE SOLVED: To provide a cooling medium passage structure capable of achieving a uniform temperature distribution in a wafer with regard to the cooling medium passage structure of an electrostatic chuck in a plasma apparatus used in manufacturing a semiconductor for carrying out the etching and the thin film formation, etc., on the wafer surface. SOLUTION: The passage is formed toward the peripheral part at the shortest distance from a cooling medium supply port 13 positioned on the center side of the electrostatic chuck 2. Then, a meandering passage is formed from the peripheral part toward the center side while repeating nearly one round about the electromagnetic chuck 2 to be connected to a central exhaust port 14. Further, a gas is made to flow through the clearance between the electrostatic chuck 2 and the wafer 3 in the radially outward direction. Thus, the temperature in the wafer and the plasma process rate can be made uniform so that the fraction defective of the semiconductor device can be reduced.

5. 发明专利

JPH11297951A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD FOR MANUFACTURING IT 失效
公开(公告)号：JPH11297951A
公开(公告)日：1999-10-29
申请号：JP15382298
申请日：1998-05-18
申请人： HITACHI LTD
发明人： KAWAKAMI HIROSHI , SAITO MASAYOSHI , NAKAMURA YOSHITAKA , KAWAKITA KEIZO , YAMADA SATORU , SEKIGUCHI TOSHIHIRO , TADAKI YOSHITAKA , FUKUDA TAKUYA , TOKUNAGA TAKAFUMI , ASANO ISAMU , YOSHIDA MAKOTO , TAMARU TAKESHI , GOSHIMA HIDEKAZU , KUMAUCHI TAKAHIRO , UMEZAWA TADASHI , MITSUYA HARUHITO
IPC分类号： H01L21/8242 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To detect the signal stored in an information storage capacity element with high sensitivity by preventing a parasitic capacity of bit line from increasing, related to a DRAM where memory cell size is finer. SOLUTION: By allowing the width of a bit line BL narrower than a minimum work dimension which is decided by the resolution limit of photo-lithography, a parasitic capacity formed between adjoining bit lines is reduced. In order to make the width of the bit line BL more minute, a photo-resist film 43 is cut by ashing using ozone so that the width of a bit line pattern 43a is narrower than a minimum work dimension.

6. 发明专利

JPH11238862A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH11238862A
公开(公告)日：1999-08-31
申请号：JP31141298
申请日：1998-10-30
申请人： HITACHI LTD
发明人： NAKAMURA YOSHITAKA , AOKI HIDEO , FUKUDA NAOKI , GOSHIMA HIDEKAZU , ASANO ISAMU , KAWAKITA KEIZO , YAMADA SATORU , TAMARU TAKESHI , KOBAYASHI NOBUYOSHI , UMEZAWA TADASHI , OHIRA YOSHIKAZU
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/8242 , H01L23/52 , H01L27/10 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To prevent the transverse etching of a silicide film of a connection part between a bit line and a polycrystalline silicon plug by preventing the unevenness of a polycrystalline silicon plug in a bit line connection hole. SOLUTION: A bit line BL, formed simultaneously with a first layer wiring 18, is made of a laminated film of a titanium film 18a, a titanium nitride film 18b and a tungsten film 18c, and a titanium silicide film 20 containing nitrogen or oxygen is formed in a connection part between the bit line BL and a plug 19. A titanium silicide film 2 containing nitrogen or oxygen may be also formed in a connection part between the first layer wiring 18 and a semiconductor board 1. A tungsten silicide layer containing nitrogen or oxygen, a cobalt silicide layer containing nitrogen or oxygen or a cobalt silicide layer may be formed in place of the titanium silicide film 20.

7. 发明专利

JPH09246377A MANUFACTURE OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MANUFACTURE DEVICE USED THEREFOR 失效
公开(公告)号：JPH09246377A
公开(公告)日：1997-09-19
申请号：JP5018096
申请日：1996-03-07
申请人： HITACHI LTD
发明人： SAIKAWA KENJI , TAMARU TAKESHI
IPC分类号： C23C16/02 , C23C16/46 , C23C16/511 , C23F4/00 , H01L21/205 , H01L21/31 , H01L21/316 , H01L21/768 , H01L23/522
摘要： PROBLEM TO BE SOLVED: To enable an insulating film formed through a high-density plasma CVD method and a metal interconnection film to be surely bonded together. SOLUTION: The surface 2a of a first interconnection layer 2 of tungsten or the like formed on a semiconductor wafer 1 is etched as far as 200Å or so through an argon sputtering method, and the oxidized surface 2a of the first interconnection layer 2 is removed. By this setup, an insulating film 11 is formed after the activated surface 2b of the interconnection layer 2 is exposed.

8. 发明专利

JPH08241968A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH08241968A
公开(公告)日：1996-09-17
申请号：JP6404596
申请日：1996-03-21
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SUGIURA JUN , TSUCHIYA OSAMU , OGASAWARA MAKOTO , OTSUKA FUMIO , TORII KAZUNARI , ASANO ISAMU , OWADA NOBUO , HORIUCHI MITSUAKI , TAMARU TAKESHI , AOKI HIDEO , OTSUKA NOBUHIRO , SHIRAI SEIICHIRO , SAGAWA MASAKAZU , IKEDA YOSHIHIRO , KAGA TORU , TSUNEOKA MASATOSHI , NIINA TOMOJI , OGISHI HIDEJI , KASAHARA OSAMU , ENAMI HIROMITSU , WAKAHARA ATSUSHI , AKIMORI HIROYUKI , SUZUKI SHINICHI , FUNATSU YOSHIAKI , KAWASAKI YOSHINAO , TSUBONE TSUNEHIKO , KOGANO MASAYOSHI , TSUGANE MASARU
IPC分类号： H01L21/76 , H01L21/8242 , H01L27/08 , H01L27/108 , H01L29/78
摘要： PURPOSE: To obtain a semiconductor integrated circuit device which enhances the junction breakdown strength of a substrate to an element and which reduces a leakage current amount at the junction part of the substrate to the element by a method wherein an active region is not arranged in the boundary region between a first channel stopper region and a second channel stopper region. CONSTITUTION: In a DRAM, a memory cell and an n-channel MISFET in a peripheral circuit are arranged respectively on main faces inside respective different active regions in a p-type well region which is prescribed by a p-type channel stopper region formed on the main face of an inactive region in the p-type well region. Here, a p-type channel stopper region 25A which surrounds the circumference of the memory cell and an n-channel stopper region 24 in the peripheral circuit are constituted independently in separate manufacturing processes. Then, an active region Act such as the memory cell, the n-channel MISFET or the like in the peripheral circuit are not arranged in the boundary region between the p-type channel stopper region 25A and the n-type channel region 24.

9. 发明专利

JPH04206526A METHOD OF FILLING IN THROUGH HOLE WITH METAL 失效
公开(公告)号：JPH04206526A
公开(公告)日：1992-07-28
申请号：JP32909590
申请日：1990-11-30
申请人： HITACHI LTD
发明人： TSUJIKU SUSUMU , NISHITANI EISUKE , TOKUNAGA TAKAFUMI , TAMARU TAKESHI
IPC分类号： C23C16/04 , C23C16/06 , H01L21/3205
摘要： PURPOSE:To enhance the selectivity and the conductivity between an exposed underneath metal and a metal for filling in a hole by a method wherein a part of underneath metal of a substrate exposed from an insulating film is light-etched using ClF3 gas and then selectively CVD processed without exposing it to the atmosphere. CONSTITUTION:A substrate 2 is arranged on a substrate heating state 5 in a processing chamber 1. Next, an SiO2 film 15 as an insulating film is formed by plasma CVD step on an Al wiring 14 as an underneath metal on the substrate 2 and then a through hole 16 is made in the SiO2 film 15. At this time, a natural oxide film 17 is bonded onto the Al wiring 14 in the through hole 16. Next, the processing chamber 1 is exhausted and then the substrate 2 is heated by a heater 5a. Next, ClF3 gas is led in the chamber 1 so as to light-etch the surface of the insulating film 15 and the film 17. Next, the leading-in step of the ClF3 gas is stopped and then the evacuation step is cased. Next, the substrate 2 not-exposed to atmosphere is carried to a film formation chamber 7 by a carrier and then a gate valve 6 is closed while another substrate 2a is mounted on a supporting body 10. Next, the film formation chamber 7 is exhausted, He is led in, the infrared rays emitted from halogen lamps 8 are projected on the substrate 2a to be heated, WF6 gas is led-in and finally the through hole 16 is filled in with W18.

10. 发明专利

JPH02299267A MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH02299267A
公开(公告)日：1990-12-11
申请号：JP12078089
申请日：1989-05-15
申请人： HITACHI LTD
发明人： OWADA NOBUO , KASAHARA OSAMU , ASANO ISAMU , TAMARU TAKESHI
IPC分类号： H01L29/73 , H01L21/28 , H01L21/331 , H01L29/40 , H01L29/732
摘要： PURPOSE:To enable the miniaturization of a bipolar LSI and to enable it to operate at a high speed by a method wherein an opening is provided to a part of an element isolation insulating film adjacent to the base diffusion layer of the bipolar transistor to form a collector lifting layer. CONSTITUTION:An opening is provided to an element isolation insulating film 6 in contact with insulating films 15 and 10 and a base diffusion layer 8 through etching to form a contact hole 16c whose base reaches to a collector buried layer 2, and then a collector lifting layer 19 is formed by filling a tungsten film into the contact hole 18c. A barrier metal layer 20 and an aluminum film 21 are successively deposited thereon, which is etched to form a base electrode 22, an emitter electrode 23, and a collector electrode 24. In this case, the space between the base diffusion layer 8 and the collector lifting layer 19 can be made small and the collector lifting layer 19 small in resistance can be obtained. By this setup, a bipolar transistor of this design can be miniaturized and made to operate at a high speed.

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