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1. 发明专利

JPH0321127A OPTICAL SUBSCRIBER'S LINE MONITORING SYSTEM IN OPTICAL DISTRIBUTION SYSTEM 失效
公开(公告)号：JPH0321127A
公开(公告)日：1991-01-29
申请号：JP15454689
申请日：1989-06-19
申请人： HITACHI LTD
发明人： TAKANO MITSUHIRO
IPC分类号： H04B10/07 , H04B10/071 , H04B10/079 , H04B10/272
摘要： PURPOSE:To monitor a fault in an optical subscriber's line in optical distribution type service by branching an optical signal from the home side by an optical directional coupler and monitoring a branched optical signal on an optional line with a light receiving device and an electric selector. CONSTITUTION:An optical signal 5 from an intra-office light transmitter 1 is received by an intra-home light receiver 3 and an upward reflected light signal is branched with the optical directional coupler 6. When N home side equipments exist, N branched optical signals are inputted to a line monitoring device 7. When an upward optical signal is transmitted from the home side, the upward optical signal is branched at minimum required by an optical directional coupler 6 and the demultiplexed light beams are inputted to a line monitoring device 7. The inputted N demultiplexed beams are converted into electric signals by photodetectors 9 corresponding to the number of demultiplexed beams, one of the electric signals is selected by the electric selector 11 and the selected electric signal is monitored by a monitoring part to monitor the optional line. At this time, a line selection controller 11 outputs a specific line selecting signal, controls N light receiving device 9 and drives only the light receiving 9 connected to a specified line. Thus, electric conversion or the selector 12 is controlled to monitor the specific line.

2. 发明专利

JPS6482399A TEST SYSTEM FOR STORED CAPACITY IN SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPS6482399A
公开(公告)日：1989-03-28
申请号：JP23724487
申请日：1987-09-24
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： KASAMA YASUHIRO , OSHIMA KAZUYOSHI , KAJITANI KAZUHIKO , YAMAZAKI TAKASHI , TAKANO MITSUHIRO
IPC分类号： G11C11/413 , G11C11/34 , G11C11/401 , G11C29/00 , G11C29/56
摘要： PURPOSE:To detect that a stored capacity does not reach an expected value by leaking the holding charge of a memory cell to be tested in which prescribed data is written to a data line during the non-selection period of a word line and controlling the reading signal level of the holding charge. CONSTITUTION:When the word lines W1-Wn are not selected, a selecting signal S for turning on the selecting MOSFETQ1 of respective memory cells MC is supplied from a testing pad Ptest. The time is shorter than a time for leaking the charge of the required quantity for inverting the holding data of the stored capacity Cs satisfying the expected value of the capacity to the data line DL and longer than a time for leaking the charge of the quantity required for inverting the holding data of the stored capacity Cs satisfying no expected value to the data line DL. Therefore, the data held by the stored capacity Cs satisfying no expected value is inverted to the data of a low level. Thereby, it is detected that the stored capacity does not reach the expected value.

3. 发明专利

JPH1127210A OPTICAL OUTPUT DISCONNECTION DETECTION CIRCUIT 失效
公开(公告)号：JPH1127210A
公开(公告)日：1999-01-29
申请号：JP17702397
申请日：1997-07-02
申请人： HITACHI LTD
发明人： SUZUKI MUNETOSHI , FURUKAWA MASAAKI , TAKANO MITSUHIRO , ARAI TAKATERU
IPC分类号： H03K17/78 , H04B10/032 , H04B10/07 , H04B10/079 , H04B10/112 , H04B10/40 , H04B10/50 , H04B10/524 , H04B10/556 , H04B10/564 , H04B10/60 , H04B10/08 , H04B10/00 , H04B10/04 , H04B10/06 , H04B10/14 , H04B10/26 , H04B10/28
摘要： PROBLEM TO BE SOLVED: To instantaneously detect an optical output disconnection in case of deterioration of a light emitting element light output in an optical transmission line of burst signals. SOLUTION: An optical output signal 9 from a light emitting element 2 driven by a light emitting element operating circuit 1, to which a transmission signal 8 of a burst state is inputted, is received by a light output monitoring detector 3 for a light emitting element. Its output signal 10 is outputted as an output signal 11 whose polarities are reversed for transmission period and non-transmission period by a monitoring signal instantaneous peak detection circuit 4. An amplifier discrimination circuit 5 compares the output signal 11 with a set value of a reference voltage source 6 and outputs an output signal 12 of a fixed amplitude when a level of the output signal 11 is higher than the set value of the reference voltage source 6. This output signal 12 and a burst gate signal 13 for outputting the transmission period as a low level and non-transmission period a high level are inputted to a NAND circuit 7 for logical discrimination and their output becomes an optical output disconnection detection signal 14.

4. 发明专利

JPH09107081A SEMICONDUCTOR MEMORY AND SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH09107081A
公开(公告)日：1997-04-22
申请号：JP8991096
申请日：1996-03-21
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： KAJITANI KAZUHIKO , YAMAGUCHI YASUNORI , OSHIMA KAZUYOSHI , YAMAZAKI TAKASHI , MIYAMOTO EIJI , SAKAI YUJI , SAWADA JIRO , ETO JUN , HORIGUCHI SHINJI , IKENAGA SHINICHI , KUMADA ATSUSHI , TSUNOSAKI MANABU , KASAMA YASUHIRO , UDO SHINJI , YOSHIOKA HIROSHI , SAITO HIROMI , TAKANO MITSUHIRO , MORINO MAKOTO , MIYATAKE SHINICHI , MATSUMOTO TETSUO
IPC分类号： G11C11/41 , G11C11/401 , H01L21/82 , H01L21/8242 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To provide a highly integrated device with high speed, by forming a peripheral circuit in first and second regions and providing a plurality of bonding pads on the first region in a zigzag form along the first region for connecting a semiconductor substrate and the outside. SOLUTION: A memory array is formed in a four-sectional area made of cross-shaped areas A to E. Then, a Y-decoder(Ydec) and a Y-select driver (YS driver) are provided according to the upper and lower arrays made in a pair. An X-decoder(Xdec) is put in the area of C and a word line driver (WL driver) is put in the area of D. An address buffer and the like are put in the areas A and B, a common source switch circuit and the like are put in the area of C and D, and an address signal generating circuit for the X-decoder and Y decoder is put in the central area of E. In this way, a large-size semiconductor device can be realized.

5. 发明专利

JPH05252191A 失效
公开(公告)号：JPH05252191A
公开(公告)日：1993-09-28
申请号：JP5006092
申请日：1992-03-06
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE , FUJITSU LTD
发明人： SHINADA SHIGEO , TAKANO MITSUHIRO , YAMANAKA NAOAKI , SATO YOICHI , IGUCHI KAZUO , TAKEO HIROSHI , KUSAYANAGI MICHIO , OGURA TAKAO
IPC分类号： H04Q3/00 , G06F19/00 , H04L12/28 , H04L12/813 , H04L12/48 , G06F15/48
摘要： PURPOSE:To provide a polishing circuit with a self-operating counter which can obtain arrival intervals by a simple processing and a little increase of hardwares. CONSTITUTION:This circuit is provided with a cell detector 2 which receives a cell and detects the user identification number, a decision comparator 4 which decides illegal arrival when the arrival interval between the current arrival and arrival before the permissible number X of cells is less than a specific monitor time and normal arrival when the arrival interval is larger, the self- operating counter 5 which cyclically counts up to a specific maximum value T0, a resettable status counter 8 which counts the overflow frequency of the counter 5, and a stamp memory part 11 which is stored with the counted values of the self-operating counter 5 and status counter 8 corresponding to user identification numbers. The comparing decision unit 4 decides the arrival interval between the time of the current arriving cell and the cell which is X cells before from the respective counted values.

6. 发明专利

JPH05219093A METHOD AND CIRCUIT FOR POLISHING 失效
公开(公告)号：JPH05219093A
公开(公告)日：1993-08-27
申请号：JP2097492
申请日：1992-02-06
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： TAKASE MASAHIKO , SHINADA SHIGEO , TAKANO MITSUHIRO , OUCHI TOSHIYA , YAMANAKA NAOAKI , SATO YOICHI
IPC分类号： H04L12/813 , H04Q11/04
摘要： PURPOSE:To provide the polishing circuit for controlling the traffic which flows in violation of a report, and especially, the method for executing the detection of high accuracy by a simple constitution, in a network using an asynchronous transfer mode. CONSTITUTION:A VP/VC distributing circuit 2 distributes an ATM cell from an entry interface 1 to a traffic monitor circuit block 3 in accordance with a virtual path identifier or a virtual channel identifier. Plural counters 4-1 and 4-2 of the circuit block 3 are reset in a period T, and also, with a time shift of T/2, respectively. Comparators 5-1, 5-2 compare a counting value of each corresponding counter 4-1, 4-2 with a threshold X, and give an instruction to a rejection control circuit 9, when the counting value of either counter exceeds the value of X. Accordingly, the burst detection capacity of the polishing circuit can be doubled by a simple constitution, and the network can be utilized effectively.

7. 发明专利

JPH05191433A FAULT DIAGNOSTIC SYSTEM FOR UPC CIRCUIT 失效
公开(公告)号：JPH05191433A
公开(公告)日：1993-07-30
申请号：JP302292
申请日：1992-01-10
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE , HITACHI LTD
发明人： AMAMIYA SHIGEO , OGURA TAKAO , NAKAJO TAKAFUMI , TAKEO HIROSHI , KUSAYANAGI MICHIO , YAMANAKA NAOAKI , SATO YOICHI , TAKASE MASAHIKO , SHINADA SHIGEO , TAKANO MITSUHIRO , SAITO KIYOSHI , HOBARA KAZUHIKO , OKABE TETSUHIRO
IPC分类号： G06F11/20 , H04L12/70 , H04L12/813
摘要： PURPOSE:To provide the fault diagnostic synchronizing signal for a UPC circuit diagnosing properly a fault of the UPC circuit. CONSTITUTION:The fault diagnostic synchronizing signal for a UPC circuit controlling a cell flow based on specified information with respect to a cell traffic is provided with an active system UPC circuit W applying policing control to m-kinds of cells and a standby system UPC circuit P applying policing control to n-kinds of cells, decides policing by 2 systems or over with respect to one kind of cell or over and compares the result of decision to diagnose a fault of the UPC circuit. Furthermore, the traffic is measured by 2 systems or over with respect to one kind of cell or over and the fault of the UPC circuit is diagnosed by comparing the traffic measured values. Furthermore, q-sets of bridge memories storing prescribed information of the arrived cells in time series are provided and a fault of the bridge memory is diagnosed by comparing the content of the bridge memory by 2 systems or over.

8. 发明专利

JPH01309539A BIT PHASE ABSORPTION CIRCUIT 失效
公开(公告)号：JPH01309539A
公开(公告)日：1989-12-13
申请号：JP13931788
申请日：1988-06-08
申请人： HITACHI LTD , HITACHI COMMUNICATION SYSTEM
发明人： KAMIMURA YUJI , TAKANO MITSUHIRO
IPC分类号： H03K5/00 , H04J3/06 , H04L7/00
摘要： PURPOSE:To facilitate large scale circuit integration by comparing an output signal from an input system timing generating circuit with an output signal from an output system timing generating circuit and controlling a timing signal from the output system timing generating circuit based on the result of comparison. CONSTITUTION:The input system timing generating circuit 9 generates a timing control signal to apply time division demultiplex to a serial signal being in input data and an input system storage circuit demultiplexes the serial signal by using the timing signal from the input system timing generating circuit 9 synchronously with the input phase. An output system timing generating circuit 10 generates a timing signal to apply time division multiplex to a parallel signal demultiplexed in time division. The output system storage circuit and a multiplex circuit 11 multiplex the parallel signal in time division by using a timing signal from the output system timing generating circuit 10 synchronously with the output phase. A comparator circuit 12 compares the phases of the timing signals in the input and output systems to control the output system timing signal. Thus, the large scale circuit integration is facilitated.

9. 发明专利

JPH01145853A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH01145853A
公开(公告)日：1989-06-07
申请号：JP30319387
申请日：1987-12-02
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： KASAMA YASUHIRO , OSHIMA KAZUYOSHI , TAKANO MITSUHIRO , KOMATSU NOBUO , UDO SHINJI
IPC分类号： H01L27/10 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/108
摘要： PURPOSE:To decrease the occurring rate of soft errors in a memory cell mode and a bit line mode, by providing a potential barrier layer beneath the memory cell in a DRAM and beneath a semiconductor region, which is connected to a bit line, and not providing a potential barrier layer beneath a MISFET. CONSTITUTION:A p-type potential barrier layer 4B is constituted at a lower part of a memory cell M. The potential barrier layer 4B is formed beneath the entire surface of the memory cell M, i.e., at the entire surface of a memory cell array MA. The potential barrier layer 4B can be provided at least beneath a data storing capacitor element C of the memory cell M. The potential barrier layer 4B forms a potential barrier against minority carriers, which are generated by incident alpha rays within a semiconductor substrate 1. The potential barrier layer 4B is constituted so as to block the intrusion of the minority carriers into the data storing capacitor element C and so as to decrease the occurring rate of soft errors in a memory cell mode. The potential barrier layer 4B is also constituted so as to increase the charge storing capacity of the data storing capacitor element.

10. 发明专利

JPS6243232A MULTIPLEX SIGNAL DEMODULATOR 失效
公开(公告)号：JPS6243232A
公开(公告)日：1987-02-25
申请号：JP18176685
申请日：1985-08-21
申请人： HITACHI LTD
发明人： TAKANO MITSUHIRO , MIYAMORI YOSHIO
IPC分类号： H04J1/08
摘要： PURPOSE:To attain the reception and demodulation for the FM music broadcast, the high-grade TV broadcast and the TV broadcast of the NTSC, PAL and SECOM systems, etc., by combining the suitable demodulators in an input VHF signal system and according to the contents of each system. CONSTITUTION:For the VHF signal inputs of (n) types of systems, a demodulator 1 extracts (n) types of IF signals out of a multi-IF output tuner 2. Then the signal waves can be received and transmitted according to each signal and regardless of the modulation system by (n) types of band pass filters BPF4-6, demodulators 7-9 and output devices 10-12. This can improves greatly the defects of the conventional system where just a single modulator is used to a single broadcast signal.

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